74163244APAG

IDT74FCT163244A RENESAS | Alldatasheet

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3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 IDT74FCT163244A/C INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUFFER/LINE DRIVER The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2009 Integrated Device Technology, Inc. DSC-2532/12 FEATURES:

• 0.5 MICRON CMOS Technology  Typical t SK(o) (Output Skew) < 250ps  ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) V CC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range  CMOS power levels (0.4 μ μ μ μ μ W typ. static)  Rail-to-rail output swing for increased noise margin  Low Ground Bounce (0.3V typ.)  Inputs (except I/O) can be driven by 3.3V or 5V components  Available in SSOP, TSSOP, and TVSOP packages FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The FCT163244 16-bit buffer/line drivers are built using advanced dual metal CMOS technology. These high-speed, low-power devices offer bus/ backplane interface capability with improved packing density. These devices have a flow-through organization for simplifying board layout. The three-state controls operate these devices in a Quad-Nibble, Dual-Byte or single 16-bit word mode. All inputs are designed with hysteresis for improved noise margin. The inputs of the FCT163244 can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V supply system. Thus, the FCT163244 can be used as buffers to connect 5V components to a 3.3V bus. 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 1Y1 1Y2 1Y3 1Y4 1A1 1A2 1A3 1A4 1OE 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4

INDUSTRIAL TEMPERATURE RANGE IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER SSOP/ TSSOP/ TVSOP TOP VIEW PIN CONFIGURATION Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to 7 V VTERM(4) Terminal Voltage with Respect to GND –0.5 to V CC+0.5 V TSTG Storage Temperature –65 to +150 ° C IOUT DC Output Current –60 to +60 mA ABSOLUTE MAXIMUM RATINGS(1)(1)(1)(1)(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals. Pin Names Description xOE 3-State Output Enable Inputs (Active LOW) x A x Data Inputs x Y x 3-State Outputs PIN DESCRIPTION NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance Inputs Outputs xOE xAx xYx LL L LH H HX Z FUNCTION TABLE(1) 1Y1 GND 1Y3 VCC GND 3Y2 GND VCC GND 1Y2 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y3 3Y4 4Y1 4Y3 4Y4 4Y2 4OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 VCC 4A1 4A3 4A4 4A2 GND GND GND 2OE 3OE 1OE Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance V IN = 0V 3.5 6 pF COUT Output Capacitance V OUT = 0V 3.5 8 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested.

3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2 — 5.5 V Input HIGH Level (I/O pins) 2 — V CC+0.5 VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level –0.5 — 0.8 V IIH Input HIGH Current (Input pins) V CC = Max. V I = 5.5V — — ±1 Input HIGH Current (I/O pins) V I = VCC —— ±1µ A IIL Input LOW Current (Input pins) V I = GND — — ±1 Input LOW Current (I/O pins) V I = GND — — ±1 IOZH High Impedance Output Current V CC = Max. V O = VCC —— ±1µ A IOZL (3-State Output pins) V O = GND — — ±1 VIK Clamp Diode Voltage V CC = Min., IIN = –18mA — –0.7 –1.2 V IODH Output HIGH Current V CC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA IODL Output LOW Current V CC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 90 200 mA VOH Output HIGH Voltage V CC = Min. I OH = –0.1mA V CC-0.2 — — VIN = VIH or VIL IOH = –3mA 2.4 3 — V VCC = 3V I OH = –8mA 2.4 (5) 3— VIN = VIH or VIL VOL Output LOW Voltage V CC = Min. I OL = 0.1mA — — 0.2 VIN = VIH or VIL IOL = 16mA — 0.2 0.4 IOL = 24mA — 0.3 0.55 V VCC = 3V I OL = 24mA — 0.3 0.5 VIN = VIH or VIL IOS Short Circuit Current(4) VCC = Max., V O = GND(3) –60 –135 –240 mA VH Input Hysteresis — — 150 — mV ICCL Quiescent Power Supply Current V CC = Max. — 0.1 10 µ A ICCH VIN = GND or VCC ICCZ DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: T A = –40°C to +85°C, VCC = 2.7V to 3.6V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. V OH = V CC–0.6V at rated current.

INDUSTRIAL TEMPERATURE RANGE IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ΔICC Quiescent Power Supply Current V CC = Max. — 2 30 µ A TTL Inputs HIGH V IN = VCC - 0.6V(3) ICCD Dynamic Power Supply V CC = Max. V IN = VCC — 5 0 7 5 µA/ Current(4) Outputs Open V IN = GND MHz xOE = GND One Input Togging 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. V IN = VCC — 0.5 0.8 mA Outputs Open V IN = GND fi = 10MHz 50% Duty Cycle V IN = VCC - 0.6V — 0.5 0.8 xOE = GND V IN = GND One Bit Toggling VCC = Max. V IN = VCC —2 3 (5) Outputs Open V IN = GND fi = 2.5MHz 50% Duty Cycle xOE = GND V IN = VCC - 0.6V — 2 3.3 (5) Sixteen BitsTogging V IN = GND POWER SUPPLY CHARACTERISTICS NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 3.3V, +25°C ambient. 3. Per TTL driven input. All other inputs at V CC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested. 6. I C = IQUIESCENT + IINPUTS + IDYNAMIC IC = I CC + ΔICC DHNT + I CCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (I CCL, ICCH and I CCZ) ΔICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D H ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at f CP fi = Input Frequency Ni = Number of Inputs at fi FCT163244A FCT163224C Symbol Parameter Cond ition(2) Min.(3) Max. Min.(3) Max. Unit tPLH Propagation Delay C L = 50pF 1.5 4.8 1.5 4.1 ns tPHL xAx to xYx R L = 500Ω tPZH Output Enable Time 1.5 6.2 1.5 5.8 ns tPZL tPHZ Output Disable Time 1.5 5.6 1.5 5.2 ns tPLZ tSK(o) Output Skew(4) — 0.5 — 0.5 ns SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) NOTES: times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE Pulse Generator R T D.U.T VCC VIN C L VOUT 50pF 500 Ω 500 Ω Open GND 1.5V 1.5V 1.5V 1.5V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL CLEAR ETC. tSU tH tREM tSU tH PRESET CLEAR CLOCK ENABLE ETC. PRESET SYNCHRONOUS CONTROL HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 1.5V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 1.5V tPLH tPHL tPHL VOL CONTROL INPUT 1.5V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH SWITCH GND VOL 0.3V 0.3V tPLZtPZL tPZH tPHZ 1.5V 1.5V ENABLE DISABLE VOH TEST CIRCUITS AND WAVEFORMS Propagation Delay Test Circuits for All Outputs Enable and Disable Times Set-up, Hold, and Release Times Pulse Width Test Switch Open Drain Disable Low 6V Enable Low Disable High GND Enable High All Other Tests Open SWITCH POSITION DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator. NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 3. if V CC is below 3V, input voltage swings should be adjusted not to exceed V CC.

INDUSTRIAL TEMPERATURE RANGE IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER

ORDERING INFORMATION

Temp. Range XXXX Device Type X Package PVG PAG PFG Shrink Small Outline Package - Green Thin Shrink Small Outline Package - Green Thin Very Small Outline Package - Green 244A 244C Non-Inverting 16-Bit Buffer/Line Driver − 40°C to +85°C74 FCT XXX Family 163 Double-Density 3.3Volt Datasheet Document History 09/10/09 Pg.6 Updated the ordering information by removing the "IDT" notation and non RoHS part.

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