74163

74163 FAIRCHILD | Alldatasheet

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■ ICC reduced by 50% ■ Synchronous counting and loading ■ High-speed synchronous expansion ■ Typical count rate of 125 MHz ■ Outputs source/sink 24 mA ■ ACT163 has TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Order Number Package Number Package Description 74AC163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74AC163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide 74AC163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT163SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74ACT163SJ M16D 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT163PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Pin Names Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input SR Synchronous Reset Input P0–P3 Parallel Data Inputs PE Parallel Enable Input Q 0–Q 3 Flip-Flop Outputs TC Terminal Count Output

www.fairchildsemi.com 2 74AC163 • 74ACT163 Logic Symbols IEEE/IEC Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Functional Description The AC/ACT163 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transi- tion of the CP input signal. The circuits have four funda- mental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputs—Synchronous Reset (SR ), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (P n) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and SR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The AC/ACT163 uses D-type edge-triggered flip-flops and changing the SR , PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the rec- ommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchro- nous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to com- plete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim- its the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET SR PE CET CEP Action on the Rising Clock Edge (/c17 ) L X X X Reset (Clear) H L X X Load (P n → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold)

www.fairchildsemi.com 4 74AC163 • 74ACT163 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC . Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) −0.5V to VCC + 0.5V DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC + 0.5V DC Output Source or Sink Current (IO ) ±50 mA DC V CC or Ground Current per Output Pin (ICC or IGND ) ±50 mA Storage Temperature (TSTG ) −65°C to +150°C Junction Temperature (TJ) PDIP 140 °C Supply Voltage (VCC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I) 0V to V CC Output Voltage (VO ) 0V to V CC Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (ΔV/Δt) AC Devices V IN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (ΔV/Δt) ACT Devices V IN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Symbol Parameter VCC TA = +25°C T A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits 5.5 2.75 3.85 3.85 5.5 2.75 1.65 1.65 VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I OUT = −50 µA 5.5 5.49 5.4 5.4 VIN = VIL or VIH 3.0 2.56 2.46 I OH = −12 mA 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 2) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I OUT = 50 µA 5.5 0.001 0.1 0.1 VIN = VILor VIH 3.0 0.36 0.44 I OL = 12 mA 4.5 0.36 0.44 V I OL = 24 mA 5.5 0.36 0.44 I OL = 24 mA (Note 2) IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAV I = VCC , GND IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 4.0 40.0 µAV IN = VCC (Note 4) Supply Current or GND

5 www.fairchildsemi.com 74AC163 • 74ACT163 Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: Voltage Range 3.3 is 3.3V ±0.3V Voltage Range 5.0 is 5.0V ±0.5V Symbol Parameter VCC TA = +25°C T A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI OUT = −50 µA Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 5) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI OUT = 50 µA Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH 4.5 0.36 0.44 V I OL = 24 mA 5.5 0.36 0.44 I OL = 24 mA (Note 5) IIN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAV I = VCC , GND ICCT Maximum 5.5 0.6 1.5 mA V I = VCC − 2.1V ICC /Input IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 4.0 40.0 µAV IN = VCC Supply Current or GND VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 7) Min Typ Max Min Max fMAX Maximum Clock 3.3 70 95 60 MHz Frequency 5.0 110 140 95 ns ns ns ns ns ns

www.fairchildsemi.com 6 74AC163 • 74ACT163 AC Operating Requirements for AC Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Note 9: Voltage Range 5.0 is 5.0V ± 0.5V VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 8) Typ Guaranteed Minimum tS Setup Time, HIGH or LOW 3.3 5.5 13.5 16.0 ns Pn to CP 5.0 4.0 8.5 10.5 tH Hold Time, HIGH or LOW 3.3 −7.0 −1.0 −0.5 ns Pn to CP 5.0 −5.0 0 0 tS Setup Time, HIGH or LOW 3.3 5.5 14.0 16.5 ns SR to CP 5.0 4.0 9.5 11.0 tH Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 ns SR to CP 5.0 −5.5 −0.5 0 tS Setup Time, HIGH or LOW 3.3 5.5 11.5 14.0 ns PE to CP 5.0 4.0 7.5 8.5 tH Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 ns PE to CP 5.0 −5.0 −0.5 0 tS Setup Time, HIGH or LOW 3.3 3.5 6.0 7.0 ns CEP or CET to CP 5.0 2.5 4.5 5.0 tH Hold Time, HIGH or LOW 3.3 −4.5 0 0 ns CEP or CET to CP 5.0 −3.0 0 0.5 tW Clock Pulse Width (Load) 3.3 3.0 3.5 4.0 ns HIGH or LOW 5.0 2.0 2.5 3.0 tW Clock Pulse Width (Count) 3.3 3.0 4.0 4.5 ns HIGH or LOW 5.0 2.0 3.0 3.5 VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 9) Min Typ Max Min Max fMAX Maximum Clock Frequency 5.0 120 140 105 MHz tPLH Propagation Delay, CP to Qn (PE Input HIGH or LOW) tPHL Propagation Delay, CP to Qn (PE Input HIGH or LOW) tPLH Propagation Delay CP to TC tPHL Propagation Delay CP to TC tPLH Propagation Delay CET to TC tPHL Propagation Delay CET to TC

7 www.fairchildsemi.com 74AC163 • 74ACT163 AC Operating Requirements for ACT Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 10) Typ Guaranteed Minimum tS Setup Time, HIGH or LOW 5.0 4.0 10.0 12.0 ns Pn to CP tH Hold Time, HIGH or LOW Pn to CP tS Setup Time, HIGH or LOW 5.0 4.0 10.0 11.5 ns SR to CP tH Hold Time, HIGH or LOW SR to CP tS Setup Time, HIGH or LOW 5.0 4.0 8.5 10.5 ns PE to CP tH Hold Time, HIGH or LOW 5.0 −5.5 −0.5 0 ns PE to CP tS Setup Time, HIGH or LOW 5.0 2.5 5.5 6.5 ns CEP or CET to CP tH Hold Time, HIGH or LOW 5.0 −3.0 0 0.5 ns CEP or CET to CP tW Clock Pulse Width (Load) 5.0 2.0 3.5 3.5 ns HIGH or LOW tW Clock Pulse Width 5.0 2.0 3.5 3.5 ns (Count) HIGH or LOW Symbol Parameter Typ Units Conditions C IN Input Capacitance 4.5 pF V CC = OPEN CPD Power Dissipation Capacitance 45.0 pF V CC = 5.0V

www.fairchildsemi.com 8 74AC163 • 74ACT163 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A

9 www.fairchildsemi.com 74AC163 • 74ACT163 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com 10 74AC163 • 74ACT163 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

11 www.fairchildsemi.com 74AC163 • 74ACT163 Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com