SN54147_15 TI1 | Alldatasheet
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/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ’147, ’LS147 /C0068Encode 10-Line Decimal to 4-Line BCD /C0068Applications Include: − Keyboard Encoding − Range Selection ’148, ’LS148 /C0068Encode 8 Data Lines to 3-Line Binary (Octal) /C0068Applications Include: − n-Bit Encoding − Code Converters and Generators 321 2 0 1 9 91 01 11 21 3 D NC NC C NC A V NC B GND NC SN54LS147 ...F K PACKAGE (TOP VIEW) CC NC − No internal connection C B GND VCC NC D A SN54147, SN54LS147 ...J O R W PACKAGE SN74147, SN74LS147 ...D O R N PACKAGE (TOP VIEW) EI GND VCC GS SN54148, SN54LS148 ...J O R W PACKAGE SN74148, SN74LS148 . . . D, N, OR NS PACKAGE (TOP VIEW) 321 2 0 1 9 91 01 1 1 21 3 GS NC NC EI NC V GND NC SN54LS148 . . . FK PACKAGE (TOP VIEW) CC TYPE TYPICAL DATA DELAY TYPICAL POWER DISSIPATION ’147 10 ns 225 mW ’148 10 ns 190 mW ’LS147 15 ns 60 mW ’LS148 15 ns 60 mW NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54/74LS load, respectively.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74LS148N SN74LS148N 0°C to 70°C SOIC − D Tube SN74LS148D LS1480°C to 70°C SOIC − D Tape and reel SN74LS148DR LS148 SOP − NS Tape and reel SN74LS148NSR 74LS148 CDIP − J Tube SNJ54LS148J SNJ54LS148J −55°C to 125°C CFP − W Tube SNJ54LS148W SNJ54LS148W−55 C to 125C LCCC − FK Tube SNJ54LS148FK SNJ54LS148FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE − ’147, ’LS147 INPUTS OUTPUTS 1 2 3 4 5 6 7 8 9 D C B A H H H H H H H H H H H H H X XXXXXXXLL HHL X XXXXXXLHL HHH X XXXXXLHHH LLL X XXXXLHHHH LLH X XXXLHHHHH LHL X XXLHHHHHH LHH X XLHHHHHHH HLL X LHHHHHHHH HLH L H H H H H H H H H H H L H = high logic level, L = low logic level, X = irrelevant
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE − ’148, ’LS148 INPUTS OUTPUTS EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H H L H HHHHHHHH HHH L L X XXXXXXLL LLL H L X XXXXXLHL LHL H L X XXXXLHHL HLL H L X XXXLHHHL HHL H L X XXLHHHHH LLL H L X XLHHHHHH LHL H L X LHHHHHHH HLL H L L H H H H H H H H H H L H H = high logic level, L = low logic level, X = irrelevant
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’147, ’LS147 logic diagram (positive logic) (11) (12) (13) (1) (2) (3) (4) (5) (10) D B C A(9) (7) (6) (14) Pin numbers shown are for D, J, N, and W packages.
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ’148, ’LS148 logic diagram (positive logic) (10) (11) (12) (13) (1) (2) (3) (4) EI (5) (14) EO (6) (9) (7) (15) Pin numbers shown are for D, J, N, NS, and W packages.
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs EQUIVALENT OF EACH INPUT VCC Input R eq 0 input (’148): Req = 2 kΩ NOM All other inputs: Req = 4 kΩ NOM TYPICAL OF ALL OUTPUTS VCC Output ’147, ’148 /C0056/C0053 Ω NOM EQUIVALENT OF ALL INPUTS VCC Input ’LS147, ’LS148 TYPICAL OF ALL OUTPUTS Output VCC 120 Ω NOM R eq ’LS148 inputs 1–7: Req = 9 kΩ NOM All other inputs: Req = 18 kΩ NOM
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the eight data lines, 0 through 7. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54’ SN74’ SN54LS’ SN74LS’ UNITMIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX UNIT IOH High-level output current −800 −800 −400 −400 µA IOL Low-level output current 16 16 4 8 mA TA Operating free-air temperature−55 125 0 70 −55 125 0 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † ’147 ’148 UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VIK Input clamp voltage VCC = MIN, II = −12 mA −1.5 −1.5 V VOH High-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOH = −800 µA 2.4 3.3 2.4 3.3 V VOL Low-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V II Input current at maximum input voltage VCC = MIN, VI = 5.5 V 1 1 mA IIH High-level input0 input VCC = MAX, VI = 2.4 V AIIH High-level input current Any input except 0VCC = MAX, VI = 2.4 V 40 80 µA IIL Low-level input 0 input VCC = MAX, VI = 0.4 V −1.6 mAIIL Low-level input current Any input except 0VCC = MAX, VI = 0.4 V −1.6 −3.2 mA IOS Short-circuit output current§ VCC = MAX −35 −85 −35 −85 mA ICC Supply current VCC = MAX Condition 1 50 70 40 60 mAICC Supply current VCC = MAX (See Note 5) Condition 2 42 62 35 55 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 5: For ’147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For ’148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. SN54147, SN74147 switching characteristics, VCC = 5 V, TA = 25/C0053C (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT tPLH Any Any In-phase output 9 14 nstPHL Any Any In-phase output C L = 15 pF, 7 11 ns tPLH Any Any Out-of-phase output C L = 15 pF, R L = 400 Ω 13 19 ns tPHL Any Any Out-of-phase output R L = 400 12 19 ns
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54148, SN74148 switching characteristics, VCC = 5 V, TA = 25/C0053C (see Figure 1) PARAMETER † FROM (INPUT) TO (OUTPUT) WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT tPLH 1–7 A0, A1, or A2 In-phase output 10 15 nstPHL 1–7 A0, A1, or A2 In-phase output 9 14 ns tPLH 1–7 A0, A1, or A2 Out-of-phase output 13 19 nstPHL 1–7 A0, A1, or A2 Out-of-phase output 12 19 ns tPLH 0–7 EO Out-of-phase output 6 10 nstPHL 0–7 EO Out-of-phase output 14 25 ns tPLH 0–7 GS In-phase output C L = 15 pF, 18 30 nstPHL 0–7 GS In-phase output C L = 15 pF, R L = 400 Ω 14 25 ns tPLH EI A0, A1, or A2 In-phase output R L = 400 10 15 nstPHL EI A0, A1, or A2 In-phase output 10 15 ns tPLH EI GS In-phase output 8 12 nstPHL EI GS In-phase output 10 15 ns tPLH EI EO In-phase output 10 15 ns tPHL EI EO In-phase output 17 30 ns † tPLH = propagation delay time, low-to-high-level output. tPHL = propagation delay time, high-to-low-level output. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54LS’ SN74LS’ UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V VIK Input clamp voltage VCC = MIN, II = −18 mA −1.5 −1.5 V VOH High-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOH = −400 µA 2.5 3.4 2.7 3.4 V VOL Low-level output voltage VCC = MIN, VIH = 2 V, IOL = 4 mA 0.25 0.4 0.25 0.4 VVOL Low-level output voltage CC VIH = 2 V, VIL = VIL MAX IOL = 8 mA 0.35 0.5 V II Input current at maximum input ’LS148 inputs 1–7 VCC = MAX, VI = 7 V 0.2 0.2 mAII maximum input voltage All other inputs VCC = MAX, VI = 7 V 0.1 0.1 mA IIH High-level input’LS148 inputs 1–7 VCC = MAX, VI = 2.7 V 40 40 AIIH High-level input current All other inputs VCC = MAX, VI = 2.7 V 20 20 µA IIL Low-level input ’LS148 inputs 1–7 VCC = MAX, VI = 0.4 V −0.8 −0.8 mAIIL Low-level input current All other inputs VCC = MAX, VI = 0.4 V −0.4 −0.4 mA IOS Short-circuit output current§ VCC = MAX −20 −100 −20 −100 mA ICC Supply current VCC = MAX Condition 1 12 20 12 20 mAICC Supply current VCC = MAX (See Note 6) Condition 2 10 17 10 17 mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 6: For ’LS147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For ’LS148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open.
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS147, SN74LS147 switching characteristics, VCC = 5 V, TA = 25/C0053C (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT tPLH Any Any In-phase output 12 18 nstPHL Any Any In-phase output C L = 15 pF, 12 18 ns tPLH Any Any Out-of-phase output C L = 15 pF, R L = 2 kΩ 21 33 ns tPHL Any Any Out-of-phase output R L = 2 k 15 23 ns SN54LS148, SN74LS148 switching characteristics, VCC = 5 V, TA = 25/C0053C (see Figure 2) PARAMETER † FROM (INPUT) TO (OUTPUT) WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT tPLH 1–7 A0, A1, or A2 In-phase output 14 18 nstPHL 1–7 A0, A1, or A2 In-phase output 15 25 ns tPLH 1–7 A0, A1, or A2 Out-of-phase output 20 36 nstPHL 1–7 A0, A1, or A2 Out-of-phase output 16 29 ns tPLH 0–7 EO Out-of-phase output 7 18 nstPHL 0–7 EO Out-of-phase output 25 40 ns tPLH 0–7 GS In-phase output C L = 15 pF, 35 55 nstPHL 0–7 GS In-phase output C L = 15 pF, R L = 2 kΩ 9 21 ns tPLH EI A0, A1, or A2 In-phase output R L = 2 k 16 25 nstPHL EI A0, A1, or A2 In-phase output 12 25 ns tPLH EI GS In-phase output 12 17 nstPHL EI GS In-phase output 14 36 ns tPLH EI EO In-phase output 12 21 ns tPHL EI EO In-phase output 23 35 ns † tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output
NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open, and S2 is closed for tPZH ; S1 is closed, and S2 is open for tPZL . 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open, and S2 is closed for tPZH ; S1 is closed, and S2 is open for tPZL . E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms
/C0083/C0078/C0053/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0049/C0052/C0056/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0053/C0052/C0076/C0083/C0049/C0052/C0056 /C0083/C0078/C0055/C0052/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0049/C0052/C0056 /C0040/C0084/C0073/C0077/C0057/C0057/C0048/C0055/C0041/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0055/C0044 /C0083/C0078/C0055/C0052/C0076/C0083/C0049/C0052/C0056 /C0049/C0048/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0052/C0262/C0076/C0073/C0078/C0069 /C0065/C0078/C0068 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0051/C0262/C0076/C0073/C0078/C0069 /C0080/C0082/C0073/C0079/C0082/C0073/C0084/C0089 /C0069/C0078/C0067/C0079/C0068/C0069/C0082/C0083 SDLS053B − OCTOBER 1976 − REVISED MAY 2004 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
’148/’LS148 01234567E I EO A0 A1 A2 GS ’148/LS148 ’08/’LS08 01234567 9 1 0 1 1 1 2 1 3 1 4 1 5 Enable (active low) 012 3 Encoded Data (active low) Priority Flag (active low) 16-Line Data (active low) 01234567E I EO A0 A1 A2 GS ’148/’LS148 01234567E I EO A0 A1 A2 GS ’148/’LS148 ’HC00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Enable (active low) 012 3 Encoded Data (active high) Priority Flag (active high) 16-Line Data (active low) Figure 3. Priority Encoder for 16 Bits low on GS when all inputs are high. This must be considered when strobing the outputs.
www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 78027012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78027012A SNJ54LS 148FK 7802701EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701EA SNJ54LS148J 7802701FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701FA SNJ54LS148W JM38510/36001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 36001B2A JM38510/36001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BEA JM38510/36001BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BFA M38510/36001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 36001B2A M38510/36001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BEA M38510/36001BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 36001BFA SN54148J OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 SN54LS148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS148J SN74147N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70 SN74148J OBSOLETE CDIP J 16 TBD Call TI Call TI 0 to 70 SN74148N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70 SN74148N3 OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70 SN74LS147DR OBSOLETE SOIC D 16 TBD Call TI Call TI 0 to 70 SN74LS147N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70 SN74LS148D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148 SN74LS148DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148 SN74LS148DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148
www.ti.com 24-Apr-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LS148J OBSOLETE CDIP J 16 TBD Call TI Call TI 0 to 70 SN74LS148N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS148N SN74LS148N3 OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70 SN74LS148NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS148N SN74LS148NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS148 SNJ54148J OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 SNJ54148W OBSOLETE CFP W 16 TBD Call TI Call TI -55 to 125 SNJ54LS148FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78027012A SNJ54LS 148FK SNJ54LS148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701EA SNJ54LS148J SNJ54LS148W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701FA SNJ54LS148W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 24-Apr-2015 Addendum-Page 3 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54147, SN54148, SN54LS147, SN54LS148, SN74147, SN74148, SN74LS147, SN74LS148 :
- Catalog: SN74147 , SN74148 , SN74LS147 , SN74LS148
- Military: SN54147 , SN54148 , SN54LS147 , SN54LS148 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Military - QML certified for Military and Defense Applications
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS148DR SOIC D 16 2500 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2
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