7403

74HC7403 PHILIPS | Alldatasheet

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Technical content

Product specification Supersedes data of October 1990 File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT7403 4-Bit x 64-word FIFO register; 3-state For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403

FEATURES

• Synchronous or asynchronous operation
• 3-state outputs
• 30 MHz (typical) shift-in and shift-out rates
• Readily expandable in word and bit dimensions
• Pinning arranged for easy board layout: input pins directly opposite output pins
• Output capability: driver (8 mA)
• I CC category: LSI.

APPLICATIONS

• High-speed disc or tape controller
• Communications buffer. GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. The “7403” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 4 bits. A guaranteed

15 MHz data-rate makes it ideal for

high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out ( SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input ( MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. QUICK REFERENCE DATA GND = 0 V; T amb = 25°C; tr = tf = 6 ns. Note 1. For HC the condition is VI = GND to VCC . For HCT the condition is VI = GND to VCC −1.5 V.

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS TYP. UNIT HC HCT tPHL /tPLH propagation delaySO, SI to DIR and DOR C L = 15 pF; VCC = 5 V 15 17 ns fmax maximum clock frequency 30 30 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per package note 1 475 490 pF EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT7403N 16 DIL plastic SOT38Z 74HC/HCT7403D 16 SO16L plastic SOT162

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 PINNING SYMBOL PIN DESCRIPTION OE 1 output enable input (active LOW) DIR 2 data-in-ready output SI 3 shift-in input (active HIGH) D O to D3 4, 5, 6, 7 parallel data input GND 8 ground MR 9 asynchronous master-reset input (active LOW) Q 3 to Q0 10, 11, 12, 13 data output DOR 14 data-out-ready output SO 15 shift-out input (active LOW) VCC 16 positive supply voltage Fig.1 Pin configuration. handbook, halfpage DIR GND VCC D 0 D 1 D 2 D 3 Q 3 Q 2 Q 1 Q 0 OE 7403 MGA672 SI DOR SO MR Fig.2 Logic symbol. handbook, halfpage MGA674 DIR D 0 D 1 D 2 D 3 Q 3 Q 2 Q 1 Q 0 OE SI DOR SO MR Fig.3 IEC logic symbol. handbook, halfpage MGA676 1 ( /C2) CT = 0 <CT 64 >CT 0 CTR 5Z6 1Z2 EN4 [IR] 3 [OR] 6 FIFO 64 x 4 2D 4

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Fig.4 Functional diagram. MGA679 DIR OE SI MR D nA4 DIR SI DOR SO DATA INPUT A A 4 SO A DOR A Q nA 7403 FIFO A DIR OE SI MR D nB B B SO B DOR B Q nB7403 FIFO B DATA OUTPUT OE MR FUNCTIONAL DESCRIPTION A DIR flag indicates the input stage status, either empty and ready to receive data (DIR = HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D 0 to D3 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW, data is automatically shifted to the output stage or to the last empty location. A FIFO which can receive data is indicated by DIR set HIGH. A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy (DOR = LOW). When SO and DOR are HIGH, data is available at the outputs (Q 0 to Q3). When SO is set LOW new data may be shifted into the output stage, once complete DOR is set HIGH. Expanded format(see Fig.17) The DOR and DIR signals are used to allow the “7403” to be cascaded. Both parallel and serial expansion is possible. Serial expansion is only possible with typical devices. Parallel expansion Parallel expansion is accomplished by logically ANDing the DOR and DIR signals to form a composite signal. Serial expansion Serial expansion is accomplished by:

• tying the data outputs of the first device to the data inputs of the second device
• connecting the DOR pin of the first device to the SI pin of the second device
• connecting the SO pin of the first device to the DIR pin of the second device.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 ull pagewidth MSB118 (1) R SQ FS LATCHES CL CLD 0 D 1 D 2 D 3 DIR SI MR (2) R SQ FF1 (2) R SQ FF2 RQ RQ R SQ FF3 to FF63 RQ 61 x R SQ FF64 RQ (2) R SQ FB (1) R SQ FP (1)R DOR SO OE position 1 LATCHES CL CL position 2 LATCHES CL CL position 3 to 63 LATCHES CL CL position 64 3-STATE OUTPUT BUFFER Q 0 Q 1 Q 2 Q 3 Fig.5 Logic diagram. (see control flip-flops) LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state onR input. LOW on R input of FF1 to FF64 will set Q output to LOW independent of state onS input.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not valid for driver output. They are replaced by the values given below. Output capability: driver 8 mA I CC category: LSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HC SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITION +25 −40 to+85 −40 to+125 VCC (V) VI OTHER MIN TYP MAX MIN MAX MIN MAX VOH HIGH level output voltage all outputs 1.9 4.4 5.9 2.0 4.5 1.9 4.4 5.9 1.9 4.4 5.9 V V V 2.0 4.5 6.0 V IH or VIL IO =−20 µA VOH HIGH level output voltage driver outputs 3.98 5.48 4.32 5.81 3.84 5.34 3.70 5.20 V V 4.5 6.0 V IH or VIL IO =−8 mA IO =−10 mA VOL LOW level output voltage all outputs 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V 2.0 4.5 6.0 V IH or VIL IO = 20µA VOL LOW level output voltage driver outputs 0.15 0.15 0.26 0.26 0.33 0.33 0.40 0.40 V V 4.5 6.0 V IH or VIL IO = 8 mA IO = 10 mA

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITION +25 −40 to+85 −40 to+125 VCC (V) WAVEFORMS MIN TYP MAX MIN MAX MIN MAX tPHL /tPLH propagation delay MR to DIR, DOR 210 265 315 ns ns ns 2.0 4.5 6.0 Fig.8 t PHL propagation delay MR to Qn 160 200 240 ns ns ns 2.0 4.5 6.0 Fig.8 t PHL /tPLH propagation delay SI to DIR 205 255 310 ns ns ns 2.0 4.5 6.0 Fig.6 t PHL /tPLH propagation delay SO to DOR 290 365 435 ns ns ns 2.0 4.5 6.0 Fig.9 t PHL /tPLH propagation delay DOR to Q n 6.0 ns ns ns 2.0 4.5 6.0 Fig.10 t PHL /tPLH propagation delay SO to Qn 105 325 406 488 ns ns ns 2.0 4.5 6.0 Fig.14 t PLH propagation delay/ripple through delay SI to DOR 2.2 0.8 0.6 1.4 1.2 8.8 1.8 1.5 10.5 2.1 1.8 µs µs µs 2.0 4.5 6.0 Fig.10 t PLH propagation delay/bubble-up delay SO to DIR 2.8 1.0 0.8 1.8 1.5 11.2 2.2 1.9 13.5 2.7 2.3 µs µs µs 2.0 4.5 6.0 Fig.7 t PZH /tPZL 3-state output enable OE to Qn 150 190 225 ns ns ns 2.0 4.5 6.0 Fig.16 t PHZ /tPLZ 3-state output disable OE to Qn 150 190 225 ns ns ns 2.0 4.5 6.0 Fig.16 t THL /tTLH output transition time ns ns ns 2.0 4.5 6.0 Fig.16 t W SI pulse width HIGH or LOW 6.0 ns ns ns 2.0 4.5 6.0 Fig.6 t W SO pulse width HIGH or LOW 6.0 105 ns ns ns 2.0 4.5 6.0 Fig.9

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 tW DIR pulse width HIGH 130 165 195 ns ns ns 2.0 4.5 6.0 Fig.7 t W DOR pulse width HIGH 6.0 160 200 6.0 5.0 240 ns ns ns 2.0 4.5 6.0 Fig.10 t W MR pulse width LOW 120 150 180 ns ns ns 2.0 4.5 6.0 Fig.8 t rem removal time MR to SI 100 120 ns ns ns 2.0 4.5 6.0 Fig.15 t su set-up time D n to SI −36 −13 −10 ns ns ns 2.0 4.5 6.0 Fig.13 t h hold time D n to SI 135 170 205 ns ns ns 2.0 4.5 6.0 Fig.13 f max maximum clock pulse frequency SI, SO burst mode 3.6 9.9 2.8 2.4 MHz MHz MHz 2.0 4.5 6.0 Figs 11 and 12 f max maximum clock pulse frequency SI, SO using flags 3.6 9.9 2.8 2.4 MHz MHz MHz 2.0 4.5 6.0 Figs 6 and 9 f max maximum clock pulse frequency SI, SO cascaded 7.6 MHz MHz MHz 2.0 4.5 6.0 Figs 6 and 9 SYMBOL PARAMETER T amb (°C) UNIT TEST CONDITION +25 −40 to+85 −40 to+125 VCC (V) WAVEFORMS MIN TYP MAX MIN MAX MIN MAX

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that VOH and VOL are not valid for driver output. They are replaced by the values given below. Output capability: driver 8 mA. I CC category: LSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HCT Notes to the HCT DC Characteristics 1. The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. 2. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITION +25 −40 to+85 −40 to+125 VCC (V) VI OTHER MIN TYP MAX MIN MAX MIN MAX VOH HIGH level output voltage all outputs IH or VIL IO =−20 µA VOH HIGH level output voltage driver outputs IH or VIL IO =−8 mA VOL LOW level output voltage all outputs IH or VIL IO = 20µA VOL LOW level output voltage driver outputs IH or VIL IO = 8 mA INPUT UNIT LOAD COEFFICIENT OE 1 SI 1.5 D n 0.75 MR 1.5 SO 1.5

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITION −25 −40 to+85 −40 to+125 VCC (V) WAVEFORMS MIN TYP MAX MIN MAX MIN MAX tPHL /tPLH propagation delay MR to DIR, DOR − 30 51 − 53 − 63 ns 4.5 Fig.8 t PHL propagation delay MR to Qn − 22 38 − 48 − 57 ns 4.5 Fig.8 tPHL /tPLH propagation delay SI to DIR − 25 43 − 54 − 65 ns 4.5 Fig.6 t PHL /tPLH propagation delay SO to DOR − 36 61 − 76 − 92 ns 4.5 Fig.9 tPHL /tPLH propagation delay SO to Qn − 42 72 − 90 − 108 ns 4.5 Fig.14 tPHL /tPLH propagation delay DOR to Q n − 71 2 − 15 − 18 ns 4.5 Fig.10 tPLH propagation delay/ripple through delay SI to DOR t PLH propagation delay/bubble-up delay SO to DIR tPZH /tPZL 3-state output enable time OE to Qn − 16 30 − 38 − 45 ns 4.5 Fig.16 tPHZ /tPLZ 3-state output disable time OE to Qn − 19 30 − 38 − 45 ns 4.5 Fig.16 tTHL /tTLH output transition time − 51 2 − 15 − 18 ns 4.5 Fig.16 tW SI pulse width HIGH or LOW 95 − 6 − 8 − ns 4.5 Fig.6 tW SO pulse width HIGH or LOW 14 8 − 18 − 21 − ns 4.5 Fig.9 tW DIR pulse width HIGH 5 17 29 4 36 4 44 ns 4.5 Fig.7

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 tW DOR pulse width HIGH 7 21 36 6.0 45 6.0 54 ns 4.5 Fig.10 t W MR pulse width LOW 26 15 − 33 − 39 − ns 4.5 Fig.8 trem removal time MR to SI 18 10 − 23 − 27 − ns 4.5 Fig.15 tsu set-up time D n to SI th hold time D n to SI 30 18 − 38 − 45 − ns 4.5 Fig.13 fmax maximum clock pulse frequency SI, SO burst mode 18 30 − 14 − 12 − MHz 4.5 Figs 11 and 12 fmax maximum clock pulse frequency SI, SO using flags 18 30 − 14 − 12 − MHz 4.5 Figs 6 and 9 fmax maximum clock pulse frequency SI, SO cascaded − 23 −−−−− MHz 4.5 Figs 6 and 9 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITION −25 −40 to+85 −40 to+125 VCC (V) WAVEFORMS MIN TYP MAX MIN MAX MIN MAX

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 AC WAVEFORMS Shifting in sequence FIFO empty to FIFO full Notes to Fig.6 1. DIR initially HIGH; FIFO is prepared for valid data 2. SI set HIGH; data loaded into input stage 3. DIR goes LOW, input stage “busy” 4. SI set LOW; data from first location “ripple through” 5. DIR goes HIGH, status flag indicates FIFO prepared for additional data 6. Repeat process to load 2nd word through to 64th word into FIFO DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs. Fig.6 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum pulse frequency. handbook, full pagewidth MGA659 VM (1) 1/ f max Wt tPHL tPLH VM (1) 1st word 2nd word 64th word 2SI INPUT D n INPUT DIR OUTPUT (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 With FIFO full; SI held HIGH in anticipation of empty location Notes to Fig.7 1. FIFO is initially full, shift-in is held HIGH 2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins 3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input 4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again 5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full. Fig.7 Waveforms showing bubble-up delay,SO input to DIR output and DIR output pulse width. handbook, full pagewidth SI INPUT MGA660 DIR OUTPUT VM (1)2 bubble - up delay VM (1) SO INPUT tPLH VM (1)1 tW (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Master reset applied with FIFO full Notes to Fig.8 1. DIR LOW, output ready HIGH; assume FIFO is full 2. MR pulse LOW; clears FIFO 3. DIR goes HIGH; flag indicates input prepared for valid data 4. DOR goes LOW; flag indicates FIFO empty 5. Q n outputs go LOW (only last bit will be reset). Fig.8 Waveforms showing theMR input to DIR, DOR and Qn output propagation delays and theMR pulse width. handbook, halfpage tPHL VM (1) tW tPLH DIR OUTPUT VM (1) MR INPUT VM (1) MGA668 Q n OUTPUT tPHL DOR OUTPUT (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Notes to Fig.9 1. DOR HIGH; no data transfer in progress, valid data is present at output stage 2. SO set HIGH; results in DOR going LOW 3. DOR goes LOW; output stage “busy” SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input stage 5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay 6. Repeat process to unload the 3rd through to the 64th word from FIFO 7. DOR remains LOW; FIFO is empty. Fig.9 Waveforms showing theSO input to DOR output propagation delay. TheSO pulse widths and maximum pulse frequency. handbook, full pagewidth MGA661 VM (1)SO INPUT Q n OUTPUT 1/ fmax Wt DOR OUTPUT tPHL tPLH VM (1) VM (1) 1st SO pulse 2nd SO pulse 64th SO pulse 1st word 2nd word 64th word (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 With FIFO empty;SO is held HIGH in anticipation Notes to Fig.10 1. FIFO is initially empty,SO is held HIGH 2. SI pulse; loads data into FIFO and initiates ripple through process 3. DOR flag signals the arrival of valid data at the output stage 4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the DOR pulse to the Q n output 5. DOR goes LOW; data shift-out is complete, FIFO is empty again SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty. Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation delay from the DOR pulse to the Qn output. handbook, full pagewidth SI INPUT MGA658 Q OUTPUTn DOR OUTPUT VM (1)2 ripple through delay VM (1) SO INPUT tPLH tPLHtPHL VM (1)1 tW (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Shift-in operation; high-speed burst mode Note to Fig.11 In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored. Fig.11 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst mode. handbook, full pagewidth MGA662 VM (1)SI INPUT D n INPUT 1/ fmax tW DIR OUTPUT (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Shift-out operation; high-speed burst mode Note to Fig.12 In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The DOR flag is a don't care condition and anSO pulse can be applied without regard to the flag. Fig.12 Waveforms showingSO minimum pulse width and maximum pulse frequency, in high-speed shift-out burst mode. handbook, full pagewidth MGA663 VM (1)SO INPUT Q n OUTPUT 1/ fmax tW DOR OUTPUT (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Fig.13 Waveforms showing hold and set-up times for Dn input to SI input. The shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth SI INPUT MGA657 VM (1)D n INPUT tsu th VM (1) tsu th (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V. Fig.14 Waveforms showingSO input to Qn output propagation delays and output transition time. handbook, full pagewidth tTHLtTLH tPLH MGA664 VM (1)SO INPUT Q n OUTPUT VM (1) tPHL (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Fig.15 Waveform showing theMR input to SI input removal time. handbook, halfpage MGA665 trem SI INPUT MR INPUT VM (1) VM (1) (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V. Fig.16 Waveforms showing the 3-state enable and disable times for inputOE. handbook, full pagewidth MGA656 tPLZ tPZL VM (1) outputs disabled outputs enabled tPZH 90 % tPHZ 10 % 90 % tftr outputs enabled OE INPUT 10 % VM (1) VM (1) Q OUTPUT LOW - to - OFF OFF - to - LOW n Q OUTPUT HIGH - to - OFF OFF - to - HIGH n (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V.

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403

APPLICATION INFORMATION

Fig.17 Expanded FIFO (parallel and serial) for increased word length; 8 bits wide x 64 n-bits. handbook, full pagewidth MGA684 DIR SI DOR SO MR OE OE DIR SI DOR SOMR 7403 D 0 D 1 D 2 D 3 Q 3 Q 2 Q 1 Q 0 OE DIR SI DOR SOMR 7403 D 0 D 1 D 2 D 3 Q 3 Q 2 Q 1 Q 0 OE DIR SI DOR SOMR 7403 D 0 D 1 D 2 D 3 Q 3 Q 2 Q 1 Q 0 OE DIR SI DOR SOMR 7403 D 0 D 1 D 2 D 3 Q 3 Q 2 Q 1 Q 0 8-bit data 8-bit data

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Note to Fig.18 The “7403” is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay on the flags. Fig.18 Expanded FIFO for increased word length; 64 words x 10 bits. handbook, full pagewidth MGA678 DIR OE SI DOR SO MR D n Q n4 4 7403 DIR OE SI DOR SO MR 7403 D n Q n4 4 DATA INPUT COMPOSITE DIR FLAG SI MR OE SO DATA OUTPUT COMPOSITE DOR FLAG DATA INPUT DATA OUTPUT

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Note to Fig.19 This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started or ifSO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see Figs 7 and 10). Fig.19 Expanded FIFO for increased word length. handbook, full pagewidth MGA683 DIR OE SI DOR SO MR D n Q n4 7403 DIR OE SI DOR SO MR 7403 D n Q n SI MR OE SO composite DOR composite DIR 4 4 DQ CP R Q DQ CP Q DQ CP Q DQ CP Q R

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Notes to Fig.21 1. FIFOA and FIFOB initially empty,SO A held HIGH in anticipation of data 2. Load one word into FIFOA; SI pulse applied, results in DIR pulse 3. Data-outA/data-inB transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFOB 4. DOR A and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output ready pulse, data is shifted into FIFOB 5. DIRB andSO A go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete 6. DIRB andSO A go HIGH automatically; the input stage of FIFOB is again able to receive data,SO is held HIGH in anticipation of additional data 7. DOR B goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output stage. Fig.21 FIFO to FIFO communication; input timing under empty condition. handbook, full pagewidth VM (1) DOR B SIA VM (1) MGA666 DIR A Q nA nBD SO ADIR B DOR A SIB VM (1) 2 ripple through delay VM (1) VM (1)1 ripple through delay nBQ

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Notes to Fig.22 1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up 2. Unload one word from FIFOB;SO pulse applied, results in DOR pulse 3. DIRB andSO A pulse HIGH; (bubble-up delay afterSO B LOW) data is loaded into FIFOB as a result of the DIR pulse, data is shifted out of FIFOA 4. DOR A and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete 5. DOR A and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting bubble-up of empty location 6. DIRA goes HIGH; (bubble-up delay afterSO A LOW) an empty location is present at input stage of FIFOA. Fig.22 FIFO to FIFO communication; output timing under full condition. handbook, full pagewidth VM (1)DOR B SO B VM (1) MGA667 4 5 DIR A Q nA nBD SO ADIR B DOR A SIB VM (1) 2 bubble - up delay VM (1) VM (1) bubble - up delay

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Note toFig.23 Sequence 1 (both FIFOS empty, starting SHIFT-IN process) After aMR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data.SO B is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SO B goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes HIGH (4). Fig.23 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.18). handbook, full pagewidth DOR B OUTPUT DIRB OUTPUT DOR A OUTPUT DIRA OUTPUT Q OUTPUTnB Q nA OUTPUT SI INPUTA D INPUTnA MR INPUT SO INPUTB sequence 1 sequence 2 sequence 3 sequence 4 sequence 5 sequence 6 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) MGA687

Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Sequence 2 (FIFOB runs full) After theMR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being empty. Sequence 3 (FIFOA runs full) When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. Sequence 4 (both FIFOs full, starting SHIFT-OUT process) SI A is held HIGH and twoSO B pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11). Sequence 5 (FIFOA runs empty) At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted out and one word being shifted in, in sequence 4. An additional series ofSO B pulses are applied. After 63SO B pulses, all words from FIFOA are shifted into FIFOB. DORA remains LOW (12). Sequence 6 (FIFOB runs empty) After the nextSO B pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63SO B pulses, DOR B remains LOW due to both FIFOs being empty (14). AdditionalSO B pulses have no effect. The last word remains available at the output Qn. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.