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Simplifying System Integration™ DATA SHEET April 2009 Rev. 1.3 © 2009 Teridian Semiconductor Corporation 1
DESCRIPTION
The Teridian 73S8024C is a single smart card interface IC. It provides full electrical compliance with ISO-7816-3, EMV 4.0 and NDS specifications1. Interfacing with the system controller is done through the control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. Data exchange with the card is managed from the system controller using the I/O line (and eventually the auxiliary I/O lines). Hardware support for auxiliary I/O lines, C4 / C8 contacts, is provided. The card clock signal can be generated by an on-chip oscillator using an external crystal or by connection to a clock signal coming from the system controller. The Teridian 73S8024C device incorporates an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Level shifters drive the card signals with the selected card voltage (3 V or 5 V), coming from an internal DC-DC converter. With its high-efficiency DC-DC converter, the Teridian 73S8024C is a cost-effective solution for any smart card reader application to be powered from a single 2.7 V to 3.6 V power supply. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a VDD (digital power supply) or a VCC (card power supply) failure, a card over-current, or
- The only smart card interface IC firmware compatible with the TDA8004 operating with a single 2.7 V to 3.6 V power supply (allows removal of 5 V from the system) an over-heating fault. ADVANTAGES
- The inductor-based DC-DC converter provides higher current and efficiency than the usual charge-pump capacitor-based converters Ideal for battery-powered applications Suitable for high current cards and SAMs: (100 mA max)
- Power down mode: 2 µA typical
FEATURES
- Card Interface: Complies with ISO-7816-3, EMV 4.0 and NDS1 A DC-DC Converter provides 3V / 5V to the card from an external power supply input High-efficiency converter: > 80% @ VDD=3.3 V, VCC=5 V and ICC Up to 100 mA supplied to the card = 65 mA ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry Protection includes 2 voltage supervisors which detect voltage drops on card V CC and on VDD The V power supplies DD True over-current detection (150 mA max.) voltage supervisor threshold value can be externally adjusted 2 card detection inputs, 1 for each possible user polarity Auxiliary I/O lines, for C4/C8 contact signals Card clock up to 20 MHz
- System Controller Interface: 3 Digital inputs control the card activation / deactivation, card reset and card voltage 4 Digital inputs control the card clock (division rate and card clock stop modes) 1 Digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults. Crystal oscillator or host clock, up to 27 MHz
- Power Supply: VDD
- Power Down mode 2.7 V to 3.6 V
- 6 kV ESD Protection on the card interface
- Package: SO28
APPLICATIONS
- Set-Top-Boxes , DVD / HDD Recorders
- Point of Sales and Transaction Terminals
- Control Access and Identification 1 Pending NDS approval.
73S8024C Data Sheet DS_8024C_023 2 Rev. 1.3 FUNCTIONAL DIAGRAM Pin number reference to SO28 Package Figure 1: 73S8024C Block Diagram ICC I/O BUFFERS VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE XTAL OSC CLOCK GENERATION DIGITAL CIRCUITRY FAULT LOGIC VDD FAULT VCC FAULT Int_Clk VDD VDD VCC RST CLK PRES PRES XTALIN XTALOUT CLKDIV1 CLKDIV2 GND TEMP FAULT NC ISO-7816-3 SEQUENCER R-C OSC. DC-DC CONVERTER ICC RESET BUFFER ICC CLOCK BUFFER OVER TEMP PWRDN I/O AUX1 AUX2 IOUC AUX1UC AUX2UC VDDF_ADJ RSTIN CMDVCC 5V/#V OFF GND LIN GND ICC FAULT
73S8024C Data Sheet DS_8024C_023 4 Rev. 1.3
1 Pin Description
1.1 Card Interface
(SO) Description IO 11 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1 13 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2 12 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. RST 16 Card reset: provides reset (RST) signal to card. CLK 15 Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by crystal oscillator frequency and CLKDIV selections. PRES 10 Card Presence switch: active high indicates card is present. Includes a pull- down current source. PRES 9 Card Presence switch: active low indicates card is present. Includes a pull-up current source. VCC 17 Card power supply: logically controlled by the sequencer, output of DC-DC converter. Requires an external filter capacitor to the card GND. GND 14 Card ground.
1.2 Miscellaneous Inputs and Outputs
(SO) Description XTALIN 24 Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. XTALOUT 25 Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as an external clock input. VDDF_ADJ 18 VDD fault threshold adjustment input: this pin can be used to adjust the VDDF value (that controls deactivation of the card). Must be left open if unused. NC 7 Non-connected pin.
1.3 Power supply and ground
(SO) Description VDD 6, 21 System controller interface supply voltage, supply voltage for internal power supply and DC-DC converter power supply source. GND 4 DC-DC converter ground. GND 22 Digital ground. LIN 5 External inductor. Connect external inductor from pin 5 to VDD. Keep the inductor close to pin 5.
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 5
1.4 Microcontroller Interface
(SO) Description CMDVCC 19 Command VCC (negative assertion): Logic low on this pin causes the DC-DC converter to ramp the VCC supply to the card and initiates a card activation sequence. 5V/#V 3 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic low selects 3 volt operation. When the part is to be used with a single card voltage, this pin should be tied to either GND or VDD. However, it includes a high impedance pull-up resistor to default this pin high (selection of 5 V card) when unconnected. PWRDN 8 Power Down control input (active high): When Power Down (PD) mode is activated; all internal analog functions are disabled to place the 73S8024C in its lowest power consumption mode. The PD mode is allowed only out of a card session (= PWRDN high is not taken into account when CMDVCC = 0). Must be tied to ground when the power down function is not used. CLKDIV1 CLKDIV2 Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card clock. These pins include pull-down resistors. CLKDIV1 CLKDIV2 Clock Rate 0 0 XTALIN/8 0 1 XTALIN/4 1 1 XTALIN/2 1 0 XTALIN OFF 23 Interrupt signal to the processor (active low): Multi-function indicating fault conditions and card presence. Open drain output configuration; it includes an internal 20 kΩ pull-up to VDD. RSTIN 20 Reset Input: This signal is the reset command to the card. I/OUC 26 System controller data I/O to/from the card. Includes internal pull-up resistor to VDD. AUX1UC 27 System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD. AUX2UC 28 System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD.
73S8024C Data Sheet DS_8024C_023 6 Rev. 1.3
2 System Controller Interface
- 2 digital inputs allow direct control of the card interface from the host as follows: Pin CMDVCC: When low, starts an activation sequence if a card is present. Pin 5V/#V: Defines the card voltage.
- The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to the host: Pin RSTIN: controls the card reset signal (when enabled by the sequencer). Pin I/OUC: data transfer to card I/O contact. Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/O lines to be connected to the C4 and C8 card connector contacts).
- 2 digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the card clock frequency, from the input clock frequency (crystal or external clock). The division rate is defined as follows: CLKDIV2 CLKDIV1 CLK 0 0 ⅛ XTAL 0 1 XTAL 1 0 ¼ XTAL 1 1 ½ XTAL When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN. When other division rates are used, the 73S8024C circuitry guarantees a duty-cycle in the range 45% to 55%, conforming to ISO-7816-3, EMV 4.0 and NDS specifications.
- Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card removed during a card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence.
- Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8024C in its Power Down state. This pin can only be activated out of a card session.
3 Oscillator
The 73S8024C device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected.
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 7
4 DC-DC Converter – Card Power Supply
An internal DC-DC converter provides the card power supply. This converter is able to provide either 3 V or 5 V card voltage from the power supply applied on the VDD pin. The digital ISO-7816-3 sequencer controls the converter. Card voltage selection is carried out by the digital input 5V/#V. The circuit is an inductive step-up converter/regulator. The external components required are 2 filter capacitors on the power-supply input VDD (next to the LIN pin, 100 nF + 10 µF), an inductor, and an output filter capacitor on the card power supply VCC. The circuit performs regulation by activating the step-up operation when VCC is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the input supply VDD is less than the set point for VCC. When VDD is greater than the set point for VCC (VDD = 3.6 V, VCC =3 V) the circuit operates as a linear regulator. Depending on the inductor values, the voltage converter can provide current on VCC as high as 100 mA. The circuit provides over-current protection and limits ICC to 150 mA. When an over-current condition is sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output OFF. Choice of the inductor The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 5 in the SO package, pin 2 in the QFN package) and the VDD voltage. The inductor value can be optimized to meet a particular configuration (ICC_MAX). The inductor should be located on the PCB as close as possible to the LIN pin of the IC. Choice of the VCC Depending on the applications, the requirements in terms of both the V capacitor CC Table 1 minimum voltage and the transient currents that the interface must provide to the card are different. shows the recommended capacitors for each VCC Table 1: Choice of VCC Pin Capacitor power supply configuration and applicable specification. Specification Requirement Application Specification Min VCC Max Transient Current Charge Voltage Allowed During Transient Current Capacitor Type Capacitor Value EMV 4.0 4.6 V 30 nAs X5R/X7R w/ ESR < 100 mΩ 3.3 µF ISO-7816-3 4.5 V 20 nAs 1 µF Table 1: Choice of VCC Pin Capacitor
5 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
73S8024C Data Sheet DS_8024C_023 8 Rev. 1.3
6 Voltage Supervision
Two voltage supervisors constantly check the level of the voltages VDD and VCC. A card deactivation sequence is triggered upon a fault of any of these voltage supervisors. The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range for the interface with the system controller. The VDD Voltage supervisor is also used to initialize the ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3 V nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the QFN package) is used to connect an external resistor REXT to ground to raise the VDD fault voltage to another value, VDDF. The resistor value is defined as follows: REXT = 180 kΩ / (VDDF An alternative (more accurate) method of adjusting the V - 2.33) DD Figure 9 fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground (see ). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R1/(R1+R3) and is calculated as: Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas: Taking the example above, where a VDD
7 Power Down
fault threshold voltage of 2.7 V is desired, solving for Kx gives: Solving for R3 gives: R3 = 72000 / 0.377 = 191 kΩ. Solving for R1 gives: R1 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ. Using standard 1% resistor values gives R3 = 191 kΩ and R1 = 115 kΩ. These values give an equivalent resistance of Kx = 0.376, a 0.3% error. If the 2.3 V default threshold is used, this pin must be left unconnected. A power down function is provided via the PWRDN pin (active high). When activated, the Power Down (PD) mode disables all the internal analog functions, including the card analog interface, the oscillators and the DC-DC converter, to put the 73S8024C in its lowest power consumption mode. PD mode is only allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from the host controller). The host controller invokes the power down state when it is desirable to save power. The signals PRES and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller must then set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to turning CMDVCC low). Resumption of the normal mode occurs at approximately 10 ms (stabilization of the internal oscillators and reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms time period. If a card is present, OFF can be used as an indication that the circuit has completed its recovery from the power down state. OFF will go high at the end of the stabilization period. Should CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on its edges, it should be toggled high and low again after the 10 ms to activate a card. Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if the power down function is not used.
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 9 Figure 2: Power Down Mode Operation
8 Activation Sequence
The 73S8024C smart card interface IC has an internal 10 ms delay at power-on reset or upon application of VDD > VDDF The following steps and or upon exit of Power-Down mode. The card interface may only be activated when OFF is high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to activate the card. Figure 3 show the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low: 1. CMDVCC is set low. 2. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during t1. If VCC does not become valid, then OFF goes low to report a fault to the system controller, and the power VCC 3. Turn I/O (AUX1, AUX2) to reception mode at the end of t to the card is shut down. 4. Due to the fall of RSTIN, CLK is applied to the card at the end of t 5. RST is a copy of RSTIN after t 4. RSTIN may be set high before t4 , however the sequencer won’t set RST high until 42000 clock cycles after the start of CLK. Figure 3: Activation Sequence – RSTIN low when CMDVCC goes low t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator) t2 = 1.5 µs, I/O goes to reception state t3 = >0.5 µs, CLK starts t4 ≥ 42000 card clock cycles (time for RST to become the copy of RSTIN) CMDVCC VCC IO CLK RSTIN t1 t2 t3 t4 RST PRES OFF PWRDN Internal RC OSC CMDVCC OFF follows PRES regardless of PWRDN PWRDN during a card session has no effect After setting PWRDN = 0, the controller must wait at least 10ms before setting CMDVCC=0 EMV / ISO deactivation time ~= 100 uS ~10ms PWRDN has effect when the cardi s deactivated
73S8024C Data Sheet DS_8024C_023 10 Rev. 1.3 The following steps and Figure 4 show the activation sequence and the timing of the card control signals when the system controller pulls CMDVCC low while RSTIN is high: 1. CMDVCC is set low. 2. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the system controller and the VCC 3. After the fall of RSTIN at t power to the card is shut down. 4. CLK is applied to the card at the end of t , turn I/O (AUX1, AUX2) to reception mode. 5. RST is a copy of RSTIN after t after I/O is in reception mode. 4. RSTIN may be set high before t4 , however the sequencer will not set RST high until 42,000 clock cycles after the start of CLK. Figure 4: Activation Sequence – RSTIN high when CMDVCC goes low
9 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VCC The following steps and fault, and card extraction during the session. Figure 5 show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: 1. RST goes low at the end of time t 2. CLK is set low at the end of time t 3. I/O goes low at the end of time t 4. V . Out of reception mode. CC is turned off at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low. t1 = 0.510 ms (timing by 1.5MHz internal Oscillator) t2 = 1.5 µs, I/O goes to reception state t3 ≥ 0.5 µs, CLK active t4 ≥ 42000 card clock cycles (time for RST to become the copy of RSTIN). CMDVCC VCC IO CLK RSTIN t1 t2 t3 t4 RST
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 11 Figure 5: Deactivation Sequence
10 OFF and Fault Detection
There are two cases for which the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Monitoring Outside a Card Session In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No deactivation is required during this time. Monitoring During a Card Session CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same time that OFF is set low, the sequencer starts the deactivation process. Figure 6 shows the timing diagram for the CMDVCC, PRES, and OFF signals during a card session and outside the card session. PRES OFF CMDVCC VCC outside card session within card session OFF is low by card extracted OFF is low by any fault within card session Figure 6: Timing Diagram – Management of the Interrupt Line OFF t1≥ 0.5 µs, timing by 1.5 MHz internal Oscillator t2 ≥ 7.5 µs t3 ≥ 0.5 µs t4 ≥ 0.5 µs t5 = depends on VCC filter capacitor For NDS application, CF = 1 µF making t1 + t2 + t3 + t4 + t5 < 100 µs RST CLK I/O VCC t2 t3 CMDVCC -- OR -- OFF
73S8024C Data Sheet DS_8024C_023 12 Rev. 1.3
11 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power on reset and they are in the high state when the activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for more details on when the I/O reception is on. The state of the I/OUC, AUX1UC, and AUX2UC is high after power on reset. Within a card session and when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both I/O lines return to their neutral state. Figure 7 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 8. Neutral State I/OUC in I/O reception I/OICC in No Yes No No No Yes No Yes I/O not I/OUC I/OUC not I/O I/OUC I/O yesyes Figure 7: I/O and I/OUC State Diagram Figure 8: I/O – I/OUC Delays: Timing Diagram Delay from I/O to I/OUC: tIO_HL = 100 ns tIO_LH = 25 ns Delay from I/OUC to I/O: tI/OUC_HL = 100 ns tI/OUC_LH = 25 ns IO IOUC tIO_HL tIO_LH tIOUC_HL tIOUC_LH
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 13
12 Typical Application Schematic
RSTIN_f rom_uC CMDVCC_from_uC 100nF 5V/3V_select_f rom_uC AUX1UC_to.f rom_uC AUX2UC_to/f rom_uC SO28 See NOTE 1 See NOTE 4 CLK track should be routed far from RST, I/O, C4 and C8. Low E SR (< 1 0 0 mohms) C1 should be placed near the SC connecter contact See NOTE 2 External_clock_f rom uC See NOTE 3 - OR - VDD R2 20K See NOTE 6 Card detection switch is normally closed. NDS & ISO7816=1uF, EMV=3.3uF L1 10uH Rext1 See note 7 CLKDIV2_f rom_uC CLKDIV1_f rom_uC See note 8 VDD See NOTE 1R3 Rext2 VDD NOTES: 1) VDD supply must be =2.7V to 3.6V DC. 2) Optional, can be left open 3) Required if external clock from uP is used. 4) Required if crystal is used. Y1, C2 and C3 must be removed if external clock is used. 5) Pin can not float. Must be driven or connected to GND if power down function is not used. 6)Internal pull-up allows it to b e left open if unused . 7) Rext1 and Rext2 are external resistors to ground and Vdd to modify the VDDfault voltage. Can be left open 8) Keep L1 close to pin 5 OFF_interrupt_to_uC VDD IOUC_to/from_uC PWRDN_from_uC CRYSTAL Smart Card Connector VCC 1RST 2CLK 3C4 4GND 5VPP 6I/O 7C8 8 SW-1 9SW-2 10 73S8024C CLKDIV11 CLKDIV22 5V3V_3 GND4 LIN5 VDD6 NC7 AU X212 PWRDN8 PRESB9 PRES10 I/O11 AU X113 GND14 CLK 15RST 16VCC 17VDD_ADJ 18CMDVCC_ 19RSTIN 20VDD 21GND 22OFF_ 23 AUX 2UC 28 AUX 1UC 27 XTALOUT 25 XTALI N 24 I/OUC 26C4 100nF 10uF Figure 9: 73S8024C Typical Application Schematic
73S8024C Data Sheet DS_8024C_023 14 Rev. 1.3
13.1 Absolute Maximum Ratings
Operation outside these rating limits may cause permanent damage to the device. Parameter Rating Supply Voltage V -0.5 to 4.0 VDC DD Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC Storage Temperature -60 °C to 150 °C Pin Voltage (except LIN and card interface) -0.3 to (VDD +0.5) VDC Pin Voltage (LIN) -0.3 to 6.0 VDC Pin Voltage (card interface) -0.3 to (VCC + 0.5) VDC ESD Tolerance – Card interface pins +/- 6 kV ESD Tolerance – Other pins +/- 2 kV ESD testing on Card pins uses the HBM condition, 3 pulses, each polarity referenced to ground.
13.2 Recommended Operating Conditions
Supply Voltage VDD 2.7 to 3.6 VDC Ambient Operating Temperature -40 °C to +85 °C Input Voltage for Digital Inputs 0 V to VDD + 0.3 V
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 15
13.3 Card Interface Characteristics
Symbol Parameter Condition Min. Typ. Max. Unit Card Power Supply (VCC) DC-DC Converter General conditions, -40 °C < T < 85 °C, 2.7 V < VDD < 3.6 V V Card supply voltage including ripple and noise CC Inactive mode -0.1 0.1 V Inactive mode ICC -0.1 =1 mA 0.4 V Active mode ICC 4.75 < 65 mA; 5 V 5.25 V Active mode ICC 2.8 < 65 mA; 3 V 3.2 V Active mode single pulse of 100 mA for 2 µs; 5 V, fixed load = 25 mA 4.6 5.25 V Active mode single pulse of 100 mA for 2 µs; 3 V, fixed load = 25 mA 2.76 3.2 V Active mode current pulses of 40 nAs with peak |ICC 4.6 | < 200 mA, t < 400 ns; 5 V 5.25 V Active mode current pulses of 40 nAs with peak |ICC 2.76 | < 200 mA, t < 400 ns; 3 V 3.2 V I Maximum supply current to the card CCmax Static load current, VCC 100 > 4.6 or 2.7 volts as selected, L=10 µH mA I ICCF CC fault current 100 125 180 mA V V SR CC C slew rate – Rise rate on activate F on VCC 0.05 = 1 µF 0.15 0.25 V/µs V V SF CC C slew rate – Fall rate on deactivate F on VCC 0.1 = 1 µF 0.3 0.5 V/µs C External filter capacitor (VF CC to GND) 0.47 1 3.3 µF L Inductor (LIN to VDD ) 10 µH Limax Imax in inductor VCC = 5 V, ICC = 65 mA, VDD = 2.7 V 400 mA η Efficiency VCC = 5 V, ICC = 65 mA, VDD = 3.3 V 80 %
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 17 Symbol Parameter Condition Min. Typ. Max. Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I//OUC, AUX1UC, and AUX2UC. IIL requirements only pertain to I//OUC, AUX1UC, and AUX2UC. V Output level, high (I/O, AUX1, AUX2) OH IOH 0.9 V = 0 CC VCC V + 0.1 IOH 0.75 V = -40 µA CC VCC V + 0.1 V Output level, high (I/OUC, AUX1UC, AUX2UC) OH IOH 0.9 V = 0 DD VDD V + 0.1 IOH 0.75 V = -40 µA DD VDD V + 0.1 V Output level, low OL IOL = 1 mA 0.3 V V Input level, high (I/O, AUX1, AUX2) IH 1.8 VCC V + 0.30 V Input level, high (I/OUC, AUX1UC, AUX2UC) IH 1.8 VDD V + 0.30 V Input level, low IL -0.3 0.8 V V Output voltage when outside of session INACT IOL = 0 0.1 V IOL = 1 mA 0.3 V I Input leakage LEAK VIH = V CC 10 µA I Input current, low IL VIL = 0, CS = 1 0.65 mA VIL = 0, CS = 0 5 μA I Short circuit output current SHORTL For output low, shorted to VCC through 33 Ω 15 mA I Short circuit output current SHORTH For output high, shorted to ground through 33 Ω 15 mA tR, t Output rise time, fall times F CL = 80 pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL = 50 pF 100 ns tIR, t Input rise, fall times IF 1 µs R Internal pull-up resistor PU Output stable for > 200ns 8 11 14 kΩ FD Maximum data rate MAX 1 MHz T Delay, I/O to I/OUC, I/OUC to I/O (falling edge to falling edge) FDIO 100 ns C Input capacitance IN 10 pF Reset and Clock for card interface, RST, CLK V Output level, high OH IOH 0.9 V = -200 µA CC V V CC V Output level, low OL IOL 0 = 200 µA 0.3 V V Output voltage when outside of a session INACT IOL = 0 0.1 V IOL = 1 mA 0.3 V I Output current limit, RST RST_LIM 30 mA I Output current limit, CLK CLK_LIM 70 mA tR, t Output rise time, fall time F CL = 35 pF for CLK, 10% to 90% 8 ns CL = 200 pF for RST, 10% to 90% 100 ns δ Duty cycle for CLK, except for f = f C XTAL L =35 pF, FCLK 45 ≤ 20 MHz 55 %
73S8024C Data Sheet DS_8024C_023 18 Rev. 1.3
13.4 Digital Signals
Symbol Parameter Condition Min. Typ. Max. Unit Digital I/O except for OSC I/O VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 1.8 VDD + 0.3 V VOL Output Low Voltage IOL = 2 mA 0.45 V VOH Output High Voltage IOH = -1 mA VDD - 0.45 V ROUT Pull-up resistor, OFF 20 kΩ |IIL1| Input Leakage Current GND < VIN < VDD -5 5 μA Oscillator (XTALIN) I/O Parameters V Input Low Voltage - XTALIN ILXTAL -0.3 0.3 V V DD V Input High Voltage - XTALIN IHXTAL 0.7 V DD VDD V + 0.3 I Input Current - XTALIN ILXTAL GND < VIN < V -30 DD 30 μA f Max freq. Osc or external clock MAX 27 MHz δin External input duty cycle limit tR/F < 10% fIN, 45% < δCLK 48 < 55% 52 %
13.5 DC Characteristics
Symbol Parameter Condition Min. Typ. Max. Unit I Supply Current on VPC Linear mode, ICC = 0 I/O, AUX1, AUX2 = high DD 4.9 mA Step up mode, ICC = 0 I/O, AUX1, AUX2 = high 4.7 mA I Supply Current on V DD_PD DD PWRDN=1, Start/stop bit = 0 All digital inputs driven with a true logical 0 or 1 in Power Down mode 0.11 2.5 µA
13.6 Voltage / Temperature Fault Detection Circuits
Symbol Parameter Condition Min. Typ. Max. Unit V V DDF DD fault (VDD No external resistor on VDDF_ADJ Voltage supervisor threshold) 2.15 2.4 V V V CCF CC fault (VCC V Voltage supervisor threshold) CC 4.20 = 5 V 4.6 V VCC 2.5 = 3 V 2.7 V T Die over temperature fault F 115 145 °C I Card over current fault CCF 90 150 mA
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 19
14 Mechanical Drawings (28-SO)
Figure 12: 28 Lead SO .335 (8.509) .320 (8.128) .420 (10.668) .390 (9.906) .050 TYP. (1.270) .305 (7.747) .285 (7.239) .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .016 nom (0.40) .110 (2.790) .092 (2.336) PIN NO. 1 BEVEL
73S8024C Data Sheet DS_8024C_023 20 Rev. 1.3 Use handling procedures necessary for a static sensitive component. (Top View) Figure 11: 73S8024C 28-SO Pin Out 73S8024C 1514 CLKDIV1 CLKDIV2 5V/#V GND VDD PRES PRES I/O AUX2 AUX1 GND AUX2UC AUX1UC I/OUC XTALIN XTALOUT OFF VDD RSTIN CMDVCC VCC RST CLK NC LIN PWRDN VDDF_ADJ GND
DS_8024C_023 73S8024C Data Sheet Rev. 1.3 21 Part Description Order Number Packaging Mark 73S8024C-SO 28-pin Lead-Free SO 73S8024C-IL/F 73S8024C-IL 73S8024C-SO 28-pin Lead-Free SO Tape / Reel 73S8024C-ILR/F 73S8024C-IL
17 Related Documentation
The following 73S8024C documents are available from Teridian Semiconductor Corporation: 73S8024C Data Sheet (this document) 73S8024C Demo Board User’s Guide
18 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8024C, contact us at:
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Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com.
73S8024C Data Sheet DS_8024C_023 22 Rev. 1.3
Revision History
1.0 6/21/2005 First publication. 1.1 7/15/2005 Removed QFN package information. 1.2 12/5/2007 Add ISO and EMV logos, remove leaded package option, update 28SO package dimension. 1.3 4/3/2009 Remove all references to VPC as VPC must be tied to VDD. © 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com