Interface

73S8014BN

Maxim Integrated Produc...

Smart Card Interface Rev 2; 12/11

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Rev. 2 1

DESCRIPTION

The 73S8014BN is a single smart card (ICC) interface circuit designed to provide full electrical compliance with ISO 7816-3, EMV® 4.2, and NDS specifications . It is derived from the 73S8024RN industry -standard electrical interface , but adds support for 1.8V smart card applications. The 73S 8014BN has been optimized to match set -top box/A/V conditional access applications. The optimization adds functionality while creating a device with a smaller pin count. For NDS applications requiring an on-chip adjustable POR, see the Maxim 73S8024RN series of interface ICs. The 73S8014BN interfaces with the host processor through the same bus (digital I/Os) as the 73S8024RN and most other 8024 type devices . As a result, the 73S 8014BN is a very attractive cost-reduction path from traditional 8024 ICs. Interfacing with the system controller is done through a control bus, composed of digital inputs to control the 73S8014BN, and one interrupt output to inform the system controller of the ca rd presence, device readiness and faults. The card clock can be generated by an on-chip oscillator using an external crystal or by connection to an externally supplied clock signal. In addition, the clock divider provides divisor values of divide by 1, 2, 4 , and 8 that are controlled through a single pin. The 73S 8014BN incorporates an ISO 7816 -3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage ( 1.8V, 3V, or 5V), coming fro m an internal l ow dropout (LDO) voltage regulator. This LDO regulator is powered by a dedicated power -supply input , V PC. Digital circuitry is powered separately by a digital power supply , VDD. With its embedded LDO regulator, the 73S 8014BN is a cost - effective solution for any application where a 5V (typically - 5% +10%) power supply is available. Emergency card deactivation is initiated upon card extraction or upon any fault detected by the protection circuitry. The fault can be a card overcurrent, V CC undervoltage, or power-supply fault (V DD). The card overcurrent circuitry is a true current - detection function, as opposed to V CC voltage drop detection, as usually implemented in non-Maxim 8024 interface ICs. The 73S8014BN contains a power -down mode with typical power consumption of 1 µA on each of the V DD and V PC supplies. The power-down mode is controlled through existing control pins without the need for a dedicated control pin.

APPLICATIONS

Set-Top Box Conditional Access and Pay-per-View
General-Purpose Smart Card Readers ADVANTAGES
NDS Compliant
Same Advantages as the Maxim 73S80xxR Family:  Card VCC Generated by an LDO Regulator  Very Low Power Dissipation (Saves Up to 1/2W)  Fewer External Components Are Required  Better Noise Performance
True Card Overcurrent Detection
Firmware Compatibility with 8024 ICs
Small-Format 20-Pin SO Package Capable of Fully Supporting NDS Applications
Power-Down Mode

FEATURES

Card Interface  Complies with ISO 7816-3, EMV 4.2, and NDS  Supports 3V/5V Cards Up to 65mA and 1.8V Cards Up to 40mA  ISO 7816-3 Activation/Deactivation Sequencer  Automated Deactivation Upon Hardware Fault (i.e., Upon Drop on VDD Power Supply or Card Overcurrent)  Overcurrent Detection 145mA max  Card CLK Clock Frequency Up to 20MHz
System Controller Interface  Three Digital Inputs Control the Card Activation/Deactivation, Card Reset, Power-Down, and Card Voltage  One Digital Input Controls the Card Clock Frequency  One Digital Output, Interrupt to the System Controller, Reports to the Host the Card Presence, Device Readiness, and Faults  Crystal Oscillator or Host Clock, Up to 27MHz
Regulator Power Supply  4.75V to 5.5V (EMV 4.2)  4.85V to 5.5V (NDS)
Digital Interfacing: 2.7V to 3.6V
±6kV ESD Protection on the Card Interface
20-Pin SO Package
RoHS-Compliant (6/6)/Lead(Pb)-Free Package 19-5669; Rev 2; 12/11 EMV is a registered trademark of EMVCo L LC. 73S8014BN Smart Card Interface DS_8014BN_057

73S8014BN Data Sheet DS_8014BN_057 2 Rev. 2 FUNCTIONAL DIAGRAM SMART CARD SIGNAL CONTROL and LEVEL SHIFTERS LDO REGULATOR SC SEQUENCER VOLTAGE and CURRENT REFERENCES CLOCK GENERATION CONTROLLER AND FAULT LOGIC RESET BUFFER CLOCK BUFFERR-C OSC. VDD FAULT VCC FAULT CLOCK 1.5MHz VDD VPC VCC RST CLK PRES C4C4UC CMDVCC RSTIN 5V#V GND OFF bias currents vref vcc circuits VDD CKT vdd circuits vdd circuits VCC CONTROL C8UC I/OUC I/O XTAL OSC XTALIN/ CLKIN XTALOUT CKDIV POWER DOWN Figure 1: 73S8014BN Block Diagram

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 3 Table of Contents

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 5

1 Pinout

The 73S8014BN is offered in a 20-pin SO package. 1110 2 19 CLKDIV C4UC 5V/#V VPC PRES I/O I/OUC XTALIN/CLKIN XTALOUT OFF VDD RSTIN CMDVCC VCC RST CLK GND 73S8014BN C8UC Figure 2: 73S8014BN 20-SO Pinout

73S8014BN Data Sheet DS_8014BN_057 6 Rev. 2 Table 1 provides the 73S8014BN pin names, pin numbers, type, equivalent circuits, and descriptions. Table 1: 73S8014BN 20-Pin SO Pin Definitions NAME PIN TYPE EQUIVALENT CIRCUIT FIGURE # I/O 13 IO Figure 16 Card I/O: Data Signal to/from Card. Includes an 11kΩ pullup resistor to VCC. C4 12 IO Figure 16 Card C4: Data Signal to/from Card. Includes an 11kΩ pullup resistor to VCC. C8 14 IO Figure 16 Card C8: Data Signal to/from Card. Includes an 11kΩ pullup resistor to VCC. RST 15 O Figure 15 Card Reset. Provides reset (RST) signal to card. CLK 17 O Figure 14 Card Clock: Provides clock signal (CLK) to card. The rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on XTALIN and CLKDIV selections. PRES 19 I Figure 18 Card Presence Switch. Active high indicates the card is present. Includes a high-impedance pulldown current source. The PRES input includes a 5ms debounce for card insertion. VCC 18 PSO Figure 13 Card Power Supply. Logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. GND 16 GND — Card and Digital Ground HOST PROCESSOR INTERFACE CMDVCC 8 I Figure 18 Command VCC (Negative Assertion). Logic-low on this pin causes the LDO regulator to ramp the VCC supply to the card and initiates a card activation sequence, only when a card is present. 5V/3V 9 I Figure 18 5V/3V/1.8V Card Selection. Logic-high selects 5V for VCC and card interface. Logic-low selects 3V operation. Logic going from high to low within ±400ns of CMDVCC falling selects 1.8V. When the device is to be used with a single card voltage (3V or 5V only), this pin should be connected to either GND or VDD. However, it includes a high-impedance pullup resistor to default this pin high (selection of 5V card) when not connected. Do not change the level of this pin when CMDVCC is low. CLKDIV 6 I Figure 20 Sets the Divide Ratio from the XTAL Oscillator (or External Clock Input) to Card Clock. This is a multilevel input that uses a ratio of the VDD voltage to select the clock divider as shown: CLKDIV CLOCK RATE GND XTALIN/4 VDD/3 XTALIN VDD x 2/3 XTALIN/8 VDD XTALIN/2 Note: This input has no internal pullup or pulldown so it must not be left unconnected. OFF 20 O Figure 12 Active-Low Interrupt Signal to the Processor. Active-low multifunction indicating fault conditions, device readiness, and card presence. Open-drain output configuration. It includes an internal 20kΩ pullup to VDD.

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 7 NAME PIN TYPE EQUIVALENT CIRCUIT FIGURE # Reset Input. Within a card session, this signal is the reset command to the card. Outside a card session, this signal is used to place the device in power-down. C8UC 2 IO Figure 17 System Controller Data C8 to/from the Card. Includes an 11kΩ pullup resistor to VDD. I/OUC 3 IO Figure 17 System Controller Data I/O to/from the Card. Includes an 11kΩ pullup resistor to VDD. C4UC 5 IO Figure 17 System Controller Data C4 to/from the Card. Includes an 11kΩ pullup resistor to VDD. MISCELLANEOUS INPUTS AND OUTPUTS XTALIN/ CLKIN 10 I Figure 19 Crystal Oscillator Input. This pin can either be connected to crystal or driven as a source for the card clock. XTALOUT 11 O Figure 19 Crystal Oscillator Output. Connected to crystal. This pin can be left open if XTALIN is being used as external clock input. POWER SUPPLY AND GROUND VDD 7 PSO Figure 13 System Interface Supply Voltage and Supply Voltage for Internal Circuitry VPC 4 PSO Figure 13 LDO Regulator Power Supply Source

73S8014BN Data Sheet DS_8014BN_057 8 Rev. 2

2 Electrical Specifications

This section provides the following:  Absolute Maximum Ratings  Recommended Operating Conditions  Smart Card Interface Requirements  Digital Signals Characteristics  DC Characteristics  Voltage Fault-Detection Circuits

2.1 Absolute Maximum Ratings

Table 2 lists the maximum operating conditions for the 73S 8014BN. Permanent device damage can occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. The smart card interface pins are protected against short circuits to V CC, ground, and each other. Table 2: Absolute Maximum Device Ratings PARAMETER RATING Supply Voltage Range, VDD -0.5V to 4.0V DC Supply Voltage Range, VPC -0.5V to 6.0V DC Input Voltage for Digital Inputs -0.3V to (VDD + 0.5V) DC Storage Temperature Range -60°C to +150°C Pin Voltage Range (except Card Interface) -0.3V to (VDD + 0.5V) DC Pin Voltage Range (Card Interface) -0.3V to (VCC + 0.5V) DC ESD Tolerance (Card Interface Pins)* ±6kV ESD Tolerance (Other Pins) ±2kV *ESD testing on smart card pins is Human Body Model (HBM) condition, three pulses, each polarity referenced to ground. Note: Smart card pins are protected against shorts between any combinations of smart card pins.

2.2 Recommended Operating Conditions

Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions PARAMETER RATING Supply Voltage Range, VDD 2.7V to 3.6V DC Supply Voltage Range, VPC 4.75V to 5.5V DC Ambient Operating Temperature Range -40°C to +85°C Input Voltage for Digital Inputs 0 to (VDD + 0.3V)

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 9

2.3 Smart Card Interface Requirements

Table 4 lists the 73S8014BN smart card interface requirements. Table 4: DC Smart Card Interface Requirements PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CARD POWER SUPPLY (VCC) REGULATOR (NDS conditions: 4.85V < VPC < 5.5V, unless otherwise noted.) Card Supply Voltage Including Ripple and Noise VCC Inactive mode -0.1 +0.1 V Inactive mode, ICC = 1mA -0.1 +0.4 Active mode; ICC < 65mA; 5V 4.65 5.25 Active mode; ICC < 65mA; 5V, NDS condition 4.75 5.25 Active mode; ICC < 65mA; 3V 2.85 3.15 Active mode; single pulse of 100mA for 2µs; 5V, fixed load = 25mA (Note 1) 4.6 5.25 Active mode; ICC < 40mA; 1.8V 1.68 1.92 Active mode; single pulse of 100mA for 2µs; 3V, fixed load = 25mA (Note 1) 2.76 3.15 Active mode; current pulses of 40nAs with peak |ICC | < 200mA, t < 400ns; 5V (Note 1) 4.6 5.25 Active mode; current pulses of 40nAs with peak |I CC | <200mA, t < 400ns; 5V, NDS condition (Note 1) 4.65 5.25 Active mode; current pulses of 40nAs with peak |ICC | <200mA, t < 400ns; 3V (Note 1) 2.7 3.15 Active mode; current pulses of 20nAs with peak |ICC | <100mA, t < 400ns; 1.8V (Note 1) 1.62 1.92 VCC Ripple VCCRIP fRIPPLE = 20kHz – 200MHz (Note 1) 350 mV Card Supply Output Current ICCMAX Static load current, VCC > 4.6V or 2.7V as selected 65 mA Static load current, VCC>1.65 40 ICC Fault Current ICCF VCC = 3V or 5V 70 145 mA VCC = 1.8V 50 110 mA VCC Slew Rate, Rise VSR CF = 1.0µF on VCC 0.06 0.150 0.30 V/µs VCC Slew Rate, Fall VSF CF = 1.0µF on VCC 0.075 0.150 0.60 V/µs External Filter Cap (VCC to GND) CFNDS NDS applications, CF should be ceramic with low ESR (< 100mΩ) (Note 1) 0.5 1.0 1.5 µF

73S8014BN Data Sheet DS_8014BN_057 10 Rev. 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERFACE REQUIREMENTS DATA SIGNALS: I/O, C4, C8 HOST INTERFACES: I/OUC, C4UC, C8UC (ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, C4UC, and C8UC.) Output Level High (I/OUC, C4UC, C8UC) VOH IOH = -40µA 0.9 x VDD VDD + 0.1 V IOH = 0mA 0.75 x VDD VDD + 0.1 Output Level High (I/O, C4, C8) IOH = -40µA (VCC = 3V/5V), -20µA (VCC = 1.8V) 0.9 x VCC VCC + 0.1 IOL = 1mA 0.75 VCC VCC+0.1 Output Level Low (I/OUC, C4UC, C8UC) VOL IOL = 1mA 0.15 x VDD V Output Level Low (I/O, C4, C8) 0.15 x VCC Input Level High (I/OUC, C4UC, C8UC) VIH 0.6 x VDD VDD + 0.30 V Input Level High (I/O, C4, C8) 0.6 x VCC VCC + 0.30 Input Level Low (I/OUC, C4UC, C8UC) VIL -0.15 0.20 x VDD V Input Level Low (I/O, C4, C8) IOL = 0mA -0.15 0.20 x VCC Output Voltage When Outside of Session VINACT IOL = 1mA 0.1 V VIH = VCC 0.3 Input Leakage ILEAK VIL = 0V 10 µA Input Current Low IIL For output low, shorted to VCC through 33Ω 0.65 mA Short-Circuit Output Current ISHORTL For output high, shorted to ground through 33Ω 15 mA Short-Circuit Output Current ISHORTH CL = 80pF, 10% to 90% 15 mA Output Rise Time, Fall Times tR, tF 100 ns Input Rise, Fall Times tIR, tIF Output stable for > 400ns (Note 1) 1 µs Internal Pullup Resistor RPU 8 11 15 kΩ Maximum Data Rate FDMAX Edge from master to slave, measured at 50% 1 MHz Delay, I/O to I/OUC, I/OUC to I/O, C4 to C4UC, C4UC to C4, C8 to C8UC, C8UC to C8 (Respectively Falling Edge to Falling Edge and Rising Edge to Rising Edge) t FDIO 60 100 200 ns tRDIO 15 Input Capacitance CIN (Note 1) 10 pF

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 11 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RESET AND CLOCK FOR CARD INTERFACE: RST, CLK Output Level High VOH IOH =-200µA 0.9 x VCC VCC V Output Level Low VOL IOL=200µA 0 0.15 x VCC V Output Voltage When Outside of Session VINACT IOL = 0mA 0.1 V IOL = 1mA 0.3 Output Current Limit, RST IRST_LIM 30 mA Output Current Limit, CLK I CLK_LIM 70 mA Output Rise Time, Fall Time tR, tF CL = 35pF for CLK, 10% to 90% 8 ns CL = 200pF for RST, 10% to 90% 100 Duty Cycle for CLK δ CL =35pF, fCLK ≤ 20MHz 45 55 % Note 1: Guaranteed by design; not production tested.

2.4 Digital Signals Characteristics

Table 5 lists the 73S8014BN digital signals characteristics. Table 5: Digital Signals Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL -0.3 +0.8 V Input High Voltage VIH 1.8 VDD + 0.3 V Output Low Voltage VOL IOL = 2mA 0.45 V Output High Voltage VOH IOH = -1mA VDD - 0.45 V Pullup Resistor, OFF ROUT 13.5 20 26.5 kΩ Input Leakage Current |IIL1| VGND < VIN < VDD -5 +5 µA Input Level, CLKDIV VINCD1 Level Range 1 -0.3 +0.400 V VINCD2 Level Range 2 0.26 x VDD 0.40 x VDD VINCD3 Level Range 3 0.6 x VDD 0.80 x VDD VINCD4 Level Range 4 VDD - 0.400 VDD + 0.3 Input Low Voltage, XTALIN VILXTAL -0.3 0.3 x VDD V Input High Voltage, XTALIN VIHXTAL 0.7 x VDD VDD + 0.3 V Input Current, XTALIN IILXTAL VGND < VIN < VDD -30 +30 µA Max Frequency Oscillator or External Clock fMAX 27 MHz External Input Duty- Cycle Limit δin tR/tF < 10% fIN, 45% < δCLK < 55% (Note 1) 48 52 % Note 1: Guaranteed by design; not production tested.

73S8014BN Data Sheet DS_8014BN_057 12 Rev. 2

2.5 DC Characteristics

Table 6 lists the 73S8014BN DC characteristics. Table 6: DC Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD Supply Current IDD VDD = 2.7V to 3.6V 2.0 4 mA VDD Supply Current IPD Power-down 1 5 µA VPC Supply Current IPC VCC on, ICC = 0mA, CLK = 2.0MHz, external load < 10pF, I/O, C4, C8 = high 1 2 mA VPC Supply Current IPCPD CMDVCC = 1 1 2 µA

2.6 Voltage Fault-Detection Circuits

Table 7 lists the 73S8014BN voltage and current fault-detection circuits. Table 7: Voltage and Current Fault-Detection Circuits PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD Fault VDDF VDD falling 2.15 2.4 V ICC Fault Current ICCF VCC = 3V or 5V 70 145 mA VCC = 1.8V 50 110 VCC Fault (VCC Voltage Supervisor Threshold) VCCF VCC = 5V 4.6 V VCC = 3V 2.7 VCC = 1.8V (Note 1) 1.65 Note 1: Guaranteed by design; not production tested.

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 13

3 Applications Information

This section provides general usage information for the design and implementation of the 73S8014BN.

3.1 Example 73S8014BN Schematics

Figure 3 shows a typical application schematic for the implementation of the 73S8014BN. Note that minor changes can occur to the reference material from time to time and the reader is encouraged to contact Maxim for the latest information.

73S8014BN Data Sheet DS_8014BN_057 14 Rev. 2 NDS, EMV & ISO7816= 1.0uF Low ESR (<100mohms) C1 should be placed near the SC connector contact CLKDIV2_from_uC CLK track should be routed far from RST, I/O, C4 and C8. NOTES: 1) VDD = 2.7V to 3.6V DC.* 2) VPC = 4.75V(ISO)/4.85V(NDS) to 5.5V DC* 3) Required if external clock from uP is used. 4) Required if crystal is used. Y1, C2 and C3 must be removed if external clock is used. See NOTE 2 73S8014BN 10 11 CLKDIV VPC PRES I/O CLK RST VCC RSTIN VDD GND XTALOUTXTALIN C8UC Smart Card Connector VCC RST CLK GND VPP I/O SW-1 SW-2 100nF 10uF VPC OFF_interrupt_to_uC C8UC_to/from_uC RSTIN_from_uC CMDVCC_from_uC See NOTE 4 Y1CRYSTAL C222pF C322pF External_clock_from uC See NOTE 3 - OR - VDD Card detection switch is normally open 47K * Do not begin a NDS card session until VPC > 4.85V and VDD > VTH (VDD fault threshold) OFF 5V3V CMDVCC C4UC I/OUC I/OUC_to/from_uC C4UC_to/from_uC 5V/#V_select_from_uC See NOTE 1 100nF VDD See NOTE 5 5) Since the internal PRES pull down is weak, it is recommended that an external pull down is included 6) Pull down resistor R5 must be installed when using VCC = 1.8V, optional otherwise 20K See NOTE 6 Figure 3: 73S8014BN—Typical Application Schematic

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 15

3.2 System Controller Interface

Three digital inputs allow direct control of the card interface by the host. The 73S8014BN is controlled as follows:  Pin CMDVCC: When asserted low, starts an activation sequence. When deasserted high, starts deactivation sequence.  Pin RSTIN: Controls the card RST signal (when enabled by the sequencer) while the card is activated and the power-down mode when the card is not activated.  Pin 5V/3V: Defines the card VDD voltage according to Table 8. Table 8: VCC Voltage Logic Table CONTROL PINS VCC VOLTAGE (V) NOTES CMDVCC 5V/3V 1 x 0 Off 1 5 5V/3V must be stable for at least 1µs before assertion of CMDVCC and held high until deassertion of CMDVCC. 0 3 5V/3V must be stable for at least 1µs before assertion of CMDVCC and held low until deassertion of CMDVCC.

1.8 Must be asserted low within 400ns of each other to generate

1.8V and held low until assertion of CMDVCC. The OFF digital output reports status back to the host. See the Fault Detection and OFF section for details on the operation of the OFF output. Note: 5V/ 3V should not change during a card session. Doing so does not change the voltage on V CC during that session, but if it is changed, the 5V /3V must be taken high outside the current card session and before beginning the next card session. Otherwise, the next card session may not power up to the selected VCC voltage.

3.3 Power-Down Mode

The 73S8014BN includes a power -down mode to greatly reduce the power consumption on the V DD and V PC supplies when the smart card interface is deactivated. The power-down mode shuts down the crystal oscillat or and other internal circuits to save power. When the power -down mode is released, the oscillator is restarted. It requires some time to start up and stabilize. During this time, the OFF output goes low (if a card is inserted) and is held low until the os cillator stabilizes, and then the OFF output goes high to indicate that the device is ready to activate the card. The power-down mode is initiated when RSTIN, CMDVCC , and 5V/3V are all logic-high for more than 2ms. The power-down mode is released immediat ely by bringing RSTIN low. This action forces the OFF output low for approximately 5ms to 7ms to allow the oscillator to start up and stabilize. This action inform s the host that the 73S8014BN is busy and should not be activated while the OFF output is low . This ensures a proper activation sequence after coming out of power-down. The card-detection logic on the PRES input remains active in power-down mode. The card status is reported on OFF. Note: The CMDVCC and 5V/3V inputs have no effect when exiting power -down. Bringing RSTIN low is the only way to exit power-down. Figure 4 shows the power-down mode control timing with PRES debounce. See Section 3.9 for a full description of the PRES debounce behavior.

73S8014BN Data Sheet DS_8014BN_057 16 Rev. 2 CMDVCC 5V/#V RSTIN PRES PWR_DOWN OFF This is a sequence of PRES events during the time when the host is requesting Power Down by setting CMDVCC = 5V/#V = RSTIN = High. In such a sequence, the circuit has to sense PRES and de-assert Power Down and time (de-bounce) the PRES signal, or assert the Power Down as appropriate. 5 - 7ms When Power Down is de-asserted (RSTIN=Low), OFFB will go low indicating circuit is not ready, and then go high after 5ms (if PRES is high) 2ms 5ms 5ms Figure 4: Power-Down Mode and PRES Debounce

3.4 Power Supply and Voltage Supervision

The 73S8014BN smart card interface IC incorporates a low dropout (LDO) voltage regulator for VCC. The voltage output is controlled by the digital input 5V/ 3V of the 73S8014BN. This regulator can provide 1.8V, 3V, or 5V card voltage from the power supply applied on the V PC pin. The voltage regulator can provide a current of at least 65mA on VCC for both 3V and 5V or 40mA for 1.8V that complies with EMV 4.0 and NDS specifications. An overcurrent supervisor triggers a fault if the current on VCC exceeds the threshold at the given VCC voltage. Digital circuitry is powered by the power supply applied on the V DD pin. VDD is sourced by 2.7 to 3.6V so the system controller must operate with this supply level . A card deactivation sequence is forced upon fault of any voltage or overcurrent supervisor. One supervisor monitors the V CC output voltage at the selected V CC voltage level. The maximum VCC voltage-fault threshold does not exceed the minimum VCC voltage spec according to ISO 7816. See VCCF specification for the VCC voltage thresholds. Another voltage supervisor constantly monitors the VDD voltage. This fixed threshold supervisor is used to initialize the ISO 7816-3 sequencer at power -on and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set to 2.26V ty pical (VDDF). If an adjustable V DD threshold (>2.26V) is required on the device, then the 73S8024RN should be considered or an external circuit configured for the desired VDD threshold should be added to the circuit to control either the CMDVCC or PRES input for an immediate VCC deactivation. Note: Since the V DD and the VPC power supplies are separate, special care must be taken to ensure that the V PC voltage is greater than 4.85V before beginning activating the card. In addition, V DD must be greater than the threshold for V DD fault before card activation. When turning off power to the V DD and the V PC power supplies, the card should be deactivated before shutdown or the VPC power supply must remain higher than 4.85V when the VDD fault is detected and the emergency deactivation sequence is completed.

3.5 Card Power Supply

The 73S8014BN smart card interface IC incorporates an LDO voltage regulator for V CC. The voltage output is controlled by the digital inputs 5V/3V and CMDVCC of the 73S8014BN. This regulator can provide 1.8V, 3V, or 5V card voltage from the power supply applied on the VPC pin. The voltage regulator can provide a current of at least 65mA on VCC for both 3V and 5V and 40mA for 1.8V that complies with EMV 4.2 and NDS specifications. Note: When using V CC = 1.8V , a minimum load is required on V CC to e nsure proper output regulator stability. A 20kΩ resistor is required between VCC and GND to meet this minimum load requirement. If VCC = 1.8V is never used in a given application, the resistor is not required.

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 17

3.6 On-Chip Oscillator and Card Clock

The 73S8014BN device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is available from another source it can be connected to XTALIN, and XTALOUT should be left unconnected. For this device the card clock frequency can be chosen among four different division rates, defined by multiple- state input CLKDIV, as per the following table: CLKDIV CLK MAX XTALIN/CLKIN (MHz) GND 1/4 XTALIN 27 VDD/3 XTALIN 20 VDD x 2/3 1/8 XTALIN 27 VDD 1/2 XTALIN 27 Note: The clock-divider ratio must be configured prior to activation and must not change during the card session. Note: Special care should be taken when configuring the CLKDIV input when using the power-down mode. The CLKDIV input does not contain an internal pullup or pulldown so it must not be allowed to be left unconnected. In addition, the CLKDIV input should be set in such a manner as to set the voltage level to GND or V DD to keep the current consumption to an absolute minimum. There are numerous simple methods available to control CLKDIV as shown in Figure 5. CLKDIV PINHOST I/O PIN 1. Selecting between Divide by 2 (I/O HIGH) or divide by 4 (I/O LOW) CLKDIV PINHOST I/O PIN 2. Selecting between Divide by 2 (IO HIGH) or divide by 8 (IO LOW) VDD CLKDIV PINHOST I/O PIN 1 HOST I/O PIN 2 3. Selecting any of the four Divide ratios R R Figure 5: CLKDIV Usage

73S8014BN Data Sheet DS_8014BN_057 18 Rev. 2

3.7 Activation Sequence

The 73S8014BN smart card interface IC has an internal 1ms delay on the application of V DD where VDD > VDDF. No activation is allowed during this 1ms period. The CMDVCC (edge triggered) signal must then be set low to activate the card. To initiate activation, the card must be present and there can be no VDD fault. The following steps show the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low:

CMDVCC is set low at t0.
VCC rises to the selected level and then the internal V CC control circuit checks the presence of V CC at the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid at t1, OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
Turn I/O to reception mode at t2.
CLK is applied to the card at t3.
RST is a copy of RSTIN after t3. CMDVCC VCC I/O CLK RSTIN t1 t2 t3 RST t1 = 0.2ms (timing by 1.5MHz internal oscillator) t2 = 1.5µs, I/O goes to reception state t3 = > 0.5µs, CLK starts, RST to become the copy of RSTIN Figure 6: Activation Sequence—RSTIN Low When CMDVCC Goes Low The startup of the CLK output can be delayed in the activation sequence by setting the RSTIN input high before beginning activation by bringing CMDVCC low. The CLK output is delayed until RSTIN is taken low. Special care must be taken when performing this type of activation. The power -down mode is initiated by setting the RSTIN and 5V/3V inputs high while CMDVCC is high (outside a card session). If this state is held for more than 2ms, the power mode is initiated. As a result, to use this activation mode, the CMDVCC falling edge must occur within 1ms of the RSTIN input being set high. The following steps show the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high:
CMDVCC is set low at t0.
VCC rises to the selected level and then the int ernal VCC control circuit checks the presence of V CC at the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid at t1, OFF goes low to report a fault to the system controller, and VCC to the card is shut off.
At the fall of RSTIN (under host control) at t2, CLK is applied to the card.
RST is a copy of RSTIN after t2.

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 19 CMDVCC VCC I/O CLK RSTIN t1 t2t0 RST t1 = 0.2 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state) t2 = RSTIN goes low and CLK becomes active t3 = > 0.5µs, CLK active, RST to become the copy of RSTIN Figure 7: Activation Sequence—RSTIN High When CMDVCC Goes Low

3.8 Deactivation Sequence

Deactivation is initiated either by the system controller by setting the CMDVCC high or automatically in the event of hardware faults. Hardware faults are overcurrent, VDD fault, VCC fault, and card extraction during the session. The following steps show the deactivation sequence and the timing of the card control signal s when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:

RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low. RST CLK I/O VCC t2 t3 CMDVCC -- OR -- OFF t1 = > 0.5µs, timing by 1.5MHz internal oscillator t2 = > 7.5µs t3 = > 0.5µs t4 = > 0.5µs t5 = depends on VCC filter capacitor For NDS application, CF=1µF makes t1 + t2 + t3 + t4 + t5 < 100µs Figure 8: Deactivation Sequence

73S8014BN Data Sheet DS_8014BN_057 20 Rev. 2

3.9 Fault Detection and OFF

There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence and device readiness outside card sessions, or for fault detection during card sessions. The OFF interrupt output operates as follows: As long as the card is not activated (CMDVCC is always high), OFF informs the host about the card presence or device readiness. When no card is inserted, the OFF output is low. When a card is inserted, the OFF output is set high after a 5ms debounce period. Upon card removal, there is no debounce on the PRES input as the emergency deactivation must occur as soon as possible to prevent any potential card errors or data corruption. The OFF output goes low immediately upon detection of a logic -low on the PRES input, but the OFF output does not bounce and remains low for at least 5ms. In addition, when a card is present and the power-down mode is released, the OFF output is taken low for about 5ms to indicate that the device is not ready. This time allows the crystal oscillator to start up and stabilize. When CMDVCC is asserted low (card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. , card removal during card session, voltage fault, or overcurrent fault) that automatically initiates a deactivation sequence. Figure 9 shows the timing diagram for the signals CMDVCC, PRES, and OFF while the card is activated and deactivated: PRES OFF CMDVCC VCC outside card session within card session OFF is low by card extracted OFF is low by any fault within card session Figure 9: Timing Diagram—Management of the Interrupt Line OFF

3.10 I/O, C4, and C8 Circuitry and Timing

The I/O, C4, and C8 are smart card data signals that operate identically , and I/OUC, C4UC, and C8UC are the corresponding microcontroller interface signals . The I/O and I/OUC data signals are described henceforth. The state of the I/O and I/OUC pins are low after power-on reset and goes high when the activation sequencer turns on the I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The state of I/OUC is high after power-on reset. When the card is activated and the I/O reception state is turned on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both I/O lines return to their neutral state. Note: In certain situations and conditions, the I/O logic can get confused if the host and the card attempt to drive the I/OUC and the I/O signal low at the same time. It shoul d be noted that this is an illegal condition as all card communication is initiated by the host with a command/response protocol. The next host command should not be sent until a valid response has been completely received from the card. However, if this c ondition should occur, the 73S8014BN could set both I/OUC and I/O as outputs where they are both driven low at the same time. When either side drives their respective signal high, this mode should be released. H owever, if there is a series resistance between the host and the 73S8014BN, there may not be enough drive to release this mode. If the series resistance is greater than approximately 100Ω, this can cause this mode to become locked for the duration of the card session. If the host detects this condition (I/OUC held low for more than 1 byte time), the card session must be terminated and restarted.

73S8014BN Data Sheet DS_8014BN_057 22 Rev. 2

4 Equivalent Circuits

This section provides illustrations of circuits equivalent to those described in the pinout section. PIN VDD STRONG NFET Data From circuit Output Disable 20K ESD Figure 12: Open-Drain Type—OFF PIN ESD To Internal circuits Figure 13: Power Input/Output Circuit—VDD, VPC, VCC

73S8014BN Data Sheet DS_8014BN_057 26 Rev. 2 CLKDIV PIN VDD Vin>Vmid ESD Vmid Vlow Vhigh Vin>Vlow Vin>Vhigh ESD Figure 20: CLKDIV

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 27

5 Mechanical Drawing

0.505(12.83) 0.406(10.31) 0.296(7.52) + .003(.07) - .004(.10) ± .005(.127) + .004(.10) - .006(.15) BASE PLANE SEATING PLANE 0.505(12.83) 0.009 (.22) 0.092 (2.34) ± .002(.05) TYP + .003(.07) - .002(.06) ± .005(.127) + .0025(.07) - .004(.093) 0.01(.25) + .0025(.007) - .0009(.002) Detail A .032 (.81) Detail “A” 0°- 8° ± .008(.20) Figure 21: Mechanical Drawing 20-Pin SO Package Inches (mm)

73S8014BN Data Sheet DS_8014BN_057 28 Rev. 2

6 Ordering Information

Table 9 lists the order numbers and packaging marks used to identify 73S8014BN products. Table 9: Order Numbers and Packaging Marks PART PIN-PACKAGE TOP MARK 73S8014BN-IL/F 20 SO 73S8014BN 73S8014BN-ILR/F 20 SO 73S8014BN F = Lead(Pb)-free/RoHS-compliant package. R = Tape and reel.

7 Contact Information

For more information about Maxim products or to check the availability of the 73S8014BN, contact technical support at www.maxim-ic.com/support.

DS_8014BN_057 73S8014BN Data Sheet Rev. 2 29 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No cir cuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408 - 737- 7600  2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.

Revision History

1.0 12/10 Initial release — 2 12/11 Deleted “Certification Pending” from the NDS logo. Added “designed to provide full electrical compliance with ISO 7816-3, EMV® 4.2, and NDS specifications” to the first sentence. Added “For NDS applications requiring an on-chip adjustable POR, see the Maxim 73S8024RN series of interface ICs.” to the first paragraph. Provided additional description to Section 3.4. 16

Product Information

73S8014BN specifications and overview.

Summary

Smart Card Interface Rev 2; 12/11

Description

Smart Card Interface Rev 2; 12/11

Source title 73S8014BN Datasheet(PDF) - Maxim Integrated Products

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