73S8010R TERIDIAN | Alldatasheet

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Low Cost Smart Card Interface DATA SHEET Page: 1 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 January 2008

DESCRIPTION

The TERIDIAN 73S8010R is a single smart card interface IC. The TERIDIAN 73S8010R has been designed to provide full electrical compliance with ISO-7816-3 and EMV 4.0 (EMV2000) specifications. Interfacing with the host is done through the two-wire I 2C bus, and one interrupt output to inform the system controller of the card presence and faults. The card clock signal can be generated by an on-chip oscillator using an external crystal, or by connection to a clock signal. The TERIDIAN 73S8010R incorporates an ISO-7816-3 activation/deactivation sequenc er that controls the card signals. Level-shifters drive the card signals with the selected card voltage (3V or 5V), coming from an internal Low Drop-Out (LDO) voltage regulator. This LDO regulator is powered by a dedicated power supply input V PC. Digital circuitry is separately powered by a digital power supply VDD. With its embedded LDO regulator, the TERIDIAN 73S8010R is a cost-effective solution for any application where a 5V (typically -5% +10%) power supply is available. Hardware support for auxiliary I/O lines, C4 / C8 contacts, is provided. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a card over-current, a V DD (digital power supply), a V PC (regulator power supply), a VCC (card power supply) or an over-heating fault. The card over-current circuitry is a true current detection function, as opposed to V CC voltage drop detection, as usually implemented in ICC interface ICs. The VDD voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network. It allows automated card deactivation at a customized V DD voltage threshold value. It can be used, for instance, to match the system controller operating voltage range.

APPLICATIONS

  • Set-Top-Box Conditional Access and Pay-per- View
  • Point of Sales & Transaction Terminals
  • Control Access & Identification
  • Multiple card and SAM reader configurations ADVANTAGES
  • Single smart card interface
  • IC firmware compatible with TDA8020
  • Traditional step-up converter is replaced by a LDO regulator: Æ Greatly reduced power dissipation Æ Fewer external components are required Æ Better noise performance Æ High current capability (90mA supplied to the card)
  • Small format (5x5x0.8mm) QFN32 package option
  • True card over-current detection

FEATURES

  • Card Interface: ƒ Complies with ISO-7816-3 and EMV 4.0 ƒ A LDO voltage regulator provides 3V / 5V to the card from an external power supply input ƒ Provides at least 90mA to the card ƒ ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry ƒ Protection includes 3 voltage supervisors that detects voltage drops on V CC card and on power supplies VDD and VPC ƒ The VDD voltage supervisor threshold value can be externally adjusted ƒ Over-current detection 150mA max. ƒ 1 card detection input ƒ Auxiliary I/O lines, for C4 / C8 contact signals ƒ CLK signal up to 20MHz
  • Host Interface: ƒ Fast mode, 400kbps I2C slave bus ƒ 8 possible devices in parallel ƒ One control register and one status register ƒ Interrupt output to the host for fault detection ƒ Crystal oscillator or host clock, up to 27MHz
  • Power Supply: ƒ VPC: 4.75V to 5.5V ƒ VDD: 2.7V to 5.5V
  • 6kV ESD Protection on the card interface
  • Package: SO28 or QFN32

Low Cost Smart Card Interface DATA SHEET Page: 2 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 FUNCTIONAL DIAGRAM Pin numbers reference to the SO28 package [Pin numbers] reference to the QFN32 Package Figure 1: 73S8010R Block Diagram [2] 5 GND ICC I/O BUFFERS VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE I2C DIGITAL FAULT LOGIC VDD FAULT VCC FAULT Int_Clk VDD VPC RST CLK PRES TEMP FAULT [3] 6 [7] 10 [8] 11 [10] 12 [11] 13 [13] 15 [14] 16 [20] 21 [17] 18 [26] 26 [28] 28 [27] 27 [21] 22 ISO-7816 SEQUENCER R-C OSC. LDO REGULATOR VOLTAGE SUPERVISORS ICC RESET BUFFER ICC CLOCK BUFFER OVER TEMP I/O AUX1 AUX2 IOUC AUX1UC AUX2UC GND VDDF_ADJ XTAL OSC CLOCK GENERATION XTALIN XTALOUT [24] 25 [23] 24 NC [31] 3 SAD2 [29] 1 SAD0 [30] 2 SAD1 VCC GND [12] 14 [15] 17 GND [1] 4 [22] 23 INT [19] 20 SDA [18] 19 SCL VPC FAULT

Low Cost Smart Card Interface DATA SHEET Page: 3 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 PIN DESCRIPTION CARD INTERFACE NAME PIN (SO) PIN (QFN) DESCRIPTION I/O 11 8 Card I/O: Data signal to/from card. Includes a pull-up resistor to V CC. AUX1 13 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2 12 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. RST 16 14 Card reset: provides reset (RST) signal to card. CLK 15 13 Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by crystal oscillator frequency and CLKSEL bits in the control register. PRES 10 7 Card Presence switch: active high indicate s card is present. Includes a pull-down resistor. VCC 17 15 Card power supply – logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. GND 14 12 Card ground. MISCELLANEOUS INPUTS AND OUTPUTS NAME PIN (SO) PIN (QFN) DESCRIPTION XTALIN 24 23 Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. XTALOUT 25 24 Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock input. VDDF_ADJ 18 17 VDD threshold adjustment input: this pi n can be used to overwrite higher V DDF value (that controls deactivation of the card). Must be left open if unused. NC 7, 8, 9 4, 5, 6, 9, 16, 25, 32 Non-connected pin. POWER SUPPLY AND GROUND NAME PIN (SO) PIN (QFN) DESCRIPTION VDD 21 20 System controller interface supply vo ltage and supply voltage for internal circuitry. VPC 6 3 LDO regulator power supply source. GND 4 1 LDO regulator ground. GND 14 12 Smart Card I/O Ground. GND 5, 22 2,21 Digital ground.

Low Cost Smart Card Interface DATA SHEET Page: 4 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 MICROCONTROLLER INTERFACE NAME PIN (SO) PIN (QFN) DESCRIPTION INT 23 22 Interrupt output(negative assertion). Interrupt output signal to the processor. A 20k Ω pull up to VDD is provided internally SAD0 SAD1 SAD2 Serial device address bits. Digi tal inputs for address selection that allows for the connection of up to 8 devices in parallel. Address selections as follows: SAD2 SAD1 SAD0 I C Address (7 bits) 0 0 0 40h 0 0 1 42h 0 1 0 44h 0 1 1 46h 1 0 0 48h 1 0 1 4Ah 1 1 0 4Ch 1 1 1 4Eh Note: Pins SADO and SAD1 are internally pulled-down and SAD2 is internally pulled-up. The default address when left unconnected is 48h. SCL 19 18 I C clock signal input SDA 20 19 I C bi-directional serial data signal I/OUC 26 26 System controller data I/O to/from the card. Includes internal pull-up resistor to V DD AUX1UC 27 27 System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD AUX2UC 28 28 System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to VDD

Low Cost Smart Card Interface DATA SHEET Page: 5 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 SYSTEM CONTROLLER INTERFACE (I2C BUS) A fast-mode 400kHz I2C bus slave interface is used for controlling the device and reading the status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This allows up to 8 devices to be connected in parallel. Device Address Selections SAD2 SAD1 SAD0 I 2C Address (7 bits) 0 0 0 40h 0 0 1 42h 0 1 0 44h 0 1 1 46h 1 0 0 48h 1 0 1 4Ah 1 1 0 4Ch 1 1 1 4Eh Note: bit 0 of the I C address is the R/W bit. Refer to figures 2 and 3 for usage. CONTROL register Power On Reset = 00h Name Bit Description Start/Stop 0 When set, initiates an activation and a cold reset procedure; when reset, initiates a deactivation sequence Warm reset 1 When set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute 5Vand 3V 2 When set, VCC = 3v; when reset, VCC = 5v. When de-activating (setting bit 0 = 0) and operating with 3V (bit 2 =1), do not simultaneously set bit 2 =0. Clock Stop 3 When set, the card clock is stop ped. Bit 4 determines the card clock stop level Clock Stop Level 4 When set, card clock stops high; when reset card clock stops low Clksel1 5 Clksel2 6 Bits 5 and 6 determine the clock rate to the. See card clock rate selection table for more details. I/O enable 7 I/O enable bit. When set, I/O is transferred on I/OUC; when reset I/O to I/OUC is high impedance. Card clock rate selection table Bit Clksel2 Bit Clksel1 Card Clock 0 0 Clkin/8 0 1 Clkin/4 1 0 Clkin/2 1 1 Clkin (Xtalin)

Low Cost Smart Card Interface DATA SHEET Page: 6 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 I2C-bus Write to Control Register: I2C-bus Write command to the control register follows the format shown below. After the START condition, a slave address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts sending the 8 bits of data to the control register during the DATA bits. After the DATA bits, the ‘zero’ ACK bit is sent to the master by the device. The master should send the STOP condition after receiving this ACK bit. 1 - 78 91 - 8 9 ADDRESS bits R/ W bit ACK bit DATA bits ACK bit STOP condition START condition SCL SDA MSB MSB LSBLSB Figure 2 - I2C Bus Write Protocol STATUS register Power On Reset = 04h Name Bit Description PRES 0 Set when the card is present (pin PRES is high); reset when the card is not present. PRESL 1 Set when the PRES pin changes state (rising/falling edge); reset when the status register is read. Generates an interrupt when set. I/O 2 Set when I/O is high; reset when I/O is low. SUPL 3 Set when a voltage fault is detected; reset when the status register is read. Generates an interrupt when set PROT 4 Set when an over-current or over-heating fault has occurred during a card session; reset when the status register is read. Generates an interrupt when set MUTE 5 Set during ATR when the card has not answered during the ISO 7816-3 time window (40000 card clock cycles); reset when the next session begins. EARLY 6 Set during ATR when the card has answered before 400 card clock cycles; reset when the next session begin. ACTIVE 7 Set when the card is active (V CC is on); reset when the card is inactive.

Low Cost Smart Card Interface DATA SHEET Page: 8 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 POWER SUPPLY AND VOLTAGE SUPERVISON The TERIDIAN 73S8010R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. V DD also defines the voltage range to interface with the system controller. Three voltage supervisors constantly check the presence of the voltages V DD, VPC and V CC. A card deactivation sequence is forced upon fault of any of these vo ltage supervisors. The two voltage supervisors for V PC and V CC are linked so that a fault is generated to ac tivate a deactivation sequence when the voltage V PC becomes lower than VCC. It allows the 73S8010R to operate at lower VPC voltage when using 3V cards only. The voltage regulator can provide a current of at least 90mA on VCC that comply easily with EMV 4.0 specification. The V PC voltage supervisor threshold values are defined from EMV 4.0 standard. A third voltage supervisor monitors the VDD voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or upon fault. T he voltage threshold of the V DD voltage supervisor is internally set by default to 2.3V nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the QFN package) is used to connect an external resistor R EXT to ground to raise the VDD fault voltage to another value VDDF. The resistor value is defined as follows: REXT= 56kΩ /(VDDF - 2.33) An alternative method (more accurate) of adjusting the V DD fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as: Kx = (2.789 / V TH) - 0.6125 where VTH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas. Taking the example above, where a V DD fault threshold voltage of 2.7V is desired, solving for Kx gives: Solving for R3 gives: Æ R3 = 24000 / 0.42046 = 57080. Solving for R1 gives: Æ R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412. Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ. These values give an equivalent resistance of Kx = 0.4228, a 0.6% error. If the 2.3V default threshold is used, this pin must be left unconnected.

Low Cost Smart Card Interface DATA SHEET Page: 9 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 CARD POWER SUPPLY The card power supply is provided by the LDO regulato r, and controlled by the digital ISO-7816-3 sequencer. Card voltage selection is carried out by bit 2 of the control register. Choice of the V CC capacitor: Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that the interface must be able to provide to the card are di fferent. An external capacitor must be connected between the VCC pin and to the card ground in order to guar antee stability of the LDO regulator, and to handle the transient requirements. The type and value of this capaci tor can be optimized to meet the desired specification. The table below shows the recommended capacitors for each V PC power supply configuration and applicable specification. Table 1: Choice of VCC pin capacitor OVER-TEMPERATURE MONITOR A built-in detector monitors die temperature. Upon over-temperature condition (most likely resulting from a heavily loaded card interface, including short circuits), a card deact ivation sequence is initiated, and a fault condition is reported to the system controller (sets bit 4 of the status register and generates an interrupt). ON-CHIP OSCILLATOR AND CARD CLOCK The TERIDIAN 73S8010R devic e has an on-chip oscillator that can gene rate the smart card clock using an external crystal, connected between the pins XTALIN and XTALOUT, to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. The card clock frequency may be chosen between 4 differe nt division rates, defined by bits 5 and 6 of the I 2C Control register, as per the following table: Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs bits 3 and 4 of the I 2C Control register, respectively Clock Stop, and Clock Stop Level. Specification Requirements System Requirements Specification Min VCC Voltage allowed during transient current Max transient current charge Min VPC Power Supply required Capacitor Type Capacitor Value ISO-7816-3 4.5V 20nA.s 4.75V X5R/X7R ESR < 100mΩ 1µF Bit Clksel2 Bit Clksel1 Card Clock 0 0 Clkin/8 0 1 Clkin/4 1 0 Clkin/2 1 1 Clkin (Xtalin)

Low Cost Smart Card Interface DATA SHEET Page: 10 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 ACTIVATION SEQUENCE After Power on Reset, the signal INT is low until the VDD is stable. When VDD has been stable for approximately 10 ms and the signal INT is high, the system controller may read the status register to see if the card is present. If all the status bits are satisfied, the system controller can initiate the activation sequence by writing a ‘1’ to Start/Stop bit (bit 0) of control register. The following steps show the activation sequence and the timing of the card control signals when the system controller initiates the Start/Stop bit (bit 0) of the control register: - Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the session is aborted. - Turn I/O to reception mode at the end of t1. - CLK is applied to the card at the end of t2. - RST (to the card) is set high at the end of t3. Start/Stop VCC IO CLK RST t1 t2 t3 t 1 = 0.510 ms (timing by 1.5MHz internal Oscillator), I/O in reception mode t 2 =1.5µs, CLK starts t 3 = >42000 card clock cycles, RST set high Figure 5 - Activation Sequence

Low Cost Smart Card Interface DATA SHEET Page: 11 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 DEACTIVATION SEQUENCE Deactivation is initiated either by the system controller by resetting the Start/Stop bit, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VPC fault, VCC fault, and card extraction during the session. The following steps show the deactivation sequence and the timing of the card control signals when the system controller clears the start/stop bit: - RST goes low at the end of t1. - CLK goes low at the end of t2. - I/O goes low at the end of t3. Out of reception mode. - Shut down VCC at the end of time t4. Start/Stop RST CLK IO VCC t1 t2 t3 t4 t 1 = > .5µs t 2 = > 7.5µs t 3 = > .5µs t 4 = > .5µs Figure 6 - Deactivation Sequence

Low Cost Smart Card Interface DATA SHEET Page: 12 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 INTERRUPT Interrupt is an active low interrupt. It is set low if any of these internal faults are detected: -V CC fault -V DD fault -V PC fault Or if one of these status bits condition is detected: -Early ATR -Mute ATR -Card insert or card extract -Protection status from Ov er-current or Over-heating In case the interrupt is set low by the detection of thes e status bits, then the interrupt is set high when these status bits are read. (READ STATUS DONE) INT ANY FAULT STATUS BITS READ STATUS DONE Figure 7 - FAULT Functions, INT operation Note that a power-on-reset event will reset all of the control and status registers to their default states. A VDD fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that creates interval “t1,” not clearing the interrupt until VDD is valid for at least t 1. VDD fault can be considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of VDD fault, POR will be asserted.

Low Cost Smart Card Interface DATA SHEET Page: 13 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 WARM RESET The 73S8010R automatically asserts a warm reset to the card when instructed through the bit 1 of the I2C Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The bit Warm Reset is automatically reset when the card starts answering or when the card is declared mute. Figure 8 – Warm Reset operation Warm Reset (bit 1) RST t1 t2 t1 > 1.5µs, Warm Reset Starts t2 = 42000 card clock cycles, End of Warm Reset t3 = Resets Warm Reset bit 1 when detected ATR or Mute IO

Low Cost Smart Card Interface DATA SHEET Page: 14 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 I/O CIRCUITRY AND TIMING The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the activation sequencer enables the I/O reception state. See Activation Sequence timing section for more details on when the I/O reception is enabled. The states of the I/OUC, AU X1UC, and AUX2UC are high after power on reset. When the control I/O enable bit 7 of control register is set, t he first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O li ne. When the input I/O line rising edge is detected then both I/O lines return to their neutral state. The delay between these signals is shown in Figure 9. IO IOUC tIO_HL tIO_LH tIOUC_HL tIOUC_LH Delay from I/O to I/OUC: t IO_HL = 100ns t IO_LH = 25ns Delay from I/OUC to I/O: t IOuc_HL = 100ns t IOUC_LH = 25ns Figure 9 - I/O Timing Definition

Low Cost Smart Card Interface DATA SHEET Page: 15 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 TYPICAL APPLICATION SCHEMATIC SO28 See NOTE 4 VDD CRYSTAL 22pF ISO7816=1uF, EMV=3.3uF SDA_to/from_uC SAD1 CLK track should be routed far from RST, I/O, C4 and C8. NOTES: 1) VDD = 2.7V to 5.5V DC. 2) VPC = 4.75V(EMV, ISO) to 5.5V DC 3) Required if external clock from uP is used. 4) Required if crystal is used. Y1, C2 and C3 must be removed if external clock is used. 5) Optional. Can be left open. 6) R1 and R3 are external resistors that adjust the VDD fault voltage. Can be left open. I/OUC_to/from_uC Rext1 See NOTE 1 Card detection switch is normally closed VPC 100nF VDD External_clock_from uC 100nF 22pF AUX1UC_to.from_uC See NOTE 5 10uF AUX2UC_to/from_uC See NOTE 3 See note 2 VDD Low ESR (<100mohms) C1 should be placed near the SC connecter contact SAD0 SCK_from_uC 73S8010R 14 15 SAD0 SAD1 SAD2 GND GND VPC NC AUX2 NC NC PRES I/O AUX1 GND CLK RST VCC VDDF_ADJ SCL SDA VDD GND INT AUX2UC AUX1UC XTALOUT XTALIN I/OUC SAD2 INT_interrupt_to_uC Rext2 - OR - 20K See note 6 Smart Card Connector VCC RST CLK GND VPP I/O SW-1 SW-2 R4 R5 2K 2K 7) Hardware to define address of device See note 7 Figure 10: 73S8010R – Typical Application Schematic

Low Cost Smart Card Interface DATA SHEET Page: 16 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 ELECTRICAL SPECIFICATION ABSOLUTE MAXIMUM RATINGS Operation outside these rating limits may cause permanent damage to the device. PARAMETER RATING Supply Voltage VDD -0.5 to 6.0 VDC Supply Voltage VPC -0.5 to 6.0 VDC Input Voltage for Digital Inputs -0.3 to (V DD +0.5) VDC Storage Temperature -60 to 150°C Pin Voltage (except card interface) -0.3 to (V DD +0.5) VDC Pin Voltage (card interface) -0.3 to (V CC + 0.5) VDC ESD Tolerance – Card interface pins +/- 6kV ESD Tolerance – Other pins +/- 2kV Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. RECOMMENDED OPERATING CONDITIONS PARAMETER RATING Supply Voltage VDD 2.7 to 5.5 VDC Supply Voltage VPC 4.75 to 5.5 VDC Ambient Operating Temperature -40°C to +85°C Input Voltage for Digital Inputs 0V to V DD + 0.3V

Low Cost Smart Card Interface DATA SHEET Page: 17 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 CHARACTERISTICS: CARD INTERFACE SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Card Power Supply (VCC) Regulator General conditions, -40°C < T < 85°C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v Inactive mode -0.1 0.1 V Inactive mode ICC = 1mA -0.1 0.4 V Active mode; ICC <65mA; 5v 4.60 5.25 V Active mode; ICC <90mA; 5v 4.55 V Active mode; ICC <90mA; 3v 2.80 3.2 V Active mode; single pulse of 100mA for 2µs; 5 volt, fixed load = 25mA 4.6 5.25 V Active mode; single pulse of 100mA for 2µs; 3v, fixed load = 25mA 2.76 3.2 V Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5v 4.6 5.25 V VCC Card supply voltage including ripple and noise Active mode; current pulses of 40nAs with peak |I CC | <200mA, t <400ns; 3v 2.76 3.2 V ICCmax Maximum supply current to the card Static load current, VCC>4.6 or 2.7 volts as selected, 90 mA ICCF I CC fault current 100 150 mA VSR VCC slew rate - Rise rate on activate CF = 3.3µF on VCC 0.02 0.05 0.08 V/µs VSF VCC slew rate - Fall rate on de-activate CF = 3.3µF on VCC 0.025 0.06 0.08 V/µs CF External filter capacitor (VCC to GND) 1 3.3 5 µF

Low Cost Smart Card Interface DATA SHEET Page: 18 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. IOH =0 0.9 V CC V CC+v0.1 V VOH Output level, high (I/O, AUX1, AUX2) IOH = -40µA 0.75 VCC V CC + 0.1 V IOH =0 0.9 V DD V DD+0.1 V VOH Output level, high (I/OUC, AUX1UC, AUX2UC) IOH = -40µA 0.75 VDD V DD + 0.1 V VOL Output level, low I OL=1mA 0.3 V VIH Input level, high (I/O, AUX1, AUX2) 1.8 V CC +0.30 V VIH Input level, high (I/OUC, AUX1UC, AUX2UC) 1.8 V DD +0.30 V VIL Input level, low -0.3 0.8 V IOL = 0 0.1 V VINACT Output voltage when outside of session IOL = 1mA 0.3 V ILEAK Input leakage V IH = VCC 10 µA IIL Input current, low V IL = 0 0.65 mA ISHORTL Short circuit output current For output low, shorted to VCC through 33 ohms 15 mA ISHORTH Short circuit output current For output high, shorted to ground through 33 ohms 15 mA tR, tF Output rise time, fall times CL = 80pF, 10% to 90% For I/OUC, AUX1UC, AUX2UC, CL=50pF 100 ns tIR, tIF Input rise, fall times 1 µs RPU Internal pull-up resistor Output stable for >200ns 8 11 14 kΩ FDMAX Maximum data rate 1 MHz TFDIO Delay, I/O to I/OUC, I/OUC to I/O, AUX1 to AUX1UC, AUX1UC to AUX1, AUX2 to AUX2UC, AUX2UC to AUX2 Falling edge from master to slave measured at 50% point 60 100 200 ns TRDIO Delay, I/O to I/OUC, I/OUC to I/O, AUX1 to AUX1UC, AUX1UC to AUX1, AUX2 to AUX2UC, AUX2UC to AUX2 Rising edge from master to slave measured at 50% point 25 90 ns CIN Input capacitance 10 pF

Low Cost Smart Card Interface DATA SHEET Page: 19 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Reset and Clock for card interface, RST, CLK VOH Output level, high IOH =-200µA 0.9 VCC V CC V VOL Output level, low IOL=200µA 0 0.3 V IOL = 0 0.1 V VINACT Output voltage when outside of session IOL = 1mA 0.3 V IRST_LIM Output current limit, RST 30 mA ICLK_LIM Output current limit, CLK 70 mA CL = 35pF for CLK, 10% to 90% 8 ns tR, tF Output rise time, fall time CL = 200pF for RST, 10% to 90% 100 ns δ Duty cycle for CLK CL =35Pf, FCLK ≤ 20MHz 45 55 % CHARACTERISTICS: DIGITAL SIGNALS SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Digital I/O except for OSC I/O VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 0.7*V DD V DD + 0.3 V VOL Output Low Voltage I OL = 2mA 0.45 V VOH Output High Voltage I OH = -1mA V DD - 0.45 V ROUT Pull-up resistor, INT 20 kΩ |IIL1| Input Leakage Current GND < V IN < VDD -5 5 µA Oscillator (XTALIN) I/O Parameters VILXTAL Input Low Voltage - XTALIN -0.3 0.5 V VIHXTAL Input High Voltage - XTALIN 0.7*V DD V DD+0.3 V IILXTAL Input Current - XTALIN GND < VIN < VDD -30 30 µA DC CHARACTERISTICS SYMBOL PARAMETER Condition MIN Typ. MAX UNIT IDD Supply Current on VDD 1.5 3.0 mA IPC Supply Current on V PC VCC on, ICC=0 I/O, AUX1, AUX2=high 0.45 0.65 mA

Low Cost Smart Card Interface DATA SHEET Page: 20 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 CHARACTERISTICS I2C INTERFACE SYMBOL PARAMETER Condition MIN Typ. MAX UNIT SDA, SCL VIL Input Low Voltage -0.3 0.3* V DD V VIH Input High Voltage 0.7*V DD V DD + 0.3 V VOL Output Low Voltage I OL = 3mA 0.40 V CIN Pin capacitance 10 pF IIN Output High Voltage I OH = -1mA V DD - 0.45 V TF Output fall time CL = 0 to 400pF 20 + 0.1*CL 250 ns TSP Pulse width of spikes that are suppressed Transition from valid logic level to opposite level 50 ns VOLTAGE / TEMPERATURE FAULT DETECTION CIRCUITS SYMBOL PARAMETER Condition MIN Typ. MAX UNIT VDDF VDD fault (VDD Voltage supervisor threshold) No external resistor on VDDF_ADJ pin 2.15 2.4 V VPCF VPC fault (VPC Voltage supervisor threshold) VPC<VCC, a transient event V CC - 0.2 V VCC = 5v 4.20 4.55 V VCCF VCC fault (VCC Voltage supervisor threshold) VCC= 3v 2.5 2.7 V TF Die over temperature fault 115 145 °C

Low Cost Smart Card Interface DATA SHEET Page: 21 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 MECHANICAL DRAWING (QFN) 2.5 2.5 TOP VIEW Figure 11: QFN 32 0.85 NOM. / 0.9MAX. 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW 0.2 MIN. 0.35 / 0.45 1.5 / 1.875 3.0 / 3.75 0.18 / 0.3 BOTTOM VIEW 0.250.5 0.5 0.25 3.0 / 3.75 1.5 / 1.875 0.35 / 0.45 CHAMFERED 0.30

Low Cost Smart Card Interface DATA SHEET Page: 22 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5 PACKAGE PIN DESIGNATION (QFN) (Top View) GND GND VPC NC NC NC PRES I/O XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ NC AUX2 AUX1 GND CLK RST VCC NC TERIDIAN 73S8010R NC NC SAD2 SAD1 SAD0 AUX2UC AUX1UC I/OUC Figure 12: QFN32 73S8010R Pin Out CAUTION: Use handling procedures necessary for a static sensitive component

Low Cost Smart Card Interface DATA SHEET Page: 24 of 24 © 2005-2008 TERIDIAN Semiconductor Corporation Rev 1.5

ORDERING INFORMATION

PART DESCRIPTION ORDER NO. PACKAGING MARK 73S8010R -SOL 28-pin Lead-Free SO 73S8010R -IL/F 73S8010R -IL 73S8010R -SOL 28-pin Lead-Free SO Tape / Reel 73S8010R -ILR/F 73S8010R -IL 73S8010R -QFN 32-pin Lead-Free QFN 73S8010R -IM/F 73S8010R 73S8010R -QFN 32-pin Lead-Free QFNTape / Reel 73S8010R -IMR/F 73S8010R Data Sheet This final data sheet is proprietary to TERIDIAN Semico nductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those per taining to warranty, patent in fringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify t hat a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp. • 6440 Oak Canyon, Suite 100 • Irvine, CA • 92618-5201 TEL (714) 508-8800 • FAX (714) 508-8877 http://www.teridian.com 01/17/08 Rev 1.5