7348Q

TPS7301Q_16 TI1 | Alldatasheet

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TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V Fixed-Output and Adjustable Versions /C0068Integrated Precision Supply-Voltage Supervisor Monitoring Regulator Output Voltage /C0068Active-Low Reset Signal with 200-ms Pulse Width /C0068Very Low Dropout Voltage...M aximum of 35 mV at IO = 100 mA (TPS7350) /C0068Low Quiescent Current – Independent of Load . . . 340 mA Typ /C0068Extremely Low Sleep-State Current, 0.5 mA Max /C00682% Tolerance Over Full Range of Load, Line, and Temperature for Fixed-Output Versions /C0068Output Current Range of 0 mA to 500 mA /C0068TSSOP Package Option Offers Reduced Component Height For Critical Applications

description

The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered. AVAILABLE OPTIONS OUTPUT VOLTAGE (V) NEGATIVE-GOING RESET THRESHOLD VOLTAGE (V) PACKAGED DEVICES CHIP FORMTJ MIN TYP MAX MIN TYP MAX SMALL OUTLINE (D) PLASTIC DIP (P) TSSOP (PW) CHIP FORM (Y) 40°Ct o –40°C to Adjustable The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C. § The TPS7325 has a tolerance of ± 3% over the full temperature range. ¶ The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, offering performance similar to that of the TPS73xx but without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages (TSSOP) for applications requiring minimum package size. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. GND GND GND NC NC EN NC IN IN IN RESET NC NC FB ‡ NC SENSE † OUT OUT NC NC PW PACKAGE (TOP VIEW) NC – No internal connection † SENSE – Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350) ‡ FB – Adjustable version only (TPS7301) GND EN IN IN RESET SENSE †/FB‡ OUT OUT D OR P PACKAGE (TOP VIEW)

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

to detect an undervoltage condition on the regulated output voltage. is achieved by replacing the typical pnp pass transistor with a PMOS device. at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1). constant, independent of output loading (typically 340 mA over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. reducing the quiescent current to 0.5 mA maximum at TJ = 25°C. Figure 1. Dropout Voltage Versus Output Current Figure 2. Typical Application Configuration

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS73xxY chip information These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. (6) (4) (3) (7) (2) (1) GND FB ‡ OUT RESET IN EN TPS73xx CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. † SENSE – Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350) ‡ FB – Adjustable version only (TPS7301) BONDING PAD ASSIGNMENTS SENSE †(5) NOTE A. For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the applications information section of this data sheet. (3) (4)(5) (6) (7) (2)(1) functional block diagram Vref OUT SENSE §/FB EN IN GND RESET TPS7301 TPS7325 TPS7330 TPS7333 TPS7348 TPS7350 DEVICE UNITR1 R2 260 358 420 726 756 233 233 233 233 233 W kW kW kW kW kW RESISTOR DIVIDER OPTIONS § For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in applications information section. ¶ Switch positions are shown with EN low (active). NOTE A. Resistors are nominal values only. Delayed Reset MOS transistors Bilpolar transistors Diodes Capacitors Resistors COMPONENT COUNT 464

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ VI Vres† Vres t t t VO Threshold Voltage RESET Output 200 ms Delay 200 ms Delay Output Undefined Output Undefined VIT+ VIT– VIT– VIT+ absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. § All voltage values are with respect to network terminal ground.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions MIN MAX UNIT TPS7301Q 2.47 10 V TPS7325Q 3.1 10 V Input voltage VI† TPS7330Q 3.5 10 V Input voltage, VI† TPS7333Q 3.77 10 TPS7348Q 5.2 10 V TPS7350Q 5.33 10 High-level input voltage at EN, VIH 2 V Low-level input voltage at EN, VIL 0.5 V Output current range, IO 0 500 mA Operating virtual junction temperature range, TJ –40 125 °C † Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO , at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation: V I(min)/C0043V O(max) /C0041V DO(max load) Because the TPS7301 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rDS(on) is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for the recommended input voltage range for the TPS7301.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 mF (CSR‡ = 1 W ), SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS § TJ MIN TYP MAX UNIT Ground current (active mode) EN ≤ 0.5 V, V I = VO + 1 V, 25°C 340 400 mAGround current (active mode) EN ≤ 0.5 V, VI VO + 1 V, 0 mA ≤ IO ≤ 500 mA –40°C to 125°C 550 mA Input current (standby mode) EN V 27V ≤ V ≤ 10 V 25°C 0.01 0.5 mAInput current (standby mode) EN = VI, 2.7 V ≤ VI ≤ 10 V –40°C to 125°C 2 mA Output current limit VO =0V VI=1 0V 25°C 1.2 2 AO utput current limit VO = 0 V, VI = 10 V –40°C to 125°C 2 A Pass-element leakage current in standbyEN V 27V ≤ V ≤ 10 V 25°C 0.01 0.5 mAgy mode EN = VI, 2.7 V ≤ VI ≤ 10 V –40°C to 125°C 1 mA RESET leakage current Normal operationV at RESET 10 V 25°C 0.02 0.5 mARESET leakage current N ormal operation, V at RESET = 10 V –40°C to 125°C 0.5 mA Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C Thermal shutdown junction temperature 165 °C EN logic high (standby mode)

2.5 V ≤ VI ≤ 6 V

40°Ct o1 2 5°C VEN logic high (standby mode) 6 V ≤ VI ≤ 10 V –40°C to 125°C 2.7 V EN logic low (active mode) 27V ≤ VI≤ 10 V 25°C 0.5 VEN logic low (active mode) 2.7 V ≤ VI ≤ 10 V –40°C to 125°C 0.5 V EN hysteresis voltage 25°C 50 mV EN input current 0V ≤ VI≤ 10 V mAEN input current 0 V ≤ VI ≤ 10 V mA Minimum VIfor activepass element 25°C 2.05 2.5 VMinimum VI for active pass element –40°C to 125°C 2.5 V Minimum VIfor valid RESET IO(RESET) = 300 mA 25°C 1 1.5 VMinimum VI for valid RESET IO(RESET) = –300 mA –40°C to 125°C 1.9 V ‡ CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co. § Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT 25°C 1.182 V Reference voltage (measured at FB)2.5 V ≤ VI ≤ 10 V, See Note 1 5 mA ≤ IO ≤ 500 mA, –40°C to 125°C 1.147 1.217 V Reference voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C VI=24V 50 mA ≤ IO ≤ 150 mA 25°C 0.7 1 VI = 2.4 V, 50 mA ≤ IO ≤ 150 mA –40°C to 125°C 1 VI=24V 150 mA ≤ IO ≤ 500 mA 25°C 0.83 1.3 Pass-element series resistance VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA –40°C to 125°C 1.3 W(See Note 2) VI=29V 50 mA ≤ IO ≤ 500 mA 25°C 0.52 0.85 W VI = 2.9 V, 50 mA ≤ IO ≤ 500 mA –40°C to 125°C 0.85 VI = 3.9 V, 50 mA ≤ IO ≤ 500 mA 25°C 0.32 VI = 5.9 V, 50 mA ≤ IO ≤ 500 mA 25°C 0.23 Input regulation VI = 2.5 V to 10 V,50 mA ≤ IO ≤ 500 mA, 25°C 3 18 mVInput regulation I , See Note 1 m O , –40°C to 125°C 25 mV

2.5 V ≤ VI ≤ 10 V, IO = 5 mA to 500 mA, 25°C 5 14

I , See Note 1 O , –40°C to 125°C 25 mV O utput regulation

2.5 V ≤ VI ≤ 10 V, IO = 50 mA to 500 mA, 25°C 7 22

mVI , See Note 1 O m , –40°C to 125°C 54 mV IO =5 0mA 25°C 48 59 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 44 dBRipple rejection f = 120 H z IO = 500 mA, 25°C 45 54 dB O , See Note 1 –40°C to 125°C 44 Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz C o = 4.7 mF 25°C 95 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 25°C 89 mVrms C o = 100 mF 25°C 74 RESET trip-threshold voltage§ VO(FB) decreasing –40°C to 125°C 1.101 1.145 V RESET hysteresis voltage§ Measured at VO(FB) 25°C 12 mV RESET output low voltage§ VI= 2 13 V IO(RESET) = 400mA 25°C 0.1 0.4 VRESET output low voltage§ VI = 2.13 V, IO(RESET) = 400 mA –40°C to 125°C 0.4 V FB input current 25°C –10 0.1 10 nAFB input current –40°C to 125°C –20 20 nA † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When V I < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. This parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other programmed values, refer to Figure 33.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7325Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 10 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage 25°C 2.45 2.5 2.55 VO utput voltage 3.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.425 2.575 V IO =1 0m A VI= 2 97 V 25°C 5 IO = 10 mA , VI = 2.97 V –40°C to 125°C 14 Dropout voltage§ IO = 100 mA VI= 2 97 V 25°C 50 80 mVD ropout voltage§ IO = 100 mA , VI = 2.97 V –40°C to 125°C 150 mV IO = 500 mA VI= 2 97 V 25°C 270 400 IO = 500 mA , VI = 2.97 V –40°C to 125°C 600 Pass element series resistance§ (2.97 V – VO )/IO , VI = 2.97 V, 25°C 0.5 0.7 WPass-element series resistance§ ( O ) O , IO = 500 mA I , –40°C to 125°C 1.4 W Input regulation VI=35Vt o1 0V 50 mA ≤ IO ≤ 500 mA 25°C 6 20 mVInput regulation VI = 3.5 V to 10 V, 50 mA ≤ IO ≤ 500 mA –40°C to 125°C 25 mV IO =5m At o5 0 0m A 35V ≤ VI≤ 10 V 25°C 20 32 mV Output regulation IO = 5 mA to 500 mA , 3.5 V ≤ VI ≤ 10 V –40°C to 125°C 50 mV O utput regulation IO =5 0mA to 500 mA 35V ≤ VI≤ 10 V 25°C 28 60 mVIO = 50 mA to 500 mA , 3.5 V ≤ VI ≤ 10 V –40°C to 125°C 100 mV IO =5 0mA 25°C 50 53 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 49 dBRipple rejection f = 120 H z IO = 500 mA 25°C 49 53 dB IO = 500 mA –40°C to 125°C 32 Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz C o = 4.7 mF 25°C 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 25°C 228 mVrms C o = 100 mF 25°C 159 RESET trip-threshold voltage VO decreasing –40°C to 125°C 2.23 2.32 2.39 V RESET output low voltage VI=21V IO(RESET) =0 8 m A 25°C 0.14 0.4 VRESET output low voltage VI = 2.1 V, IO(RESET) = –0.8 mA –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7330Q electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage 25°C 3 VO utput voltage 4 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.94 3.06 V IO =1 0m A VI= 2 94 V 25°C 5.2 7 IO = 10 mA , VI = 2.94 V –40°C to 125°C 10 Dropout voltage IO = 100 mA VI= 2 94 V 25°C 52 75 mVD ropout voltage IO = 100 mA , VI = 2.94 V –40°C to 125°C 100 mV IO = 500 mA VI= 2 94 V 25°C 267 450 IO = 500 mA , VI = 2.94 V –40°C to 125°C 500 Pass element series resistance (2.94 V – VO )/IO , VI = 2.94 V, 25°C 0.5 0.7 WPass-element series resistance ( O ) O , IO = 500 mA I , –40°C to 125°C 1 W Input regulation VI=4Vt o1 0V 50 mA ≤ IO ≤ 500 mA 25°C 6 23 mVInput regulation VI = 4 V to 10 V, 50 mA ≤ IO ≤ 500 mA –40°C to 125°C 29 mV IO =5m At o5 0 0m A 4V ≤ VI≤ 10 V 25°C 20 32 mV Output regulation IO = 5 mA to 500 mA , 4 V ≤ VI ≤ 10 V –40°C to 125°C 60 mV O utput regulation IO =5 0mA to 500 mA 4V ≤ VI≤ 10 V 25°C 28 60 mVIO = 50 mA to 500 mA , 4 V ≤ VI ≤ 10 V –40°C to 125°C 120 mV IO =5 0mA 25°C 43 53 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 40 dBRipple rejection f = 120 H z IO = 500 mA 25°C 39 53 dB IO = 500 mA –40°C to 125°C 36 Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz C o = 4.7 mF 25°C 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 25°C 228 mVrms C o = 100 mF 25°C 159 RESET trip-threshold voltage VO decreasing –40°C to 125°C 2.58 2.64 2.7 V RESET output low voltage VI=26V IO(RESET) =0 8 m A 25°C 0.14 0.4 VRESET output low voltage VI = 2.6 V, IO(RESET) = –0.8 mA –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7333Q electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage 25°C 3.3 VO utput voltage 4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37 V IO =1 0m A VI= 3 23 V 25°C 4.5 7 IO = 10 mA , VI = 3.23 V –40°C to 125°C 8 Dropout voltage IO = 100 mA VI= 3 23 V 25°C 44 60 mVD ropout voltage IO = 100 mA , VI = 3.23 V –40°C to 125°C 80 mV IO = 500 mA VI= 3 23 V 25°C 235 300 IO = 500 mA , VI = 3.23 V –40°C to 125°C 400 Pass element series resistance (3.23 V – VO )/IO , VI = 3.23 V, 25°C 0.44 0.6 WPass-element series resistance ( O ) O , IO = 500 mA I , –40°C to 125°C 0.8 W Input regulation VI=43Vt o1 0V 50 mA ≤ IO ≤ 500 mA 25°C 6 23 mVInput regulation VI = 4.3 V to 10 V, 50 mA ≤ IO ≤ 500 mA –40°C to 125°C 29 mV IO =5m At o5 0 0m A 43V ≤ VI≤ 10 V 25°C 21 38 mV Output regulation IO = 5 mA to 500 mA , 4.3 V ≤ VI ≤ 10 V –40°C to 125°C 75 mV O utput regulation IO =5 0mA to 500 mA 4 3 V≤ VI≤ 10 V 25°C 31 60 mVIO = 50 mA to 500 mA , 4.3 V ≤ VI ≤ 10 V –40°C to 125°C 120 mV IO =5 0mA 25°C 43 51 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 40 dBRipple rejection f = 120 H z IO = 500 mA 25°C 39 49 dB IO = 500 mA –40°C to 125°C 36 Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz C o = 4.7 mF 25°C 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 25°C 228 mVrms C o = 100 mF 25°C 159 RESET trip-threshold voltage VO decreasing –40°C to 125°C 2.868 V RESET hysteresis voltage 25°C 18 mV RESET output low voltage VI=28V IO(RESET) =1 m A 25°C 0.17 0.4 VRESET output low voltage VI = 2.8 V, IO(RESET) = –1 mA –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7348Q electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage 25°C 4.85 VO utput voltage 5.85 V≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95 V IO =1 0m A VI= 4 75 V 25°C 2.9 6 IO = 10 mA , VI = 4.75 V –40°C to 125°C 8 Dropout voltage IO = 100 mA VI= 4 75 V 25°C 28 37 mVD ropout voltage IO = 100 mA , VI = 4.75 V –40°C to 125°C 54 mV IO = 500 mA VI= 4 75 V 25°C 150 180 IO = 500 mA , VI = 4.75 V –40°C to 125°C 250 Pass element series resistance (4.75 V – VO )/IO , VI = 4.75 V, 25°C 0.28 0.37 WPass-element series resistance ( O ) O , IO = 500 mA I , –40°C to 125°C 0.52 W Input regulation VI=58 5Vt o1 0V 50 mA ≤ IO ≤ 500 mA 25°C 9 35 mVInput regulation VI = 5.85 V to 10 V, 50 mA ≤ IO ≤ 500 mA –40°C to 125°C 37 mV IO =5m At o5 0 0m A 58 5V≤ VI≤ 10 V 25°C 28 42 mV Output regulation IO = 5 mA to 500 mA , 5.85 V ≤ VI ≤ 10 V –40°C to 125°C 80 mV O utput regulation IO =5 0mA to 500 mA 5 85 V≤ VI≤ 10 V 25°C 42 65 mVIO = 50 mA to 500 mA , 5.85 V ≤ VI ≤ 10 V –40°C to 125°C 130 mV IO =5 0mA 25°C 42 53 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 39 dBRipple rejection f = 120 H z IO = 500 mA 25°C 39 50 dB IO = 500 mA –40°C to 125°C 35 Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz C o = 4.7 mF 25°C 410 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 25°C 328 mVrms C o = 100 mF 25°C 212 RESET trip-threshold voltage VO decreasing –40°C to 125°C 4.5 4.7 V RESET hysteresis voltage 25°C 26 mV RESET output low voltage IO(RESET) =1 2 m A VI= 4 12 V 25°C 0.2 0.4 VRESET output low voltage IO(RESET) = –1.2 mA ,VI = 4.12 V –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7350Q electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage 25°C 5 VO utput voltage 6 V≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1 V IO =1 0m A VI= 4 88 V 25°C 2.9 6 IO = 10 mA , VI = 4.88 V –40°C to 125°C 8 Dropout voltage IO = 100 mA VI= 4 88 V 25°C 27 35 mVD ropout voltage IO = 100 mA , VI = 4.88 V –40°C to 125°C 50 mV IO = 500 mA VI= 4 88 V 25°C 146 170 IO = 500 mA , VI = 4.88 V –40°C to 125°C 230 Pass element series resistance (4.88 V – VO )/IO , VI = 4.88 V, 25°C 0.27 0.35 WPass-element series resistance ( O ) O , IO = 500 mA I , –40°C to 125°C 0.5 W Input regulation VI=6Vt o1 0V 50 mA ≤ IO ≤ 500 mA 25°C 4 25 mVInput regulation VI = 6 V to 10 V, 50 mA ≤ IO ≤ 500 mA –40°C to 125°C 45 mV IO =5m At o5 0 0m A 6V ≤ VI≤ 10 V 25°C 30 45 mV Output regulation IO = 5 mA to 500 mA , 6 V ≤ VI ≤ 10 V –40°C to 125°C 86 mV O utput regulation IO =5 0mA to 500 mA 6V ≤ VI≤ 10 V 25°C 45 65 mVIO = 50 mA to 500 mA , 6 V ≤ VI ≤ 10 V –40°C to 125°C 140 mV IO =5 0mA 25°C 43 53 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 38 dBRipple rejection f = 120 H z IO = 500 mA 25°C 41 51 dB IO = 500 mA –40°C to 125°C 36 Output noise-spectral density f = 120 Hz 25°C 2 mV/√Hz C o = 4.7 mF 25°C 430 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 25°C 345 mVrms C o = 100 mF 25°C 220 RESET trip-threshold voltage VO decreasing –40°C to 125°C 4.55 4.75 V RESET hysteresis voltage 25°C 28 mV RESET output low voltage IO(RESET) =1 2 m A V I= 4 25 V 25°C 0.15 0.4 VRESET output low voltage IO(RESET) = –1.2 mA , VI = 4.25 V –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER TEST CONDITIONS TJ TPS7301Q, TPS7333Q TPS7348Q, TPS7350Q UNITJ MIN TYP MAX RESET time out delay See Figure 5 25°C 140 200 260 msRESET time-out delay See Figure 5 –40°C to 125°C 100 300 ms electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TPS7301Y, TPS7333Y TPS7348Y, TPS7350Y UNIT MIN TYP MAX Ground current (active mode) EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mA VI = VO + 1 V, 340 mA Input current (standby mode) EN = VI, 2.7 V ≤ VI ≤ 10 V 0.01 mA Output current limit VO = 0 V, VI = 10 V 1.2 A Pass-element leakage current in standby mode EN = VI, 2.7 V ≤ VI ≤ 10 V 0.01 mA RESET leakage current Normal operation, V at RESET = 10 V 0.02 mA Thermal shutdown junction temperature 165 °C EN logic low (active mode) 2.7 V ≤ VI ≤ 10 V 0.5 V EN hysteresis voltage 50 mV EN input current 0 V ≤ VI ≤ 10 V 0.001 mA Minimum VI for active pass element 2.05 V Minimum VI for valid RESET IO(RESET) = –300 mA 1 V † CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7301Y electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), TJ = 25°C, FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Reference voltage (measured at FB) 1.182 V VI = 2.4 V, 50 mA ≤ IO ≤ 150 mA 0.7 VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 0.83 Pass-element series resistance (See Note 2) VI = 2.9 V, 50 mA ≤ IO ≤ 500 mA 0.52 W VI = 3.9 V, 50 mA ≤ IO ≤ 500 mA 0.32 VI = 5.9 V, 50 mA ≤ IO ≤ 500 mA 0.23 Input regulation VI = 2.5 V to 10 V, See Note 1 50 mA ≤ IO ≤ 500 mA, 3 mV Output regulation

2.5 V ≤ VI ≤ 10 V,

IO = 5 mA to 500 mA, 5 mV O utput regulation IO = 50 mA to 500 mA, 7 mV IO = 50 mA 59 Ripple rejection f = 120 Hz IO = 500 mA, See Note 1 54 dB Output noise-spectral density f = 120 Hz 2 mV/√Hz C o = 4.7 mF 95 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 89 mVrms C o = 100 mF 74 RESET hysteresis voltage§ Measured at VO(FB) 12 mV RESET output low voltage§ VI = 2.13 V, IO(RESET) = 400 mA 0.1 V FB input current 0.1 nA † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When V I < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other programmed values, refer to Figure 33.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7325Y electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 10 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage 2.5 V IO = 10 mA, VI = 2.97 V 5 Dropout voltage§ IO = 100 mA, VI = 2.97 V 50 mV IO = 500 mA, VI = 2.97 V 270 Pass-element series resistance§ (2.97 V – VO )/IO , IO = 500 mA VI = 2.97 V, 0.5 W Input regulation VI = 3.5 V to 10 V, 50 mA ≤ IO ≤ 500 mA 6 mV Output regulation IO = 5 mA to 500 mA,3.5 V ≤ VI ≤ 10 V 20 mV O utput regulation IO = 50 mA to 500 mA, 3.5 V ≤ VI ≤ 10 V 28 mV Ripple rejection f = 120 Hz IO = 50 mA 53 dBRipple rejection f = 120 H z IO = 500 mA 53 dB Output noise-spectral density f = 120 Hz 2 mV/√Hz C o = 4.7 mF 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 228 mVrms C o = 100 mF 159 RESET output low voltage VI = 2.1 V, IO(RESET) = –0.8 mA 0.14 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7330Y electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage 3 V IO = 10 mA, VI = 2.94 V 5.2 Dropout voltage IO = 100 mA, VI = 2.94 V 52 mV IO = 500 mA, VI = 2.94 V 267 Pass-element series resistance (2.94 V – VO )/IO , IO = 500 mA VI = 2.94 V, 0.5 W Input regulation VI = 4 V to 10 V, 50 mA ≤ IO ≤ 500 mA 6 mV Output regulation IO = 5 mA to 500 mA,4 V ≤ VI ≤ 10 V 20 mV O utput regulation IO = 50 mA to 500 mA, 4 V ≤ VI ≤ 10 V 28 mV Ripple rejection f = 120 Hz IO = 50 mA 53 dBRipple rejection f = 120 H z IO = 500 mA 53 dB Output noise-spectral density f = 120 Hz 2 mV/√Hz C o = 4.7 mF 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 228 mVrms C o = 100 mF 159 RESET output low voltage VI = 2.6 V, IO(RESET) = –0.8 mA 0.14 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. TPS7333Y electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage 3.3 V IO = 10 mA, VI = 3.23 V 4.5 Dropout voltage IO = 100 mA, VI = 3.23 V 44 mV IO = 500 mA, VI = 3.23 V 235 Pass-element series resistance (3.23 V – VO )/IO , IO = 500 mA VI = 3.23 V, 0.44 W Input regulation VI = 4.3 V to 10 V, 50 mA ≤ IO ≤ 500 mA 6 mV Output regulation IO = 5 mA to 500 mA,4.3 V ≤ VI ≤ 10 V 21 mV O utput regulation IO = 50 mA to 500 mA, 4.3 V ≤ VI ≤ 10 V 31 mV Ripple rejection f = 120 Hz IO = 50 mA 51 dBRipple rejection f = 120 H z IO = 500 mA 49 dB Output noise-spectral density f = 120 Hz 2 mV/√Hz C o = 4.7 mF 274 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 228 mVrms C o = 100 mF 159 RESET hysteresis voltage 18 mV RESET output low voltage VI = 2.8 V, IO(RESET) = –1 mA 0.17 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7348Y electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage 4.85 V IO = 10 mA, VI = 4.75 V 2.9 Dropout voltage IO = 100 mA, VI = 4.75 V 28 mV IO = 500 mA, VI = 4.75 V 150 Pass-element series resistance (4.75 V – VO )/IO , IO = 500 mA VI = 4.75 V, 0.28 W Input regulation VI = 5.85 V to 10 V, 50 mA ≤ IO ≤ 500 mA 9 mV Output regulation IO = 5 mA to 500 mA, 5.85 V ≤ VI ≤ 10 V 28 mV O utput regulation IO = 50 mA to 500 mA, 5.85 V ≤ VI ≤ 10 V 42 mV Ripple rejection f = 120 Hz IO = 50 mA 53 dBRipple rejection f = 120 H z IO = 500 mA 50 dB Output noise-spectral density f = 120 Hz 2 mV/√Hz C o = 4.7 mF 410 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 328 mVrms C o = 100 mF 212 RESET hysteresis voltage 26 mV RESET output low voltage IO(RESET) = –1.2 mA,VI = 4.12 V 0.2 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7350Y electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage 5 V IO = 10 mA, VI = 4.88 V 2.9 6 Dropout voltage IO = 100 mA, VI = 4.88 V 27 35 mV IO = 500 mA, VI = 4.88 V 146 170 Pass-element series resistance (4.88 V – VO )/IO , IO = 500 mA VI = 4.88 V, 0.27 0.35 W Input regulation VI = 6 V to 10 V, 50 mA ≤ IO ≤ 500 mA 4 25 mV Output regulation IO = 5 mA to 500 mA, 6 V ≤ VI ≤ 10 V 28 75 mV O utput regulation IO = 50 mA to 500 mA, 6 V ≤ VI ≤ 10 V 41 mV Ripple rejection f = 120 Hz IO = 50 mA 53 dBRipple rejection f = 120 H z IO = 500 mA 51 dB Output noise-spectral density f = 120 Hz 2 mV/√Hz C o = 4.7 mF 430 Output noise voltage 10 Hz ≤ f ≤ 100 kHz C o = 10 mF 345 mVrms C o = 100 mF 220 RESET hysteresis voltage 28 mV RESET output low voltage IO(RESET) = –1.2 mA,VI = 4.25 V 0.15 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 5. Test Circuit and Voltage Waveforms Figure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 29 through 32)

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Table of Graphs IQ Quiescent current vs Output current 7 IQ Q uiescent current vs Input voltage 8 IQ Quiescent current TPS7348 vs Free-air temperature 9 IQ Quiescent current TPS7325 vs Input voltage 10 IQ Q uiescent current TPS7325 vs Free-air temperature 11 VDO Dropout voltage vs Output current 12 DVDO Change in dropout voltage vs Free-air temperature 13 VDO Dropout voltage TPS7301 vs Output current 14 DVO Change in output voltage vs Free-air temperature 15 VO Output voltage vs Input voltage 16 VO Output voltage TPS7325 vs Input voltage 17 Line regulation 18 TPS7301 vs Output current 19 TPS7325 vs Output current 20 VO Output voltage TPS7330 vs Output current 21 VO O utput voltage TPS7333 vs Output current 22 TPS7348 vs Output current 23 TPS7350 vs Output current 24 Output voltage response from enable (EN) 25 TPS7301 or TPS7333 26 TPS7325 27 Load transient response TPS7348 or TPS7350 28 Load transient response TPS7301 29 TPS7333 30 TPS7348 or TPS7350 31 Ripple rejection vs Frequency 32 Output spectral noise density vs Frequency 33 C= 4 7 mF vs Output current 34 Compensation series resistance C o = 4.7 mF vs Added ceramic capacitance 35 (CSR) C= 1 0 mF vs Output current 36 C o = 10 mF vs Added ceramic capacitance 37 rDS(on) Pass-element resistance vs Input voltage 38 VI Minimum input voltage for valid RESET vs Free-air temperature 39 VIT– Negative-going reset threshold vs Free-air temperature 40 IOL(RESET) RESET output current vs Input voltage 41 td Reset time delay vs Free-air temperature 42 td Distribution for reset delay 43

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Quiescent Current –Am IO – Output Current – mA IQ 425 375 350 300 0 50 100 150 200 250 450 400 325 TA = 25°C TPS73xx, VI = 10 V TPS7350, VI = 6 V TPS7333, VI = 4.3 V TPS7348, VI = 5.85 V 275 TPS7330, VI = 4 V TPS7325, VI = 3.5 V Figure 8 QUIESCENT CURRENT vs INPUT VOLTAGE VI – Input Voltage – V – Quiescent Current –AmIQ 200 150 0123456 250 350 500 789 1 0 100 300 TPS7333 TPS7350 TA = 25°C IO = 500 mA TPS7301 With VO Programmed to 2.5 V 400 450 TPS7348 Figure 9 TPS7348 QUIESCENT CURRENT vs FREE-AIR TEMPERATURE 300 250 200 350 400 –50 –25 0 25 50 75 100 125 VI = 5.85 V IO = 500 mA – Quiescent Current –IQ Am TA – Free-Air Temperature – °C 450 500 Figure 10 TPS7325 QUIESCENT CURRENT vs INPUT VOLTAGE 300 250 200 350 400 3 456789 1 0 – Quiescent Current –IQ Am VI – Input Voltage – V 450 500 TA = 125°C TA = 85°C TA = 25°C TA = 0°C TA = –40°C

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Change in Output Voltage – mV –10 –20 –50 –25 0 25 50 75 100 125 VO –15 TA – Free-Air Temperature – °C D VI = VO(nom) + 1 V IO = 100 mA Figure 16 0123456 – Output Voltage – V OUTPUT VOLTAGE vs INPUT VOLTAGE 7891 0 TPS7333 TA = 25°C IO = 500 mA TPS7350 TPS7348 VO VI – Input Voltage – V TPS7301 With VO Programmed to 2.5 V and TPS7325 Figure 17 1.5 0.5 0123456 – Output Voltage – V 2.5 TPS7325 OUTPUT VOLTAGE vs INPUT VOLTAGE 7891 0 TA = 25°C 100 mA 500 mA VO VI – Input Voltage – V Figure 18 45 67 – Change In Output Voltage – mV 89 1 0 –10 –15 –20 TPS7350 TPS7348 TA = 25°C IO = 250 mA VI – Input Voltage – V D VO TPS7333 TPS7325 LINE REGULATION

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.87 4.85 4.83 4.8 0 100 300 – Output Voltage – V 4.89 4.92 500 4.91 4.9 4.88 4.86 4.84 4.82 4.81 200 400 VO IO – Output Current – mA TA = 25°C VI = 5.85 V VI = 10 V Figure 24 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS7350 5.01 4.99 4.97 4.94 0 100 300 – Output Voltage – V 5.03 5.06 400 500 5.05 5.04 5.02 4.98 4.96 4.95 200 TA = 25°C VI = 6 V VI = 10 V VO IO – Output Current – mA – Output Voltage – V OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN ) 0 20 40 60 80 100 120 140 EN Voltage – V VO TA = 25°C R L = 500 W C o = 4.7 mF (CSR = 1W ) No Input Capacitance VO(nom) Time – ms Figure 25

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–100 –200 105 TPS7348 OR TPS7350 t – Time – ms 0 100 200 300 400 500 VI = 6 V C I = 0 C o = 4.7 mF CSR = 1 W TA = 25°C – Change in Output Voltage – mVDVO – Output Current – mAIO–45 Figure 28 LINE TRANSIENT RESPONSE 100 –50 –100 6.5 6.25 TPS7301 WITH VO PROGRAMMED TO 2.5 V t – Time – ms 0 100 200 300 400 TA = 25°C C I = 0 C o = 4.7 mF (CSR = 1 W ) – Change in Output Voltage – mVDVO – Input Voltage – VVI5.75 Figure 29

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Ripple Rejection – dB f – Frequency – Hz RIPPLE REJECTION vs FREQUENCY 10 100 1 K 10 K 100 K 1 M 10 M TA = 25°C No Input Capacitance Added VI = VO + 1 V IO = 100 mA C o = 4.7 mF (CSR = 1) TPS7333 TPS7301 With VO Programmed to 2.5 V TPS7348/ TPS7350 Figure 33 10 100 1 k 10 k 100 k C o = 10 mF (CSR = 1 W ) C o = 4.7 mF (CSR = 1 W ) C o = 100 mF (CSR = 1 W ) f – Frequency – Hz OUTPUT SPECTRAL-NOISE DENSITY vs FREQUENCY 0.1 0.01 TA = 25°C No Input Capacitance Added VI = VO + 1 V Output Spectral-Noise Density – V/ Hzm Figure 34 0.1 0.01 0 50 100 150 200 250 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) † vs OUTPUT CURRENT 100 IO – Output Current – mA CSR – Compensation Series Resistance – W Region of Instability TA = 25°C VI = VO + 1 V C o = 4.7 mF No Added Ceramic Capacitance No Input Capacitance Added Region of Instability Figure 35 0.1 0.01 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) † vs ADDED CERAMIC CAPACITANCE 100 Added Ceramic Capacitance – mF 0.6 0.7 0.8 0.9 1 TA = 25°C VI = VO + 1 V IO = 500 mA C o = 4.7 mF No Input Capacitor Added Region of Instability Region of Instability CSR – Compensation Series Resistance – W

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Negative-Going Reset Threshold – mV NEGATIVE-GOING RESET THRESHOLD vs FREE-AIR TEMPERATURE –10 –15 ÁÁ ÁÁ VIT– TA – Free-Air Temperature – °C –50 –25 0 25 50 75 100 125 Figure 41 1.5 0.5 0123456 – RESET Output Current – mA 2.5 3.5 RESET OUTPUT CURRENT vs INPUT VOLTAGE 789 1 0 IOL VI – Input Voltage – V TPS7333 TPS7348 TPS7350 IL = 10 mA VOL ≤ 0.4 V TA = 25°C Figure 42 192 191 196 190 – Reset Delay Time – ms 194 193 195 RESET DELAY TIME vs FREE-AIR TEMPERATURE 197 td TA – Free-Air Temperature –°C –50 –25 0 25 50 75 100 125 Figure 43 180 185 190 195 Percentage of Units – % DISTRIBUTION FOR RESET DELAY 200 205 210 td – Reset Delay Time – ms TA = 25°C

197 Devices

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch surface-mount packages. Implementation of many of today’s high-performance devices in these packages requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are illustrated in this discussion: /C0068Improving the power-dissipation capability of the PWB design /C0068Improving the thermal coupling of the component to the PWB /C0068Introducing airflow in the system Figure 44 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves adding copper on the PWB to conduct heat away from the device. The RqJA (thermal resistance, junction-to-ambient) for this component/board system is illustrated in Figure 45. The family of curves illustrates the effect of increasing the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch × 0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper. Figure 46 shows the thermal resistance for the same system with the addition of a thermally-conductive compound between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal conductivity for the compound used in this analysis is 0.815 W/m × °C. Using these figures to determine the system R qJA allows the maximum power-dissipation limit to be calculated with the equation: P D(max) /C0043 TJ(max)/C0042TA R /C0113JA(system) Where TJ(max) is the maximum allowable junction temperature; 150°C absolute maximum and 125°C maximum recommended operating temperature for specified operation. This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation for calculating total internal power dissipation of the TPS73xx is: P D(total)/C0043/C0466V I/C0042V O /C0467/C0032IO /C0041V I /C0032IQ Because the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifying the equation to: P D(total)/C0043/C0466V I/C0042V O /C0467/C0032IO For a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the device body, where TA = 55°C, airflow = 100 ft/min, and copper heat sink area = 1 cm2, the maximum power-dissipation limit can be calculated. As indicated in Figure 46, the system RqJA is 94°C/W; therefore, the maximum power-dissipation limit is: P D(max) /C0043 TJ(max)/C0042TA R /C0113JA(system) /C0043125 C /C004255 C

94 C/C0324W /C0043745 mW°

If the system implements a TPS7348 regulator where VI = 6 V and IO = 150 mA, the internal power dissipation is: P D(total)/C0043/C0466V I/C0042V O /C0467/C0032IO /C0043(6/C00424.85)/C00320.150/C0043173 mW

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 44. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOP

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The TPS73xx series of low-dropout (LDO) regulators overcome many of the shortcomings of earlier generation LDOs, while adding features such as a power-saving shutdown mode and a supply-voltage supervisor. The TPS73xx family includes five fixed-output voltage regulators: the TPS7325 (2.5 V), TPS7330 (3 V), TPS7333 (3.3 V), the TPS7348 (4.85 V), and the TPS7350 (5 V). The family also offers an adjustable device, the TPS7301 (adjustable from 1.2 V to 9.75 V). device operation The TPS73xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (I B = IC /b). Close examination of the data sheets reveals that such devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves (see Figure 7). The TPS73xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS73xx specifications reflect actual performance under load. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in b forces an increase in I B to maintain the load. During power-up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS73xx quiescent current remains low even when the regulator drops out, thus eliminating both problems. Included in the TPS73xx family is a 4.85-V regulator, the TPS7348. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges. The TPS73xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 0.5 mA. When the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is reestablished in typically 120 ms. minimum load requirements The TPS73xx family is stable even at zero load; no minimum load is required for operation. SENSE connection The SENSE terminal of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way as to minimize/avoid noise pickup. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate. external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 mF) improves load transient response and noise rejection when the TPS73xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

external capacitor requirements (continued) As with most LDO regulators, the TPS73xx family requires an output capacitor for stability. A low-ESR 10-mF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 42). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 W over temperature. Capacitors with published ESR specifications such as the AVX TPSD106M035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at 25°C is 300 mW (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the temperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem, physically smaller, 10-mF devices can be screened for ESR. Figures 29 through 32 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance. In applications with little or no high-frequency bypass capacitance (< 0.2 mF), the output capacitance can be reduced to 4.7 mF, provided ESR is maintained between 0.7 and 2.5 W . Because capacitor minimum ESR is seldom if ever specified, it may be necessary to add a 0.5-W to 1-W resistor in series with the capacitor and limit ESR to 1.5 W maximum. As shown in the CSR graphs (Figures 29 through 32), minimum ESR is not a problem when using 10-mF or larger output capacitors. Below is a partial listing of surface-mount capacitors usable with the TPS73xx family. This information, along with the CSR graphs, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. All load and temperature conditions with up to 1 mF of added ceramic load capacitance: PART NO. MFR. VALUE MAX ESR † SIZE (H × L × W)† T421C226M010AS Kemet 22 mF, 10 V 0.5 2.8 × 6 × 3.2 593D156X0025D2W Sprague 15 mF, 25 V 0.3 2.8 × 7.3 × 4.3 593D106X0035D2W Sprague 10 mF, 35 V 0.3 2.8 × 7.3 × 4.3 TPSD106M035R0300 AVX 10 mF, 35 V 0.3 2.8 × 7.3 × 4.3 Load < 200 mA, ceramic load capacitance < 0.2 mF, full temperature range: PART NO. MFR. VALUE MAX ESR † SIZE (H × L × W)† 592D156X0020R2T Sprague 15 mF, 20 V 1.1 1.2 × 7.2 × 6 595D156X0025C2T Sprague 15 mF, 25 V 1 2.5 × 7.1 × 3.2 595D106X0025C2T Sprague 10 mF, 25 V 1.2 2.5 × 7.1 × 3.2 293D226X0016D2W Sprague 22 mF, 16 V 1.1 2.8 × 7.3 × 4.3 Load < 100 mA, ceramic load capacitance < 0.2 mF, full temperature range: PART NO. MFR. VALUE MAX ESR † SIZE (H × L × W)† 195D106X0016X2T Sprague 10 mF, 16 V 1.5 1.3 × 7 × 2.7 595D156X0016B2T Sprague 15 mF, 16 V 1.8 1.6 × 3.8 × 2.6 695D226X0015F2T Sprague 22 mF, 15 V 1.4 1.8 × 6.5 × 3.4 695D156X0020F2T Sprague 15 mF, 20 V 1.5 1.8 × 6.5 × 3.4 695D106X0035G2T Sprague 10 mF, 35 V 1.3 2.5 × 7.6 × 2.5 † Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Resistors R1 and R2 should be chosen for approximately 7-mA divider current. A recommended value for R2 is 169 kW with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at FB will introduce an error. Solving for R1 yields a more useful equation for choosing the appropriate resistance: R1 /C0043 /C0466 V O V ref /C00421/C0467/C0032R2 OUTPUT VOLTAGE R1 R2 2.5 V 3.3 V 3.6 V 4 V 5 V 6.4 V UNIT 191 309 348 402 549 750 169 169 169 169 169 169 kW kW kW kW kW kW OUTPUT VOLTAGE PROGRAMMING GUIDE VO RESET OUT FB GND EN IN <0.5 V >2.7 V TPS7301 To System Reset0.1 mF 250 kW VI CSR = 1 W 10 mF Figure 48. TPS7301 Adjustable LDO Regulator Programming IT+), a 200-ms (typical) timeout period begins during which the RESET output remains low. NMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated. decays below the minimum required for a valid RESET, the RESET is undefined. signal active during the 200-ms (typical) timeout period.

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124F – JUNE 1995 – REVISED JANUARY 1999 39POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 undervoltage supervisor function (continued) Transient loads or line pulses can also cause a reset to occur if proper care is not taken in selecting the input and output capacitors. Load transients that are faster than 5 ms can cause a reset if high-ESR output capacitors (greater than approximately 7 W ) are used. A 1-ms transient causes a reset when using an output capacitor with greater than 3.5 W of ESR. Note that the output-voltage spike during the transient can drop well below the reset threshold and still not trip if the transient duration is short. A 1-ms transient must drop at least 500 mV below the threshold before tripping the reset circuit. A 2-ms transient trips RESET at just 400 mV below the threshold. Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used when fast transients are expected. NOTE: VIT+ = VIT– +Hysteresis output noise The TPS73xx has very low output noise, with a spectral noise density < 2 mV/√Hz. This is important when noise-susceptible systems, such as audio amplifiers, are powered by the regulator. regulator protection The TPS73xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be appropriate. The TPS73xx also features internal current limiting and thermal protection. During normal operation, the TPS73xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes.

www.ti.com 11-Sep-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS7301QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7301Q TPS7301QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7301Q TPS7301QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7301Q TPS7301QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7301Q TPS7301QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TPS7301QP TPS7301QPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7301 TPS7301QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 125 TPS7325QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 7325Q TPS7325QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 7325Q TPS7325QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TPS7325QP TPS7325QPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PT7325 TPS7325QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PT7325 TPS7330QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7330Q TPS7330QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7330Q TPS7330QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7330Q TPS7330QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TPS7330QP TPS7333QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7333Q

www.ti.com 11-Sep-2016 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS7333QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7333Q TPS7333QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7333Q TPS7333QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7333Q TPS7333QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TPS7333QP TPS7333QPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7333 TPS7333QPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7333 TPS7333QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 125 TPS7333QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7333 TPS7348QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7348Q TPS7348QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7348Q TPS7348QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 125 TPS7350QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7350Q TPS7350QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7350Q TPS7350QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7350Q TPS7350QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 7350Q TPS7350QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TPS7350QP TPS7350QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TPS7350QP TPS7350QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 125 TPS7350QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7350

www.ti.com 11-Sep-2016 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS7350QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PT7350 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7301QDR SOIC D 8 2500 367.0 367.0 38.0 TPS7325QPWR TSSOP PW 20 2000 367.0 367.0 38.0 TPS7330QDR SOIC D 8 2500 367.0 367.0 38.0 TPS7333QDR SOIC D 8 2500 367.0 367.0 38.0 TPS7333QPWR TSSOP PW 20 2000 367.0 367.0 38.0 TPS7348QDR SOIC D 8 2500 367.0 367.0 38.0 TPS7350QDR SOIC D 8 2500 367.0 367.0 38.0 TPS7350QPWR TSSOP PW 20 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 2

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