TDA7343 STMICROELECTRONICS | Alldatasheet
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DIGITALLY CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER - TWO STEREO AND ONE MONO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES FULLY PROGRAMMABLE LOUDNESS FUNCTION VOLUME CONTROL IN 0.3dB STEPS IN- CLUDING GAIN UP TO 20dB ZERO CROSSING MUTE AND DIRECT MUTE SOFT MUTE CONTROLLED BY SOFTWARE OR HARDWARE PIN BASS AND TREBLE CONTROL FOUR SPEAKER ATTENUATORS - FOUR INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCEAND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SE- RIAL I
2 CBUS
DESCRIPTION
The TDA7343 is an upgrade of the TDA7313 audioprocessor. Thanks to the used BIPOLAR/CMOS technology, very low distortion, low noise and DC-stepping are obtained. Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained Several new features like softmute, zero-crossing mute and pause detector are implemented. The Soft Mute function can be activated in two ways:
1 Via serial bus (bit D0, Mute Byte)
2 Directly on pin 22 through an I/O line of the
Very low DC stepping is obtained by use of a BICMOS technology. November 1999 ORDERING NUMBER: TDA7343 (DIP28) TDA7343D (SO28) DIP28 SO28
+ GAIN LEFT INPUTS RIGHT INPUTS SUPPLY ZERO CROSS + MUTE SOFT MUTE OUT(L) IN(L) 17 16 LOUD+ VOL ZERO CROSS + MUTE LOUD+ VOL BASS BASS LOUD(L) TREBLE TREBLE 10µF OUT(R)CREF IN(R) LOUD(R) BOUT(L) BIN(L) 19 18 BOUT(R) BIN(R) 21 20 5 TREBLE(R) SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE TREBLE(L) OUT LEFT FRONT OUT LEFT REAR SCL SDA OUT RIGHT FRONT OUT RIGHT REAR D93AU062B BUSSERIAL BUS DECODER + LATCHES 2 x 1µF 2 x 1µF AGND VS C8 2.2µF C7 2.2µF C9 47nF RB C11 100nF C12 100nF 4.7K C13 2.7nF C10 100nF C14 100nF C15 100nF C16 2.7nF 4.7K CSM RB CSM SM BLOCK DIAGRAM TDA7343
Symbol Parameter Value Unit VS Operating Supply Voltage 10.5 V Tamb Operating Ambient Temperature -40 to 85 °C Tstg Storage Temperature Range -55 to 150 °C THERMAL DATA Symbol Parameter DIP28 SO28 Unit R th j-amb Thermal Resistance Junction-pins 85 65 °C/W QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. Unit VS Supply Voltage 6 9 10.2 V VCL Max. input signal handling 2.1 2.6 Vrms THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.08 % S/N Signal to Noise Ratio 106 dB S C Channel Separation f = 1KHz 100 dB Volume Control 0.3dB step -59.7 20 dB Treble Control 2dB step -14 +14 dB Bass Control 2dB step -10 +18 dB Fader and Balance Control 1.25dB step -38.75 0 dB Input Gain 3.75dB step 0 11.25 dB Mute Attenuation 100 dB IN(R) OUT(R) LOUD R IN R2 IN R1 LOUD L AM MONO IN L2 IN L1 CSM IN(L) OUT(L) BOUT(L) BIN(L) BIN(R) BOUT(R) SM OUT RR23 D94AU061B CREF V S GND L R OUT LR OUT RF OUT LF SDA SCL TREBLE BUS INPUTS BASS PIN CONNECTION TDA7343
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ ;Rg =5 0Ω ;Tamb =2 5°C; all controls flat (G - 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit INPUT SELECTOR R I Input Resistance 70 100 130 K Ω VCL Clipping Level d ≤ 0.3% 2.1 2.6 V RMS SI Input Separation 80 100 dB R L Output Load Resistance 2 K Ω G I MIN Minimum Input Gain -0.75 0 0.75 dB G I MAX Maximum Input Gain 10.25 11.25 12.25 dB G step Step Resolution 2.75 3.75 4.75 dB eN Input Noise 20Hz to 20 KHz unweighted 2.3 µV VDC DC Steps Adiacent Gain Steps 1.5 10 mV G IMIN to GIMAX 3m V VOLUME CONTROL R I Input Resistance 35 50 K Ω G MAX Maximum Gain 18.75 20 21.25 dB AMAX Maximum Attenuation 57.7 59.7 62.7 dB ASTEPC Step Resolution Coarse Attenuation 0.5 1.25 2.0 dB ASTEPF Step Resolution Fine Attenuation 0.11 0.31 0.51 dB E A Attenuation Set Error G = 20 to -20dB -1.25 0 1.25 dB G = -20 to -58dB -3 2 dB Et Tracking Error 2d B VDC DC Steps Adiacent Attenuation Steps -3 0 3 mV From 0dB to AMAX 0.5 5 mV LOUDNESS CONTROL R I Internal Resistor Loud = ON 35 50 65 K Ω AMAX Maximum Attenuation 17.5 18.75 20.0 dB Astep Step Resolution 0.5 1.25 2.0 dB ZERO CROSSING MUTE VTH Zero Crossing Threshold (note 1) WIN = 11 20 mV WIN = 10 40 mV WIN = 01 80 mV WIN = 00 160 mV AMUTE Mute Attenuation 80 100 dB VDC DC Step 0dB to Mute 0 3 mV SOFT MUTE AMUTE Mute Attenuation 60 dB TDON ON Delay Time C CSM = 22nF; 0 to -20dB; I = IMAX 0.7 1 1.7 ms C CSM = 22nF; 0 to -20dB; I = IMIN 20 35 55 ms TDOFF OFF Delay Time V CSM = 0V;I = IMAX 25 50 75 µA VCSM = 0V; I = IMIN 1 µA VTHSM Soft Mute Threshold 1.5 2.5 3.5 V R INT Pullup Resistor (pin 22) (note 2) 35 50 65 K Ω VSMH (pin 22) Level High Soft Mute Active 3.5 V VSML (pin 22) Level Low 1V TDA7343
ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit BASS CONTROL BBOOST Max Bass Boost 15 18 20 dB BCUT Max Bass Cut -8.5 -10 -11.5 dB Astep Step Resolution 1 2 3 dB R g Internal Feedback Resistance 45 65 85 K Ω TREBLE CONTROL C RANGE Control Range ±13 ±14 ±15 dB Astep Step Resolution 1 2 3 dB SPEAKER ATTENUATORS C RANGE Control Range 35 37.5 40 dB Astep Step Resolution 0.5 1.25 2.0 dB AMUTE Output Mute Attenuation Data Word = XXX11111 80 100 dB E A Attenuation Set Error 1.25 dB VDC DC Steps Adjacent Attenuation Steps 0 3 mV AUDIO OUTPUT Vclip Clipping Level d = 0.3% 2.1 2.6 Vrms R L Output Load Resistance 2 K Ω R O Output Impedance 30 100 Ω VDC DC Voltage Level 3.5 3.8 4.1 V GENERAL VCC Supply Voltage 6 9 10.2 V ICC Supply Current 5 10 15 mA PSRR Power Supply Rejection Ratio f = 1KHz 60 80 dB B = 20 to 20kHz ”A” weighted 65 dB eNO Output Noise Output Muted (B= 20 to 20kHz flat) 2.5 µV All Gains0dB (B = 20 to 20kHz flat) 5 15 µV Et Total Tracking Error A V = 0 to -20dB 0 1 dB AV = -20 to -60dB 0 2 dB S/N Signal to Noise Ratio All Gains = 0dB; V O =1 Vrms 106 dB SC Channel Separation 80 100 dB d Distortion V in= 1V 0.01 0.08 % BUS INPUTS VIL Input Low Voltage 1V V lN Input High Voltage 3 V IlN Input Current VIN = 0.4V -5 5 µA VO Output Voltage SDA Acknowledge IO = 1.6mA 0.4 0.8 V Note 1: WIN represents the MUTE programming bit pair D6,D 5 for the zero crossing window threshold Note 2: Internal pullup resistor to Vs/2; ”LOW” = softmute active TDA7343
0 0 1 1 Bass, Treble 0 1 0 0 Speaker Attenuator LF 0 1 0 1 Speaker Attenuator LR 0 1 1 0 Speaker Attenuator RF 0 1 1 1 Speaker Attenuator RR 1 0 0 0 Mute AUTO INCREMENT If bit I in the subaddress byte is set to ”1”, the autoincrement of the subaddress is enabled SUBADDRESS (receive mode) CHIP ADDRESS SUBADDRESS DATA 1 to DATA n MSB LSB MSB LSB MSB LSB S1000100 R / W ACK X X X I A3 A2 A1 A0 ACK DATA ACK P ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used MAX CLOCK SPEED 500kbits/s TRANSMITTED DATA Send Mode MSB LSB X X X X X SM ZM X ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automaticallyupdated after each ACK. Transmission can be repeated without new chip address. SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines read/write transmission) A subaddressbyte. A sequenceof data (N-bytes + acknowledge) A stop condition (P) TDA7343
X = not relevant; set to ”1” during testing MSB LSB FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 X X 1 0 0 0 not used X X 1 0 0 1 IN 2 X X 1 0 1 0 IN 1 X X 1 0 1 1 AM mono X X 1 1 0 0 not used X X 1 1 0 1 not used X X 1 1 1 0 not allowed X X 1 1 1 1 not allowed X X 1 0 0 11.25dB gain X X 1 0 1 7.5dB gain X X 1 1 0 3.75dB gain X X 1 1 1 0dB gain For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X101001 Input Selector MSB LSB FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 XXX00000 0 d B X X X 0 0 0 0 1 -1.25dB X X X 0 0 0 1 0 -2.5dB X X X 0 0 0 1 1 -3.75dB X X X 0 0 1 0 0 -5dB X X X 0 0 1 0 1 -6.25dB X X X 0 0 1 1 0 -7.5dB X X X 0 0 1 1 1 -8.75dB X X X 0 1 0 0 0 -10dB X X X 0 1 0 0 1 -11.25dB X X X 0 1 0 1 0 -12.5dB X X X 0 1 0 1 1 -13.75dB X X X 0 1 1 0 0 -15dB X X X 0 1 1 0 1 -16.25dB X X X 0 1 1 1 0 -17.5dB X X X 0 1 1 1 1 -18.75dB X X X 1 D3 D2 D1 D0 Loudness OFF (1) For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0 NOTE 1: If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the attenuation level. Loudness TDA7343
1 Soft Mute On
0 1 Soft Mute with fast slope (I = IMAX ) 1 1 Soft Mute with slow slope (I = IMIN )
1 Direct Mute
00 Zero Crossing Mute Off (delayed until next
zerocrossing)
1 Zero Crossing Mute and Pause Detector Reset
0 0 160mV ZC Window Threshold (WIN = 00) 0 1 80mV ZC Window Threshold (WIN = 01) 1 0 40mV ZC Window Threshold (WIN = 10) 1 1 20mV ZC Window Threshold (WIN = 11)
0 Nonsymmetrical Bass Cut (note 4)
1 Symmetrical Bass Cut
An additionaldirect mute function is included in the Speaker Attenuators. Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain) Mute MSB LSB SPEAKER ATTENUATOR LF, LR, RF, RR D7 D6 D5 D4 D3 D2 D1 D0 1.25dB step XXX 000 0 d B X X X 0 0 1 -1.25dB X X X 0 1 0 -2.5dB X X X 0 1 1 -3.75dB XXX 100 - 5 d B X X X 1 0 1 -6.25dB X X X 1 1 0 -7.5dB X X X 1 1 1 -8.75dB 10dB step XXX00 0 d B X X X 0 1 -10dB X X X 1 0 -20dB X X X 1 1 -30dB XXX11111 Speaker Mute For example an attenuationof 25dB on a selected output is given by: X X X1 0 1 0 0 Speaker Attenuators TDA7343
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1 Bass/Treble TDA7343
0.31dB Fine Attenuation Steps 0 0 0dB 0 1 -0.31dB 1 0 -0.62dB 1 1 -0.94dB 1.25dB Coarse Attenuation Steps 000 0 d B 0 0 1 -1.25dB 0 1 0 -2.5dB 0 1 1 -3.75dB 1 0 0 -5dB 1 0 1 -6.25dB 1 1 0 -7.5dB 1 1 1 -8.75dB 10dB Gain / Attenuation Steps 000 20dB 001 10dB 010 0dB 0 1 1 -10dB 1 0 0 -20dB 1 0 1 -30dB 1 1 0 -40dB 1 1 1 -50dB For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0 Volume Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. TDA7343
DIM. mm inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S8 ° (max.) OUTLINE AND MECHANICAL DATA TDA7343
DIM. mm inch a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 D 37.34 1.470 E 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F 14.1 0.555 I 4.445 0.175 L 3.3 0.130 DIP28 OUTLINE AND MECHANICAL DATA TDA7343
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com TDA7343