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IDT72V01_12 IDT | Alldatasheet

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3.3 VOLT CMOS ASYNCHRONOUS FIFO

512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 IDT72V01, IDT72V02 IDT72V03, IDT72V04 IDT72V05, IDT72V06 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3033/7 FEATURES:

• •••• 3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/ 7205/7206 family
• •••• 512 x 9 organization (72V01)
• •••• 1,024 x 9 organization (72V02)
• •••• 2,048 x 9 organization (72V03)
• •••• 4,096 X 9 organization (72V04)
• •••• 8,192 x 9 organization (72V05)
• •••• 16,384 X 9 organization (72V06)
• •••• Functionally compatible with 720x family
• •••• Low-power consumption — Active: 180 mW (max.) — Power-down: 18 mW (max.)
• •••• Asynchronous and simultaneous read and write
• •••• Fully expandable by both word depth and/or bit width
• •••• Status Flags: Empty, Half-Full, Full
• •••• Auto-retransmit capability
• •••• Available in 32-pin PLCC
• •••• Industrial temperature range (–40 °°°°°C to +85 °°°°°C) is available
• •••• Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM W WRITE CONTROL READ CONTROLR FLAG LOGIC EXPANSION LOGICXI WRITE POINTER RAM ARRAY 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 16,384 x 9 READ POINTER DATA INPUTS RESET LOGIC THREE- STATE BUFFERS DATA OUTPUTS EF FF XO/HF RS FL/RT (D0-D8) 3033 drw 01 (Q0-Q8) DESCRIPTION: The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V. Their architecture, functional operation and pin assignments are identical to those of the IDT7201/7202/7203/7204/7205/7206. These devices load and empty data on a first-in/first-out basis. They use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices have a maximum data access time as fast as 25 ns. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. They also feature a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. It has been designed for those applications requiring asynchronous and simultane- ous read/writes in multiprocessing and rate buffer applications.

IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9 PIN CONFIGURATION IDT72V01 IDT72V02 IDT72V03 IDT72V05 IDT72V04 IDT72V06 Commercial & Industrial(1) Commercial & Industrial(1) tA = 15, 25, 35 ns t A = 15, 25, 35 ns Symbol Parameter Min. Max. Min. Max. Unit ILI(2) Input Leakage Current (Any Input) –1 1 –1 1 μA ILO(3) Output Leakage Current –10 10 –10 10 μA VOH Output Logic “1” Voltage IOH = –2mA 2.4 — 2.4 — V VOL Output Logic “0” Voltage IOL = 8mA — 0.4 — 0.4 V ICC1(4,5) Active Power Supply Current — 60 — 75 mA ICC2(4,6) Standby Current (R=W=RS=FL/RT=VIH)— 5 — 5 m A NOTES: 1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are a vailable by special order. 2. Measurements with 0.4 ≤ V IN ≤ V CC. 3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs open (I OUT = 0). 5. Tested at f = 20 MHz. 6. All Inputs = V CC - 0.2V or GND + 0.2V. PLCC (J32-1, order code: J) TOP VIEW Symbol Rating Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V GND Supply Voltage 0 0 0 V VIH(1) Input High Voltage 2.0 — V CC+0.5 V VIL(2) Input Low Voltage — — 0.8 V TA Operating Temperature Commercial 0 — 70 °C TA Operating Temperature Industrial –40 — 85 °C Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage –0.5 to +7.0 V with Respect to GND TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA NOTES: 1. For RT/RS/XI input, V IH = 2.6V (commercial). For RT/RS/XI input, V IH = 2.8V (military). 2. 1.5V undershoots are allowed for 10ns once per cycle. D2 5 D1 6 D0 7 XI 8 FF 9 Q0 10 Q1 11 NC 12 Q2 13 NC FL/RT RS EF XO/HF Q 3 2 1 32 31 30 14 15 16 17 18 19 20 GND NC R W NC VCC D5INDEX 3033 drw 02b Symbol Parameter(1) Condition Max. Unit CIN Input Capacitance V IN = 0V 8 pF COUT Output Capacitance V OUT = 0V 8 pF RECOMMENDED DC OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = –40°C to +85°C) NOTE: 1. Characterized values, not currently tested. CAPACITANCE (TA = +25°C, f = 1.0 MHz)

1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for the 25ns speed grade is available as a standard device.

All other speed grades are available by special order.

1. Pulse widths less than minimum value are not allowed.
2. Values guaranteed by design, not currently tested.
3. Only applies to read data flow-through mode.

Figure 1. Output Load

• Includes scope and jig capacitances.

IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9 SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0 – D8) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, (i.e., t RSS before the rising edge of RS ) and should not change until tRSR after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset (RS). WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data setup and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any ongoing read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after t RFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 – Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after t WEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). These FIFOs can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 512/1,024/2,048/4,096/8,192/16,384 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 512/1,024/2,048/4,096/8,192/16,384 writes to the IDT72V01/ 72V02/72V03/72V04/72V05/72V06. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Q 0 – Q8) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a HIGH state.

IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9 OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. SINGLE DEVICE MODE A single IDT72V01/72V02/72V03/72V04/72V05/72V06 may be used when the application requirements are for 512/1,024/2,048/4,096/8,192/ 16,384 words or less. These devices are in a Single Device Configuration when the Expansion In ( XI ) control input is grounded (see Figure 12). These FIFOs can easily be adapted to applications when the requirements are for greater than 512/1,024/2,048/4,096/8,192/16,384 words. Figure 14 demonstrates Depth Expansion using three IDT72V01/72V02/72V03/72V04/ 72V05/72V06s. Any depth can be attained by adding additional IDT72V01/ 72V02/72V03/72V04/72V05/72V06s. These devices operate in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load ( FL ) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out ( XO ) pin of each device must be tied to the Expansion In ( XI ) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag ( FF ) and Empty Flag ( EF ). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit ( RT ) function and Half-Full Flag ( HF ) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules. USAGE MODES: WIDTH EXPANSION Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT72V01/72V02/72V03/72V04/72V05/72V06s. Any word width can be attained by adding additional IDT72V01/72V02/72V03/72V04/72V05/72V06s (Figure 13). BIDIRECTIONAL OPERATION Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72V01/72V02/72V03/72V04/72V05/72V06s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. DATA FLOW-THROUGH Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (t WEF + tA) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after t RHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer.

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ORDERING INFORMATION

NOTES: 1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are a vailable by special order. 2. Green parts are available. For specific speeds and packages contact your local sales office. XXXXX Device Type XXX Speed X Power X Package X Process/ Temperature Range Blank I(1) 72V01 72V02 72V03 72V04 72V05 72V06 Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 512 x 9 FIFO 1,024 x 9 FIFO 2,048 x 9 FIFO 4,096 x 9 FIFO 8,192 x 9 FIFO 16,384 x 9 FIFO Access Time (tA) Speed in Nanoseconds L Low Power J Plastic Leaded Chip Carrier (PLCC, J32-1) 3033 drw 21 Commercial Only Com'l and Ind'l Commercial Only X G(2) Green X Blank Tube or Tray Tape and Reel DATASHEET DOCUMENT HISTORY 08/29/2001 pg. 3. 04/08/2003 pg. 2. 05/05/2003 pg. 2. 03/09/2006 pgs. 1 and 12. 10/22/2008 pgs. 12. 06/29/2012 pgs. 1 and 12.