IDT728980 RENESAS | Alldatasheet

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  • Manufacturer or author: gvasquez
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2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.© IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. DSC-5706/2 FUNCTIONAL BLOCK DIAGRAM Microprocessor Interface Control Register Timing Unit RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 ODEF0iC4i VCC CSDS R/W A0/ GND CCODTA D0/ 5706 drw01 Data Memory Output MUX Connection Memory Receive Serial Data Streams Transmit Serial Data Streams FEATURES:

  • •••• 256 x 256 channel non-blocking switch
  • •••• Serial Telecom Bus Compatible (ST-BUS ®)
  • •••• 8 RX inputs—32 channels at 64 Kbit/s per serial line
  • •••• 8 TX output—32 channels at 64 Kbit/s per serial line
  • •••• Three-state serial outputs
  • •••• Microprocessor Interface (8-bit data bus)
  • •••• Available in 44-pin Plastic Leaded Chip Carrier (PLCC)
  • •••• Operating Temperature Range -40°°°°°C to +85°°°°°C DESCRIPTION: The IDT728980 is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT728980 can handle as many as 256, 64 Kbit/s input and output channels. Those 256 channels are divided into 8 serial inputs and outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream. FUNCTIONAL DESCRIPTION A functional block diagram of the IDT728980 device is shown on below. The serial ST-BUS® streams operate continuously at 2.048 Mb/s and are arranged in 125μs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT728980 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock (C4i) for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 256-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed.

COMMERCIAL TEMPERATURE RANGE IDT728980 Time Slot Interchange Digital Switch 256 x 256 5706 drw02 INDEX 3940 DS CS R/W RX2 RX1 RX0 DTA TX0 TX1 TX2 DNC(1) CCO ODE TX3 TX4 TX5 TX6 TX7 GND RX3 RX4 RX5 RX6 RX7 VCC F0i C4i DNC(1)DNC(1) DNC(1) PIN CONFIGURATION PIN DESCRIPTIONS (J44, order code: J) TOP VIEW SYMBOL NAME I/O DESCRIPTION GND Ground. Ground Rail. VCC VCC +5.0 Volt Power Supply. DTA Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at th is (Open Drain) output. RX0-7 RX Input 0 to 7 I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. F0i Frame Pulse I This input identifies frame synchronization signals formatted to ST-BUS ® specifications. C4i Clock I 4.096 MHz serial clock for shifting data in and out of the data streams. A0-A5 Address 0 to 5 I These lines provide the address to IDT728980 internal registers. DS Data Strobe I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. R/W Read/Write I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. CS Chip Select I Active LOW input enabling a microprocessor read or write of control register or internal memories. D0-D7 Data Bus 0 to 7 I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. TX0-7 TX Outputs 0 to 7 O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. (Three-state Outputs) ODE Output Drive Enable I This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. I f this is HIGH, each channel may still be put into high-impedance by software control. CCO Control Channel Output O This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controll ed by the contents of the CCO bit in the Connection Memory HIGH locations. NOTE: 1. DNC - Do Not Connect.

High control the output state on a per-channel basis. stream must first be stored in Data Memory before it is sent out. the allowable input/output stream combinations for the minimum 2 channel delay. define internal memory subsections corresponding to input or output streams. is to be switched to an output. Figure 2. Processor ModeFigure 1. Connection Mode

If the ODE input pin is LOW, then all the serial outputs are high-impedance. or disables (if LOW) the output stream and channel. Table 2. Address Mapping The Control Register is only accessed when A5=0. All other address bits have no effect when A5=0. accessed is determined by the state of CRb0 -CRb4. Table 1. Input Stream to Output Stream Combinations that can Provide the Figure 3. Address Mapping

  1. Writing to the Control Register is the only fast transaction.
  2. Memory and stream are specified by the contents of the Control Register.

impedance state control to the Connection Memory High bits outputs.

Table 4. Connection Memory High Register Table 5. Connection Memory Low Register Table 3. Control Register Configuration operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. pin is LOW. When 0, the Connection Memory bits for each channel determine what is output. 4-3 MS1-MS0 0-0 - Not to be used. (Stream Address Bits) subsection of memory made accessible for subsequent operations. Data Memory and determine the source of the connection to the location's channel and stream. 1 CCO (CCO Bit) This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first. switching matrices to be constructed. A 1 enables the driver and a 0 disables it. 7-5(1) Stream Address Bits The number expressed in binary notation on these 3 bits are the number of the stream for the source of the c onnection. is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.

  1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits a re output on the channel and stream associated with

this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.

levels or high impedance states. output levels or high impedance states. Figure 4. Output Load

  1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject
  2. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
  3. Exceeding these values may cause permanent damage. Functional operation

under these conditions is not implied.

Figure 10. Processor Bus

  1. Timing is over recommended temperature and power supply voltages.
  2. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
  3. High Impedance is measured by pulling to the appropriate rail with R

L, with timing corrected to cancel time taken to discharge C L.

  1. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com BLANK 5610 drw25 Commercial (-40°C to +85°C) XXXXXX Device Type X Package Process/ Temperature Range XX 256 x 256 ⎯ Time Slot Interchange Digital Switch728980 X X Tube Tape and Reel Blank J G Plastic Leaded Chip Carrier (PLCC, J44) Green

ORDERING INFORMATION

DATASHEET DOCUMENT HISTORY 05/23/2000 pgs. 1, 2, and 10. 08/18/2000 pgs. 1, 2, and 10. 01/24/2001 pgs. 1 and 6. 03/13/2017 pgs. 1, 2, and 10.

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