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IDT72801_13 IDT | Alldatasheet

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IDT, IDT logo and the SyncFIFO logo are registered trademarks of Integrated Device Technology, Inc. MARCH 2013 DUAL CMOS SyncFIFO™ DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE ©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3034/6 FEATURES:

• •••• The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
• •••• The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
• •••• The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
• •••• The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
• •••• The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
• •••• The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
• •••• Offers optimal combination of large capacity, high speed, design flexibility and small footprint
• •••• Ideal for prioritization, bidirectional, and width expansion

applications

• •••• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/
• •••• Separate control lines and data lines for each FIFO
• •••• Separate Empty, Full, Programmable Almost-Empty and Almost- Full flags for each FIFO
• •••• Enable puts output data lines in high-impedance state
• •••• Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin Quad Flatpack (STQFP)
• Industrial temperature range (–40 °°°°°C to +85 °°°°°C) is available
• •••• Green parts available, see ordering information DESCRIPTION: The IDT72801/72811/72821/72831/72841/72851 are dual synchronous (clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/ 72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs (designated FIFO A and FIFO B) contained in the IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB) when the appropriate write enable pins are asserted. The output port of each FIFO bank is controlled by its associated clock pin (RCLKA, RCLKB) and two Read Enable pins ( RENA1, RENA2, RENB1, RENB2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO for three-state output control. Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA, FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full (PAFA, PAFB), are provided for each FIFO bank to improve memory utilization. If not programmed, the programmable flags default to empty+7 for PAEA and PAEB, and full-7 for PAFA and PAFB. The IDT72801/72811/72821/72831/72841/72851 architecture lends itself to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion These FIFOs is fabricated using high-performance submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM WCLKA WENA1 WENA2 DA0 - DA8 LDA OFFSET REGISTERINPUT REGISTER RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER OEARSA QA0 - QA8 RCLKA RENA1 RENA2 READ CONTROL LOGIC READ POINTER FLAG LOGIC EFA PAEA PAFA FFA 3034 drw 01 WCLKB WENB1 WENB2 DB0 - DB8 LDB OFFSET REGISTERINPUT REGISTER WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER OEBRSB QB0 - QB8 RCLKB RENB1 RENB2 READ CONTROL LOGIC READ POINTER FLAG LOGIC EFB PAEB PAFB FFB RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO TM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 VCC WENA2/LDA WCLKA WENA1 RSA DA8 DA7 DA6 QB0 FFB EFB OEB RENB2 RCLKB RENB1 GND V CC PAEB PAFB DB0 DB1 DB2 DB3 DB4 QA FFA EFA OEA RENA2 RCLKA RENA1 GND QB8 QB7 QB6 QB5 QB4 QB3 QB2 QB1 DA5 DA4 DA3 DA2 DA1 DA0 PAFA PAEA WENB2/LDB WCLKB WENB1 RSB DB8 DB7 DB6 DB5 3034 drw 02 PIN CONFIGURATION TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO TM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 Symbol Name I/O Description DA0-DA8 A Data Inputs I 9-bit data inputs to RAM array A. DB0-DB8 B Data Inputs I 9-bit data inputs to RAM array B. RSA, RSB Reset I When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write. WCLKA Write Clock I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write WCLKB enable(s) are asserted. WENA1 Write Enable 1 I If FIFO A (B) is configured to have programmable flags, WENA1 ( WENB1) is the only Write WENB1 Enable pin that can be used. When WENA1 ( WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is LOW. WENA2/LDA Write Enable 2/ I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) WENB2/LDB Load is HIGH at reset, this pin operates as a second write enable. If WENA2/ LDA (WENB2/LDB) is LOW at reset this pin operates as a control to load and read the programmable flag offsets for its respective array. If the FIFO is configured to have two write enables, WENA1 ( WENB1 ) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA (LDB) is held LOW to write or read the programmable flag offsets. QA0-QA8 A Data Outputs O 9-bit data outputs from RAM array A. QB0-QB8 B Data Outputs O 9-bit data outputs from RAM array B. RCLKA Read Clock I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1 RCLKB ( RENB1) and RENA2 (RENB2) are asserted. RENA1 Read Enable 1 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every RENB1 LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW. RENA2 Read Enable 2 I When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every RENB2 LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW. OEA Output Enable I When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state. EFA Empty Flag O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. EFB When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB). PAEA Programmable O When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the PAEB Almost-Empty appropriate offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to Flag RCLKA (RCLKB). PAFA Programmable O When PAFA (PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate PAFB Almost-Full Flag offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB). FFA Full Flag O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. FFB When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB). VCC Power +5V power supply pin. GND Ground 0V ground pin. PIN DESCRIPTIONS The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following description defines the input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses.

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO TM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage (Com'l & Ind'l) 4.5 5.0 5.5 V GND Supply Voltage (Com'l & Ind'l) 0 0 0 V VIH Input High Voltage (Com'l & Ind'l) 2.0 — — V VIL Input Low Voltage (Com'l & Ind'l) — — 0.8 V TA Operating Temperature 0 — 70 °C Commercial TA Operating Temperature –40 — 85 °C Industrial Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with –0.5 to +7.0 V Respect to GND TSTG StorageTemperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C) IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851 Commercial and Industrial (1) Commercial and Industrial(1) tCLK = 10, 15, 25 ns t CLK = 10, 15, 25 ns ILI(2) Input Leakage Current (Any Input) –1 — 1 –1 — 1 μA ILO(3) Output Leakage Current –10 — 10 –10 — 10 μA VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V ICC1(4,5,6,8) Active Power Supply Current (both FIFOs) — — 60 — — 80 mA ICC2(4,7,8) Standby Current — — 10 — — 10 mA Symbol Parameter Conditions Max. Unit CIN(2) Input Capacitance V IN = 0V 10 pF COUT(1,2) Output Capacitance V OUT = 0V 10 pF RECOMMENDED OPERATING CONDITIONS NOTES: 1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device. 2. Measurements with 0.4 ≤ VIN ≤ V CC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs open (I OUT = 0). 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. Typical I CC1 = 2*[1.7 + 0.7*f S + 0.02*C L*fS] (in mA). These equations are valid under the following conditions: V CC = 5V, T A = 25 °°°°°C, f S = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f S/2, C L = capacitive load (in pF). 7. All Inputs = V CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. 8. I CC1 and I CC2 parameters are improved as compared to previous data sheets. CAPACITANCE (TA = +25°C, f = 1.0MHz) NOTE: 1. With output deselected ( OEA, OEB ≥ ≥ ≥ ≥ ≥ V IH). 2. Characterized values, not currently tested.

Figure 1. Output Load *Includes jig and scope capacitances.

1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.AC TEST CONDITIONS

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO TM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 When either of the two Read Enable RENA1, RENA2 (RENB1, RENB2) associated with FIFO A (B) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from FIFO A (B), the Empty Flag EFA (EFB) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, EFA (EFB) will go HIGH after tREF and a valid read can begin. The Read Enables RENA1, RENA2 (RENB1, RENB2) are ignored when FIFO A (B) is empty. Output Enable (OEA, OEB) — When Output Enable OEA (OEB) is enabled (LOW), the parallel output buffers of FIFO A (B) receive data from their respective output register. When Output Enable OEA (OEB) is disabled (HIGH), the QA (QB) output data bus is in a high-impedance state. Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual- purpose pin. FIFO A (B) is configured at Reset to have programmable flags or to have two write enables, which allows depth expansion. If WENA2/LDA (WENB2/LDB) is set HIGH at Reset RSA = LOW (RSB = LOW), this pin operates as a second write enable pin. If FIFO A (B) is configured to have two write enables, when Write Enable

1 WENA1 (WENB1) is LOW and WENA2/LDA (WENB2/LDB) is HIGH, data can be

loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write Clock WCLKA (WCLKB). Data is stored in the array sequentially and independently of any ongoing read operation. In this configuration, when WENA1 (WENB1) is HIGH and/or WENA2/LDA (WENB2/LDB) is LOW, the input register of Array A holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag FFA (FFB) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FFA (FFB) will go HIGH after tWFF, allowing a valid write to begin. WENA1, (WENB1) and WENA2/LDA (WENB2/LDB) are ignored when the FIFO is full. FIFO A (B) is configured to have programmable flags when the WENA2/ LDA (WENB2/LDB) is set LOW at Reset RSA = LOW (RSB = LOW). Each FIFO contains four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values. If FIFO A (B) is configured to have programmable flags, when the WENA1 (WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB) inputs are written into the Empty (Least Significant Bit) Offset register on the first LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register on the third transition, and into the Full (Most Significant Bit) Offset register on the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the Empty (Least Significant Bit) Offset register. However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing LDA (LDB) HIGH, FIFO A (B) is returned to normal read/write operation. When LDA (LDB) is set LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the QA (QB) outputs when WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1, RENA2 (RENB1, RENB2) are set LOW. Data can be read on the LOW-to-HIGH transition of the Read Clock RCLKA (RCLKB). SIGNAL DESCRIPTIONS FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses. INPUTS: Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine data inputs for memory array A. DB0 - DB8 are the nine data inputs for memory array B. CONTROLS: Reset (RSA, RSB) — Reset of FIFO A (B) is accomplished whenever RSA (RSB) input is taken to a LOW state. During Reset, the internal read and write pointers associated with the FIFO are set to the first location. A Reset is required after power-up before a write operation can take place. The Full Flag FFA (FFB) and Programmable Almost-Full flag PAFA (PAFB) will be reset to HIGH after tRSF. The Empty Flag EFA (EFB) and Programmable Almost-Empty flag PAEA (PAEB) will be reset to LOW after tRSF. During Reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup and hold times must be met with respect to the LOW-to-HIGH transition of WCLKA (WCLKB). The Full Flag FFA (FFB) and Programmable Almost-Full flag PAFA (PAFB) are synchronized with respect to the LOW-to-HIGH transition of the Write Clock WCLKA (WCLKB). The Write and Read Clocks can be asynchronous or coincident. Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for programmable flags, WENA1 (WENB1) is the only enable control pin. In this configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input register of RAM Array A (B) on the LOW-to-HIGH transition of every Write Clock WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently of any ongoing read operation. In this configuration, when WENA1 (WENB1) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. If the FIFO is configured to have two write enables, which allows for depth expansion. See Write Enable 2 paragraph below for operation in this configuration. To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the FFA (FFB) will go HIGH after tWFF, allowing a valid write to begin. WENA1 (WENB1) is ignored when FIFO A (B) is full. Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag EFA (EFB) and Programmable Almost-Empty Flag PAEA (PAEB) are synchronized with respect to the LOW-to-HIGH transition of RCLKA (RCLKB). The Write and Read Clocks can be asynchronous or coincident. Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read Enables RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array A (B) to the output register on the LOW-to-HIGH transition of the Read Clock RCLKA (RCLKB).

00 Empty Offset (LSB)

Figure 3. Offset Register Formats and Default Values for the A and B FIFOs Figure 2. Writing to Offset Registers for FIFOs A and B (B); or 8,192 writes to the IDT72851's FIFO A (B). the Read Clock RCLKA (RCLKB).

1. For the purposes of this table, WENA2 and WENB2 = V IH.
2. The same selection sequence applies to reading from the registers. RENA1 and

HIGH transition of RCLKA (RCLKB).

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO TM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 NUMBER OF WORDS IN ARRAY A FFAFFAFFAFFAFFA PAFAPAFAPAFAPAFAPAFA PAEAPAEAPAEAPAEAPAEA EFAEFAEFAEFAEFA NUMBER OF WORDS IN ARRAY B FFBFFBFFBFFBFFB PAFBPAFBPAFBPAFBPAFB PAEBPAEBPAEBPAEBPAEB EFBEFBEFBEFBEFB 72801 72811 72821 00 0 H H L L 1 to n(1) 1 to n(1) 1 to n(1) HH L H 256 512 1,024 L L H H NUMBER OF WORDS IN ARRAY A FFAFFAFFAFFAFFA PAFAPAFAPAFAPAFAPAFA PAEAPAEAPAEAPAEAPAEA EFAEFAEFAEFAEFA NUMBER OF WORDS IN ARRAY B FFBFFBFFBFFBFFB PAFBPAFBPAFBPAFBPAFB PAEBPAEBPAEBPAEBPAEB EFBEFBEFBEFBEFB 72831 72841 72851 00 0 H H L L 1 to n(1) 1 to n(1) 1 to n(1) HH L H 2,048 4,096 8,192 L L H H Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will go LOW when the amount of data in Array A (B) reaches the almost-full condition. If no reads are performed after Reset, PAFA (PAFB) will go LOW after (256-m) writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or (8,192-m) writes to the IDT72851's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset registers. If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words. PAFA (PAFB) is synchronized with respect to the LOW-to-HIGH transition of WCLKA (WCLKB). Programmable Almost–Empty Flag (PAEA, PAEB) — PAEA (PAEB) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the Empty Offset registers. If no reads are performed after Reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B). If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7 words. PAEA (PAEB) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock RCLKA (RCLKB). Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA 0 - QA8 are the nine data outputs for memory array A, QB0 - QB8 are the nine data outputs for memory array B. TABLE 1: STATUS FLAGS FOR A AND B FIFOS NOTES: 1. n = Empty Offset (n = 7 default value) 2. m = Full Offset (m = 7 default value)

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6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com DEPTH EXPANSION — IDT72801/72811/72821/72831/72841/72851 can be adapted to applications that require greater than 256/512/1,024/ 2,048/4,096/8,192 words. The existence of double enable pins on the read and write ports allow depth expansion. The Write Enable 2/Load (WENA2, WENB2) pins are used as a second write enables in a depth expansion configuration, thus the Programmable flags are set to the default values. Depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. A typical application would have the expansion logic alternate data access from one device to the next in a sequential manner. These FIFOs operate in the Depth Expansion configuration when the following conditions are met: 1. WENA2/ LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables. 2. External logic is used to control the flow of data. Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN- CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details of this configuration. NOTES: 1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device. 2. Green parts are available. For specific speeds and packages contact your sales office.

ORDERING INFORMATION

Power Speed Package Process/ Temperature Range Clock Cycle Time (tCLK), Speed in Nanoseconds Commercial (0°C to +70°C) X 256 x 9 Dual SyncFIFO Thin Quad Flatpack (TQFP, PN64-1) 72801 Commercial Only PF Low Power XXX L I(1) Industrial (-40°C to +85°C) TF Slim Thin Quad Flatpack(STQFP, PP64-1) Commercial and Industrial Commercial and Industrial 72811 72821 72831 72841 72851 512 x 9 Dual SyncFIFO 1,024 x 9 Dual SyncFIFO 2,048 x 9 Dual SyncFIFO 4,096 x 9 Dual SyncFIFO 8,192 x 9 Dual SyncFIFO X G(2) Green BLANK Tube or Tray Tape and Reel X DATASHEET DOCUMENT HISTORY 04/24/2001 pgs. 4, 5 and 16. 02/10/2006 pgs. 1 and 16. 01/13/2009 pg. 16. 03/20/2013 pg. 1, 3, 7 and 16.