7282L12PAGI

IDT7280_17 IDT | Alldatasheet

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CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 IDT7280 IDT7281 IDT7282 IDT7283 IDT7284 IDT7285 NOVEMBER 2017 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3208/10 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES:

• •• •• The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs
• •• •• The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs
• •• •• The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs
• •• •• The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs
• •• •• The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs
• •• •• The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs
• •• •• Low power consumption — Active: 685 mW (max.) — Power-down: 83 mW (max.)
• •• •• Ultra high speed—12 ns access time
• •• •• Asynchronous and simultaneous read and write
• •• •• Offers optimal combination of data capacity, small foot print and functional flexibility
• •• •• Ideal for bi-directional, width expansion, depth expansion, bus-matching, and data sorting applications
• •• •• Status Flags: Empty, Half-Full, Full
• •• •• Auto-retransmit capability
• •• •• High-performance CMOS technology
• •• •• Space-saving TSSOP Industrial temperature range (–40 ° °° °°C to +85 ° °° °°C) is available DESCRIPTION: The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that load and empty data on a first-in/first-out basis. These devices are functional and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. FUNCTIONAL BLOCK DIAGRAM WA WRITE CONTROL READ CONTROLRA FLAG LOGIC EXPANSION LOGIC XIA WRITE POINTER READ POINTER DATA INPUTS RESET LOGIC THREE- STATE BUFFERS DATA OUTPUTS RSA FLA/RTAXOA/HFA FFA EFA WB WRITE CONTROL READ CONTROL RB FLAG LOGIC EXPANSION LOGIC XIB WRITE POINTER RAM ARRAY B 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 READ POINTER DATA INPUTS RESET LOGIC THREE- STATE BUFFERS DATA OUTPUTS RSB FLB/RTB 3208 drw 01 XOB/HFB FFB EFB (DA0-DA8) (DB0-DB8) (QB0-QB8)(QA0-QA8) RAM ARRAY A 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

conditions for extended periods may affect reliability.

1. Characterized values, not currently tested.
2. For RT/RS/XI input, V IH = 2.6V (commercial).
3. 1.5V undershoots are allowed for 10ns once per cycle.
4. Measurements with 0.4 ≤ V IN ≤ V CC.
5. Tested with outputs open (I OUT = 0).

CL = capacitive load (in pF).

1. All Inputs = V CC - 0.2V or GND + 0.2V.

Figure 1. Output Load

• Includes scope and jig capacitances.

COMMERCIAL TEMPERATURE RANGE IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 JUNE 29, 2012 Commercial Commercial & Industrial(2) IDT7280L12 IDT7280L15 IDT7281L12 IDT7281L15 IDT7282L12 IDT7282L15 IDT7283L12 IDT7283L15 IDT7284L12 IDT7284L15 IDT7285L12 IDT7285L15 Symbol Parameter Min. Max. Min. Max. Unit tS Shift Frequency — 50 — 40 MHz tRC Read Cycle Time 20 — 25 — ns tA Access Time — 12 — 15 ns tRR Read Recovery Time 8 — 10 — ns tRPW Read Pulse Width(3) 12 — 15 — ns tRLZ Read Pulse Low to Data Bus at Low Z(4) 3— 3 — n s tWLZ Write Pulse High to Data Bus at Low Z(4,5) 5— 5 — n s tDV Data Valid from Read Pulse High 5 — 5 — ns tRHZ Read Pulse High to Data Bus at High Z(4) —1 2 — 1 5 n s tWC Write Cycle Time 20 — 25 — ns tWPW Write Pulse Width(3) 12 — 15 — ns tWR Write Recovery Time 8 — 10 — ns tDS Data Set-up Time 9 — 11 — ns tDH Data Hold Time 0 — 0 — ns tRSC Reset Cycle Time 20 — 25 — ns tRS Reset Pulse Width(3) 12 — 15 — ns tRSS Reset Set-up Time(4) 12 — 15 — ns tRSR Reset Recovery Time 8 — 10 — ns tRTC Retransmit Cycle Time 20 — 25 — ns tRT Retransmit Pulse Width(3) 12 — 15 — ns tRTS Retransmit Set-up Time(4) 12 — 15 — ns tRTR Retransmit Recovery Time 8 — 10 — ns tEFL Reset to Empty Flag Low — 12 — 25 ns tHFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 ns tRTF Retransmit Low to Flags Valid — 20 — 25 ns tREF Read Low to Empty Flag Low — 12 — 15 ns tRFF Read High to Full Flag High — 14 — 15 ns tRPE Read Pulse Width after EF High 12 — 15 — ns tWEF Write High to Empty Flag High — 12 — 15 ns tWFF Write Low to Full Flag Low — 14 — 15 ns tWHF Write Low to Half-Full Flag Low — 17 — 25 ns tRHF Read High to Half-Full Flag High — 17 — 25 ns tWPF Write Pulse Width after FF High 12 — 15 — ns tXOL Read/Write to XO Low — 12 — 15 ns tXOH Read/Write to XO High — 12 — 15 ns tXI XI Pulse Width(3) 12 — 15 — ns tXIR XI Recovery Time 8 — 10 — ns tXIS XI Set-up Time 8 — 10 — ns NOTES: 1. Timings referenced as in AC Test Conditions. Industrial temperature range product for the 15ns speed grade is available as a standard device. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode. AC ELECTRICAL CHARACTERISTICS (1) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

COMMERCIAL TEMPERATURE RANGE IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 JUNE 29, 2012 SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0 – D 8) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, (i.e., tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset ( RS). WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read E nable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable ( R) goes HIGH, the Data Outputs (Q0 – Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after t WEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). These devices can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 256/512/1,024/2,048/4,096/8,192 writes are per- formed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 256 writes for IDT7280, 512 writes for the IDT7281, 1,024 writes for the IDT7282, 2,048 writes for the IDT7283, 4,096 writes for the IDT7284 and 8,192 writes for the IDT7285. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expan- sion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Q0 – Q 8) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a HIGH state.

Figure 14. Block Diagram of 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 FIFO Memory (Depth Expansion)

1. Pointer will increment if flag is High.
2. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

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NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Green parts are available. For specific speeds and packages contact your local sales office. LEAD FINISH (SnPb) parts are in EOL proc ess. Product Discontinuation Notice - PDN# SP-17-02 XXXX Device Type XXX Speed X Power X Package X Process/ Temperature Range Blank I(1) 7280 7281 7282 7283 7284 7285 Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 256 x 9 ⎯ CMOS Dual Asynchronous FIFO 512 x 9 ⎯ CMOS Dual Asynchronous FIFO 1,024 x 9 ⎯ CMOS Dual Asynchronous FIFO 2,048 x 9 ⎯ CMOS Dual Asynchronous FIFO 4,096 x 9 ⎯ CMOS Dual Asynchronous FIFO 8,192 x 9 ⎯ CMOS Dual Asynchronous FIFO L Low Power PA Thin Shrink SOIC (TSSOP, SO56-2) Access Time (tA) Speed in Nanoseconds 3208 drw 21 Commercial Only Commercial and Industrial G (2) Green X X Blank Tube or Tray Tape and Reel DATASHEET DOCUMENT HISTORY 07/13/2001 pgs. 2, 3 and 12. 01/13/2009 pg. 12. 06/29/2012 pgs. 1 and 12. 11/27/2017 Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018.