72605L25J

IDT72605_13 IDT | Alldatasheet

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©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2704/10 FEBRUARY 2013 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM FEATURES:

• •••• Two independent FIFO memories for fully bidirectional data transfers
• •••• 256 x 18 x 2 organization (IDT72605)
• •••• 512 x 18 x 2 organization (IDT72615)
• •••• Synchronous interface for fast (20ns) read and write cycle times
• •••• Each data port has an independent clock and read/write control
• •••• Output enable is provided on each port as a three-state control of the data bus
• •••• Built-in bypass path for direct data transfer between two ports
• •••• Two fixed flags, Empty and Full, for both the A-to-B and the B- to-A FIFO
• •••• Programmable flag offset can be set to any depth in the FIFO
• •••• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin Quad Flatpack) and 68-pin PLCC
• •••• Industrial temperature range (–40 °°°°°C to +85 °°°°°C)
• •••• Green parts available, see ordering information DESCRIPTION: The IDT72605 and IDT72615 are very high-speed, low-power bidirec- tional First-In, First-Out (FIFO) memories, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous. Each Port has its own independent clock. Data transfers to the I/O registers are gated by the enable signals. The transfer direction for each port is controlled independently by a read/write signal. Individual output enable signals control whether the SyncBiFIFO is driving the data lines of a port or whether those data lines are in a high-impedance state. Bypass control allows data to be directly transferred from input to output register in either direction. The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full, and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full and Almost-Empty flags can be programmed to any location. The SyncBiFIFO is fabricated using high-speed, submicron CMOS tech- nology. CLKA FLAG LOGIC MEMORY ARRAY 512 x 18 256 x 18 INPUT REGISTER MUX OUTPUT REGISTER HIGH Z CONTROL OUTPUT REGISTER INPUT REGISTERCLKB MUX MEMORY ARRAY 512 x 18 256 x 18 HIGH Z CONTROL FLAG LOGIC RESET LOGIC POWER SUPPLY R/WA CSA EFAB PAEAB PAFAB FFAB OEB R/WB ENB ENA OEA RS EFBA PAEBA PAFBA FFBA VCC GND BYPB μP INTERFACE DB0-DB17 DA0-DA17 2704 drw 01

INDUSTRIAL TEMPERATURE RANGE IDT72605/72615 CMOS SYNCBiFIFO™ 256 x 18x 2 and 512 x 18 x 2 PIN CONFIGURATIONS TQFP (PN64-1, order code: PF) TOP VIEW 6162636465666768 23456789 35 43 424140393837363433323130292827 DA16 CA17 CLKA R/WA ENA CSA VCC EFAB FFAB PAEAB PAFAB OEA DB17 DB16 DA2 DA1 DA0 EFBA FFBA PAEBA PAFBA GND BYPB OEB ENB R/WB CLKB RS DB0 DB1 DB2 DB15 GND DB14 DB13 DB12 DB11 DB10 VCC GND DB9 DB8 DB7 DB6 DB5 GND DB4 DB3 DA15 GND D A14 DA13 DA12 DA11 DA10 VCC GND D DA8 DA7 DA6 DA5 GND D DA3 2704 drw 02 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 GND VCC DA10 DA11 DA12 DA13 DA14 DA15 DB3 DB4 GND DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 GND D B15 DB16 DA16 DA17 CLKA R/WA ENA CSA VCC EFAB FFAB PAEAB PAFAB OEA DB17 DA1 DA0 EFBA FFBA PAEBA PAFBA GND BYBB OEB ENB R/WB CLKB RS DB0 DB1 DB2 2704 drw 03 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN 1 PLCC (J68-1, order code: J) TOP VIEW

IDT72605/72615 CMOS SYNCBiFIFO™ 256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol Name I/O Description DA0-DA17 Data A I/O Data inputs & outputs for the 18-bit Port A bus. CSA Chip Select A I Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH. R/WA Read/Write A I This pin controls the read or write direction of Port A. If R/ WA is LOW, Data A input data is written into Port A. If R/ WA is HIGH, Data A output data is read from Port A. In bypass mode, when R/WA is LOW, message is written into A→B output register. If R/WA is HIGH, message is read from B →A output register. CLKA Clock A I CLK A is typically a free running clock. Data is read or written into Port A on the rising edge of CLKA. ENA Enable A I When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data transfers occur. OEA Output Enable A I When R/ WA is HIGH, Port A is an output bus and OEA controls the high-impedance state of DA0-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is LOW while CSA is LOW and R/WA is HIGH, Port A is in an active (low-impedance) state. A0, A1, A2 Addresses I When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources. DB0-DB17 Data B I/O Data inputs & outputs for the 18-bit Port B bus. R/WB Read/Write B I This pin controls the read or write direction of Port B. If R/ WB is LOW, Data B input data is written into Port B. If R/ WB is HIGH, Data B output data is read from Port B. In bypass mode, when R/WB is LOW, message is written into B→A output register. If R/WB is HIGH, message is read from A →B output register. CLKB Clock B I Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLK B. ENB Enable B I When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data transfers occur. OEB Output Enable B I When R/ WB is HIGH, Port B is an output bus and OEB controls the high-impedance state of DB0-DB17. If OEB is HIGH, Port B is in a high-impedance state. If OEB is LOW while R/WB is HIGH, Port B is in an active (low-impedance) state. EFAB A→B Empty O When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited. When EFAB is HIGH, the FIFO is Flag not empty. EFAB is synchronized to CLKB. In the bypass mode, EFAB HIGH indicates that data DA0-DA17 is available for passing through. After the data DB0-DB17 has been read, EFAB goes LOW. PAEAB A→B O When PAEAB is LOW, the A→B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset Programmable programmed into PAEAB Register. When PAEAB is HIGH, the A→B FIFO contains more than offset in PAEAB Register. The Almost-Empty default offset value for PAEAB Register is 8. PAEAB is synchronized to CLKB. Flag PAFAB A→B O When PAFAB is LOW, the A→B FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset Programmable programmed into PAFAB Register. When PAFAB is HIGH, the A→B FIFO contains less than or equal to the depth minus the Almost-Full offset in PAFAB Register. The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA. Flag FFAB A→B Full Flag O When FFAB is LOW, the A→B FIFO is full and further data writes into Port A are inhibited. When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to CLKA. In bypass mode, FFAB tells Port A that a message is waiting in Port B’s output register. If FFAB is LOW, a bypass message is in the register. If FFAB is HIGH, Port B has read the message and another message can be written into Port A. EFBA B→A Empty O When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited. When EFBA is HIGH, the FIFO Flag is not empty. EFBA is synchronized to CLKA. In the bypass mode, EFBA HIGH indicates that data DB0-DB17 is available for passing through. After the data DA0-DA17 has been read, EFBA goes LOW on the following cycle. PAEBA B→A O When PAEBA is LOW, the B→A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset Programmable programmed into PAEBA Register. When PAEBA is HIGH, the B→A FIFO contains more than offset in PAEBA Register. The Almost-Empty default offset value for PAEBA Register is 8. PAEBA is synchronized to CLKA. Flag PAFBA B→A O When PAFBA is LOW, the B→A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset Programmable programmed into PAFBA Register. When PAFBA is HIGH, the B→A FIFO contains less than or equal to the depth minus the Almost-Full offset in PAFBA Register. The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB. Flag FFBA B→A Full Flag O When FFBA is LOW, the B →A FIFO is full and further data writes into Port B are inhibited. When FFBA is HIGH, the FIFO is not full. FFBA is synchronized to CLKB. In bypass mode, FFBA tells Port B that a message is waiting in Port A’s output register. If FFBA is LOW, a bypass message is in the register. If FFBA is HIGH, Port A has read the message and another message can be written into Port B. BYPB Port B Bypass O This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYPB is LOW, Port A has placed the FIFO into Flag bypass mode. If BYPB is HIGH, the synchronous BiFIFO passes data into memory. BYPB is synchronized to CLK B. RS Reset I A LOW on this pin will perform a reset of all synchronous BiFIFO functions. VCC Power There are three +5V power pins for the PLCC and two for the TQFP. GND Ground There are seven ground pins for the PLCC and four for the TQFP.

INDUSTRIAL TEMPERATURE RANGE IDT72605/72615 CMOS SYNCBiFIFO™ 256 x 18x 2 and 512 x 18 x 2 ABSOLUTE MAXIMUM RATINGS(1) DC ELECTRICAL CHARACTERISTICS RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.0 — — V VIL(1) Input Low Voltage — — 0.8 V TA Operating Temperature -40 — 85 °C NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. Symbol Rating Industrial Unit VTERM Terminal Voltage with –0.5 to +7.0 V Respect to Ground TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C) IDT72615L IDT72605L Industrial t CLK = 20, 25, 35, 50ns Symbol Parameter Min. Typ. Max. Unit ILI(1) Input Leakage Current (Any Input) –1 — 1 μA ILO(2) Output Leakage Current –10 — 10 μA VOH Output Logic "1" Voltage IOUT = –2mA 2.4 — — V VOL Output Logic "0" Voltage IOUT = 8mA — — 0.4 V ICC(3) Active Power Supply Current — — 230 mA NOTES: 1. Measurements with 0.4V ≤ V IN ≤ V CC. 2. OEA, OEB ≥ VIH; 0.4 ≤ VOUT ≤ VCC. 3. Tested with outputs open (I OUT = 0). Testing frequency f=20MHz. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol Parameter Conditions Max. Unit CIN(2) Input Capacitance V IN = 0V 10 pF COUT (1,2) Output Capacitance V OUT = 0V 10 pF NOTES: 1. With output deselected. 2. Characterized values, not currently tested.

1. Control signals refer to CS
2. Minimum values are guaranteed by design.

Figure 2. Output Load

• Includes jig and scope capacitances.

applications. Data can be stored or retrieved from two sources simultaneously. or receive messages directly to the Port B device using the 18-bit bypass path. configured for multiprocessor communication. Port B control pins are inputs driven by the second processor. Programmable Almost- Full flags (PAFAB, PAFBA) will be set to HIGH after tRSF. A→B and B→A FIFO offset default to 8. to select one of six internal resources (Table 1). FIFO through the bypass path (A0=1). Almost-Full flag Offset (A1=1, A0=1). the FIFO memory is undisturbed. Figure 1. 36- to 36-bit Processor Interface Configuration

1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A consists of R/ W

A, ENA, OEA, CSA, A 2, A 1, A 0. Control B consists of R/ WB, ENB, OEB.

IDT72605/72615 CMOS SYNCBiFIFO™ 256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE Data A CSA R/WA ENA OEA I/O Port A Operation 0 0 0 0 I Data A is written on CLK A ↑. This write cycle immediately following low-impedance cycle is prohibited. Note that even though OEA = 0, a LOW logic level on R/WA, once qualified by a rising edge on CLKA, will put Data A into a high-impedance state. 0 0 0 1 I Data A is written on CLKA ↑ 0 0 1 X I Data A is ignored 0 1 0 0 O Data is read (1) from RAM array to output register on CLKA ↑, Data A is low-impedance 0 1 0 1 O Data is read (1) from RAM array to output register on CLKA ↑, Data A is high-impedance 0 1 1 0 O Output register does not change (2), Data A is low-impedance 0 1 1 1 O Output register does not change (2), Data A is high-impedance 1 0 X X I Data A is ignored (3) 1 1 X X O Data A is high-impedance (3) NOTES: 1. When A 2A1A0 = 000, the next B →A FIFO value is read out of the output register and the read pointer advances. If A 2A1A0 = 001, the bypass path is selected and bypass data from the Port B input register is read from the Port A output register. If A 2A1A00 = 1XX, a flag offset register is selected and its offset is read out through Port A output register. 2. Regardless of the condition of A 2A1A0, the data in the Port A output register does not change and the B →A read pointer does not advance. 3. If CS A# is HIGH, then BYP B is HIGH. No bypass occur under this condition. TABLE 1 ⎯ PORT A OPERATION CONTROL SIGNALS CSA A2 A1 A0 Read Write

0000 B →A FIFO A →B FIFO

0100 A →B FIFO Almost-Empty

0101 A →B FIFO Almost-Full

0110 B →A FIFO Almost-Empty

0111 B →A FIFO Almost-Full

1 X X X Port A Disabled

TABLE 2 ⎯ ACCESSING PORT A RE- SOURCES USING CSA, A2, A1, AND A0 of each port operate independently, Port A can be reading bypass data at the same time Port B is reading bypass data. When R/WA and ENA is LOW, data on pins DA0-DA17 is written into Port A input register. Following the rising edge of CLKA for this write, the A→B Full Flag (FFAB) goes LOW. Subsequent writes into Port A are blocked by internal logic until FFAB goes HIGH again. On the next CLKB rising edge, the A→B Empty Flag (EFAB) goes HIGH indicating to Port B that data is available. Once R/WB is HIGH and ENB is LOW, data is read into the Port B output register. OEB still controls whether Port B is in a high-impedance state. When OEB is LOW, the output register data appears at DB0-DB17. EFAB goes LOW following the CLKB rising edge for this read. FFAB goes HIGH on the next CLKA rising edge, letting Port A know that another word can be written through the bypass path. Bypass data transfers from Port B to Port A work in a similar manner with EFBA and FFBA indicating the Port A output register state. When the Port A address changes from bypass mode (A2A1A0=001) to FIFO mode (A2A1A0=000) on the rising edge of CLKA, the data held in the Port B output register may be overwritten. Unless Port A monitors the BYPB pin and waits for Port B to clock out the last bypass word, data from the A→B FIFO will overwrite data in the Port B output register. BYPB will go HIGH on the rising edge of CLKB signifying that Port B has finished its last bypass operation. Port B must read any bypass data in the output register on this last CLKB clock or it is lost and the SyncBiFIFO returns to FIFO operations. It is especially important to monitor BYP B when CLKB is much slower than CLKA to avoid this condition. BYPB will also go HIGH after CSA is brought HIGH; in this manner the Port B bypass data may also be lost. Since the Port A processor controls CSA and the bypass mode, this scenario can be handled for B→A bypass data. The Port A processor must be set up to read the last bypass word before leaving bypass mode. PORT A CONTROL SIGNALS The Port A control signals pins dictate the various operations shown in Table 2. Port A is accessed when CSA is LOW, and is inactive if CSA is HIGH. R/ WA and ENA lines determine when Data A can be written or read. If R/WA and ENA are LOW, data is written into input register on the LOW-to-HIGH transition of CLKA. If R/WA is HIGH and OEA is LOW, data comes out of bus and is read from output register into three-state buffer. Refer to pin descriptions for more information. PROGRAMMABLE FLAGS The IDT SyncBiFIFO has eight flags: four flags for A→B FIFO (EF AB, PAEAB, PAFAB, FFAB), and four flags for B→A FIFO (EFBA, PAEBA, PAFBA, FFBA). The Empty and Full flags are fixed, while the Almost-Empty and Almost- Full offsets can be set to any depth through the Flag Offset Registers (see Table 3). The flags are asserted at the depths shown in the Flag Truth Table (Table 4). After reset, the programmable flag offsets are set to 8. This means the Almost- Empty flags are asserted at Empty +8 words deep, and the Almost-Full flags are asserted at Full -8 words deep. The PAE AB is synchronized to CLKB, while PAEAB is synchronized to CLKA; and PAEBA is synchronized to CLKA, while PAEBA is synchronized to CLKB. If the minimum time (tSKEW2) between a rising CLKB and a rising CLKA is met, the flag will change state on the current clock; otherwise, the flag may not change state until the next clock rising edge. For the specific flag timings, refer to Figures 12-15. PORT B CONTROL SIGNALS The Port B control signal pins dictate the various operations shown in Table 5. Port B is independent of CS A. R/WB and ENB lines determine when Data

INDUSTRIAL TEMPERATURE RANGE IDT72605/72615 CMOS SYNCBiFIFO™ 256 x 18x 2 and 512 x 18 x 2 can be written or read in Port B. If R/WB and ENB are LOW, data is written into input register, and on LOW-to-HIGH transition of CLKB data is written into input register and the FIFO memory. If R/WB is HIGH and OEB is LOW, data comes out of bus and is read from output register into three-state buffer. In bypass mode, if R/WB is LOW, bypass messages are transferred into B→A output register. If R/WA is HIGH, bypass messages are transferred into A→B output register. Refer to pin descriptions for more information. TABLE 3 ⎯ FLAG OFFSET REGISTER FORMAT NOTE: 1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO. 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 PAEAB Register XXXXXXXXX A →B FIFO Almost-Empty Flag Offset 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 PAFAB Register XXXXXXXXX A →B FIFO Almost-Full Flag Offset 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 PAEBA Register XXXXXXXXX B →A FIFO Almost-Empty Flag Offset 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 PAFBA Register XXXXXXXXX B →A FIFO Almost-Full Flag Offset TABLE 4 ⎯ INTERNAL FLAG TRUTH TABLE Number of Words in FIFO From To EF PAE PAF FF 0 0 LOW LOW HIGH HIGH 1 n HIGH LOW HIGH HIGH n+1 D-(m+1) HIGH HIGH HIGH HIGH D-m D-1 HIGH HIGH LOW HIGH D D HIGH HIGH LOW LOW NOTE: 1. n = Programmable Empty Offset ( PAEAB Register or PAEBA Register) m = Programmable Full Offset ( PAFAB Register or PAFBA Register) D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words) TABLE 5 ⎯ PORT B OPERATION CONTROL SIGNALS Data B R/WB ENB OEB I/O Port B Operation 000 I Data B is written on CLKB ↑. This write cycle immediately following output low-impedance cycle is prohibited. Note that even though OEB = 0, a LOW logic level on R/WB, once qualified by a rising edge on CLKB, will put Data B into a high- impedance state. 0 0 1 I Data B is written on CLKB ↑. 0 1 X I Data B is ignored 1 0 0 O Data is read (1) from RAM array to output register on CLKB ≠ Data B is low-impedance 1 0 1 O Data is read (1) from RAM array to output register on CLKB ≠, Data B is high- impedance 1 1 0 O Output register does not change (2), Data B is low-impedance 1 1 1 O Output register does not change (2), Data B is high-impedance NOTES: 1. When A 2A1A0 = 000 or 1XX, the next A →B FIFO value is read out of the output register and the read pointer advances. If A 2A1A0 = 001, the bypass path is selected and bypass data is read from the Port B output register. 2. Regardless of the condition of A 2A1A0, the data in the Port B output register does not change and the A →B read pointer does not advance.

1. When t SKEW1 ≥ minimum specification, t FRL(Max.) = t CLK + t SKEW1

The Latency Timing apply only at the Empty Boundary ( EF = LOW). Figure 9. B→→→→→A First Data Word Latency after Reset for Simultaneous Read and Write

1. When CSA is brought HIGH, A →B Bypass mode will switch to FIFO mode on the following CLK A LOW-to-HIGH transition.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for the next bypass
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B -side will be forced back to FIFO

Figure 10. A→→→→→B Bypass Timing

1. When CSA is brought HIGH, A →→→→→B Bypass mode will switch to FIFO mode on the following CLK A going LOW-to-HIGH.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B -side will be forced back to FIFO

Figure 11. B→→→→→A Bypass Timing

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DATASHEET DOCUMENT HISTORY 11/02/2000 pgs. 1, 2, 3, 4, 16 04/08/2003 pg. 17. 02/08/2009 pgs. 1 and 17. 02/25/2013 pgs. 1, 7 and 17. XXXXX X XX X X Device Type Power Speed Package Process/ Temperature Range Blank J PF L 72605 72615 Industrial (-40°C to +85°C) Plastic Leaded Chip Carrier (PLCC, J68-1) Thin Quad Flat Pack (TQFP, PN64-1) Low Power 256 x 18 ⎯ Parallel SyncBiFIFO 512 x 18 ⎯ Parallel SyncBiFIFO 2704 drw19 Clock Cycle Time (tCLK) in Nanoseconds Blank Tube or Tray Tape and Reel X