ICM7242_07 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 10

Technical content

Features

  • Replaces the 2242 in Most Applications
  • Timing From Microseconds to Days
  • Cascadable
  • Monostable or Astable Operation
  • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout ICM7242 (8 LD PDIP, SOIC) TOP VIEW

Ordering Information

TEMP . RANGE (°C) PACKAGE PKG. DWG. # ICM7242IPA 7242 IPA -25 to +85 8 Ld PDIP E8.3 ICM7242IPAZ (See Note)

7242 IPAZ -25 to +85 8 Ld PDIP**

(Pb-free) E8.3 ICM7242CBAZ* 7242 CBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15 ICM7242IBAZ* 7242 IBAZ -25 to +85 8 Ld SOIC (Pb-free) M8.15 *Add “-T” suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 VDD ÷2 OUT ÷128/256 OUT VSS TB I/O RC TRIGGER RESET Data Sheet FN2866.4 February 9, 2007 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN2866.4 February 9, 2007 Functional Block Diagram R Q Q S R 1 4 8 5 6 2 3 TRIGGERRESET ÷2 OUTTB I/OVSS Q Q S CL Q Q S CL Q Q S CL Q Q S CL ÷128/256 OUTPUT 50k 86k 50k VDD RC Q Q S CL Q Q S CL Q Q S CL Q Q S CL ICM7242

3 FN2866.4 February 9, 2007 Absolute Maximum Ratings Thermal Information Input Voltage (Note 1) Operating Conditions Temperature Range Thermal Resistance (Typical, Note2) θJA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to the device before its supply is established and, that in multiple supply systems, the supply to the ICM7242 be turned on first. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, TA = +25°C, R = 10kΩ, C = 0.1µF, VSS = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Guaranteed Supply Voltage V DD 2- 1 6 V Supply Current I DD Reset - 125 - µA Operating, R = 10kΩ, C = 0.1µF - 340 800 µA Operating, R = 1MΩ, C = 0.1µF - 220 600 µA TB Inhibited, RC Connected to V SS - 225 - µA Timing Accuracy -5- % RC Oscillator Frequency Temperature Drift Δf/Δt Independent of RC Components - 250 - ppm/°C Time Base Output Voltage V OTB ISOURCE = 100µA - 3.5 - V ISINK = 1.0mA - 0.40 - V Time Base Output Leakage Current I TBLK RC = Ground - - 25 µA Trigger Input Voltage V TRIG VDD = 5V - 1.6 2.0 V VDD = 15V - 3.5 4.5 V Reset Input Voltage V RST VDD = 5V - 1.3 2.0 V VDD = 15V - 2.7 4.0 V Trigger/Reset Input Current I TRIG, IRST -1 0-µ A Max Count Toggle Rate f T VDD = 2V Counter/Divider Mode -1- M H z VDD = 5V 2 6 - MHz VDD = 15V - 13 - MHz 50% Duty Cycle Input with Peak to Peak Voltages Equal to VDD and VSS Output Saturation Voltage V SAT All Outputs Except TB Output VDD = 5V, IOUT = 3.2mA - 0.22 0.4 V Output Sourcing Current I SOURCE VDD = 5V Terminals 2 and 3, VOUT = 1V - 300 - µA MIN Timing Capacitor (Note 3) C T 10 - - pF Timing Resistor Range (Note 3) R T VDD = 2 - 16V 1k - 22M Ω NOTE: 3. For design only, not tested. ICM7242ICM7242

NOTE: Select RC values for des ired “ON TIME” for each ICM7242. FIGURE 6. SEQUENCE TIMER

9 FN2866.4 February 9, 2007 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93 ICM7242

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2866.4 February 9, 2007 ICM7242ICM7242 Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05