IDT72421_13 IDT | Alldatasheet

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CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72421, IDT72201 IDT72211, IDT72221 IDT72231, IDT72241 IDT72251 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2655/6 FEATURES:

  • •••• 64 x 9-bit organization (IDT72421)
  • •••• 256 x 9-bit organization (IDT72201)
  • •••• 512 x 9-bit organization (IDT72211)
  • •••• 1,024 x 9-bit organization (IDT72221)
  • •••• 2,048 x 9-bit organization (IDT72231)
  • •••• 4,096 x 9-bit organization (IDT72241)
  • •••• 8,192 x 9-bit organization (IDT72251)
  • •••• 10 ns read/write cycle time
  • •••• Read and Write Clocks can be independent
  • •••• Dual-Ported zero fall-through time architecture
  • •••• Empty and Full Flags signal FIFO status
  • •••• Programmable Almost-Empty and Almost-Full flags can be set to any depth
  • •••• Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively
  • •••• Output enable puts output data bus in high-impedance state
  • •••• Advanced submicron CMOS technology
  • •••• Available in the 32-pin plastic leaded chip carrier (PLCC) and 32-pin Thin Quad Flat Pack (TQFP)
  • •••• For through-hole product please see the IDT72420/72200/72210/ 72220/72230/72240 data sheet
  • •••• Industrial temperature range (–40°°°°°C to +85°°°°°C) is available
  • •••• Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM WCLK WEN1 WEN2 D0 - D8 LD OFFSET REGISTERINPUT REGISTER RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 WRITE CONTROL LOGIC WRITE POINTER OUTPUT REGISTER READ CONTROL LOGIC READ POINTER FLAG LOGIC EF PAE PAF FF RESET LOGIC OE REN2 REN1 RS RCLK 2655 drw01 Q0 - Q8 DESCRIPTION: The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™ are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a 64, 256, 512, 1,024, 2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin (LD). These FIFOs are fabricated using high-speed submicron CMOS technology.

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 PIN CONFIGURATION TQFP (PR32-1, order code: PF) TOP VIEW PLCC (J32-1, order code: J) TOP VIEW RS WEN1 WCLK WEN2/LD VCC PAF PAE GND REN1 RCLK REN2 27 26 25 29 2832 31 30 9 1 01 11 21 31 41 5 2655 drw 02 EF OE FF INDEX RS WEN1 WCLK WEN2/LD VCC PAF PAE GND REN1 RCLK REN2 OE 432 32 31 30 14 15 16 17 18 19 20 FF EF INDEX 2655 drw02a Symbol Name I/O Description D0-D8 Data Inputs I Data inputs for a 9-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. WEN1 Write Enable 1 I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. WEN2/ Write Enable 2/ I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH LD Load at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Q0-Q8 Data Outputs O Data outputs for a 9-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. REN1 Read Enable 1 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. REN2 Read Enable 2 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. PAE Programmable O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default Almost-Empty Flag offset at reset is Empty+7. PAE is synchronized to RCLK. PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset Almost-Full Flag at reset is Full-7. PAF is synchronized to WCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. VCC Power One +5 volt power supply pin. GND Ground One 0 volt ground pin. PIN DESCRIPTIONS

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT72421 IDT72201 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 Com'l and Ind'l (1) Com'l and Ind'l (1) tCLK = 10, 15, 25 ns t CLK = 10, 15, 25 ns ILI(2) Input Leakage Current (Any Input) –1 — 1 –1 — 1 μA ILO(3) Output Leakage Current –10 — 10 –10 — 10 μA VOH Output Logic “1” Voltage, IOH = –2mA 2.4 — — 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8mA — — 0.4 — — 0.4 V ICC1(4,5,6) Active Power Supply Current — — 35 — — 50 mA ICC2(4,7) Standby Current — — 5 — — 5 mA NOTES: 1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product. 2. Measurements with 0.4 ≤≤≤≤≤ V 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ V CC. 4. Tested with outputs open (I OUT = 0). 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. Typical I CC1 = 1.7 + 0.7*f S + 0.02*C L*fS (in mA). These equations are valid under the following conditions: V CC = 5V, T A = 25 °C, f S = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f S/2, C L = capacitive load (in pF). 7. All Inputs = V CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. DC ELECTRICAL CHARACTERISTICS (Commercial: V CC = 5V ± 10%, T A = 0 °C to +70 °C; Industrial: V CC = 5V ± 10%, T A = –40 °C to +85 °C) Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with –0.5 to +7.0 V Respect to GND TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V Commercial/Industrial GND Supply Voltage 0 0 0 V V IH Input High Voltage 2.0 — — V Commercial/Industrial V IL Input Low Voltage — — 0.8 V Commercial/Industrial T A Operating Temperature 0 — +70 °C Commercial TA Operating Temperature –40 — +85 °C Industrial NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS

Figure 1. Output Load

  1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
  2. Pulse widths less than minimum values are not allowed.
  3. Values guaranteed by design, not currently tested.
  4. With output deselected (OE ≥ VIH).
  5. Characterized values, not currently tested.

(HIGH), the Q output data bus is in a high-impedance state. programmable flags or to have two write enables, which allows depth expansion. operates as a second write enable pin. independently of any ongoing read operation. and no new data is allowed to be loaded into the register. and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full. 3 for details of the size of the registers and the default values. (Least Significant Bit) Offset register. Enable 1 (WEN1) is LOW, the next offset register in sequence is written. Data inputs for 9-bit wide data. initialized to all zeros and the offset registers are initialized to their default values. (PAF) are synchronized with respect to the LOW-to-HIGH transition of WCLK. The Write and Read Clocks can be asynchronous or coincident. sequentially and independently of any ongoing read operation. holds the previous data and no new data is allowed to be loaded into the register. below for operation in this configuration. is ignored when the FIFO is full. (PAE) are synchronized with respect to the LOW-to-HIGH transition of RCLK. The Write and Read Clocks can be asynchronous or coincident. the previous data and no new data is allowed to be loaded into the register.

  1. For the purposes of this table, WEN2 = VIH.
  2. The same selection sequence applies to reading from the registers. REN1 and REN2

are enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register

Figure 3. Offset Register Location and Default Values

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72421, 256 writes for the IDT72201, 512 writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the IDT72231, 4,096 writes for the IDT72241, and 8,192 writes for the IDT72251. The Full Flag ( FF) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock (WCLK). EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock (RCLK). PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW when the FIFO reaches the almost-full condition. If no reads are performed after Reset (RS), the Programmable Almost-Full flag (PAF) will go LOW after (64-m) writes for the IDT72421, (256-m) writes for the IDT72201, (512-m) writes for the IDT72211, TABLE 1 — STATUS FLAGS NUMBER OF WORDS IN FIFO IDT72421 IDT72201 IDT72211 FF PAF PAE EF 00 0 H H L L 1 to n 1 to n 1 to n H H L H (64-m)(2) to 63 (256-m) (2) to 255 (512-m) (2) to 511 H L H H 64 256 512 L L H H NUMBER OF WORDS IN FIFO IDT72221 IDT72231 IDT72241 IDT72251 FF PAF PAE EF 00 0 0 H H L L 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HH LH 1,024 2,048 4,096 8,192 L L H H NOTES: 1. n = Empty Offset (n = 7 default value) 2. m = Full Offset (m = 7 default value) (1,024-m) writes for the IDT72221, (2,048-m) writes for the IDT72231, (4,096- m) writes for the IDT72241, and (8,192-m) writes for the IDT72251. The offset “m” is defined in the Full offset registers. If there is no Full offset specified, the Programmable Almost-Full flag (PAF) will go LOW at Full-7 words. The Programmable Almost-Full flag (PAF) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock (WCLK). PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty flag (PAE) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the Empty Offset registers. If no reads are performed after Reset the Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the IDT72421/72201/72211/72221/72231/72241/72251. If there is no Empty offset specified, the Programmable Almost-Empty flag (PAE) will go LOW at Empty+7 words. The Programmable Almost-Empty flag (PAE) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock (RCLK). DATA OUTPUTS (Q 0 - Q8) Data outputs for a 9-bit wide data. (1) (1) (1)

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ORDERING INFORMATION

NOTES: 1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product. 2. Green parts are available. For specific speeds and packages contact your sales office. 2655 drw18 Commercial (0°C to +70°C) Industrial (-40° to +85°C) XXXXX Device Type X XX X X Power Speed Package Process/ Temperature Range Clock Cycle Time (tCLK) Speed in Nanoseconds Plastic Leaded Chip Carrier (PLCC, J32-1) Thin Quad Flat Pack (TQFP, PR32-1) Commercial Only Commercial & Industrial Commercial & Industrial 64 x 9 ⎯ SyncFIFO 256 x 9 ⎯ SyncFIFO 512 x 9 ⎯ SyncFIFO 1,024 x 9 ⎯ SyncFIFO 2,048 x 9 ⎯ SyncFIFO 4,096 x 9 ⎯ SyncFIFO 8,192 x 9 ⎯ SyncFIFO BLANK I (1) J PF L 72421 72201 72211 72221 72231 72241 72251 Low Power X G Green(2) BLANK Tube or Tray Tape and Reel X DATASHEET DOCUMENT HISTORY 10/03/2000 pgs. 2, 3, 4 and 14. 05/01/2001 pgs. 1, 2, 3, 4 and 14. 02/08/2006 pgs. 1 and 14. 10/22/2008 pg. 14. 08/08/2013 pgs. 1, 3, 13 and 14.