72420L10TPG

IDT72420_13 IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 11

Technical content

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE ©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2680/6 DESCRIPTION: The IDT72420/72200/72210/72220/72230/72240 SyncFIFO™ are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a 64, 256, 512, 1,024, 2,048, and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a Write Enable pin (WEN). Data is written into the Synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and a Read Enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided for improved system control. The partial (AE) flags are set to Empty+7 and Full- 7 for AE and AF respectively. These FIFOs are fabricated using high-speed submicron CMOS technol- ogy. FUNCTIONAL BLOCK DIAGRAM FEATURES:

• •••• 64 x 8-bit organization (IDT72420)
• •••• 256 x 8-bit organization (IDT72200)
• •••• 512 x 8-bit organization (IDT72210)
• •••• 1,024 x 8-bit organization (IDT72220)
• •••• 2,048 x 8-bit organization (IDT72230)
• •••• 4,096 x 8-bit organization (IDT72240)
• •••• 10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/ 72240)
• •••• Read and Write Clocks can be asynchronous or coincidental
• •••• Dual-Ported zero fall-through time architecture
• •••• Empty and Full flags signal FIFO status
• •••• Almost-Empty and Almost-Full flags set to Empty+7 and Full-7, respectively
• •••• Output enable puts output data bus in high-impedance state
• •••• Produced with advanced submicron CMOS technology
• •••• Available in 28-pin 300 mil plastic DIP
• •••• For surface mount product please see the IDT72421/72201/72211/ 72221/72231/72241 data sheet
• •••• Green parts available, see ordering information INPUT REGISTER OUTPUT REGISTER RAM ARRAY 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 FLAG LOGIC READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WCLK RCLK REN D0 - D7 Q0 - Q7 RS OE FF AF AE EF WEN 2680 drw01

COMMERCIAL TEMPERATURE RANGE IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 PIN CONFIGURATION Symbol Name I/O Description D0 - D7 Data Inputs I Data inputs for a 8-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted. WEN Write Enable I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written into the FIFO if the FF is LOW. Q0 - Q7 Data Outputs O Data outputs for a 8-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. REN Read Enable I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. AE Almost-Empty Flag O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK. AF Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. VCC Power One +5 volt power supply pin. GND Ground One 0 volt ground pin. PIN DESCRIPTIONS PLASTIC THIN DIP (P28-2, order code: TP) TOP VIEW AF AE GND RCLK REN OE EF FF RS WEN WCLK VCC 2680 drw02

COMMERCIAL TEMPERATURE RANGE IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONS NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 3. Tested with outputs open (I OUT = 0). 4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 5. Typical I CC1 = 1.7 + 0.7*fS + 0.02*CL*fS (in mA). These equations are valid under the following conditions: VCC = 5V, TA = 25°°°°°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f S/2, CL = capacitive load (in pF). 6. All Inputs = V CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 Commercial t CLK = 10, 15, 25 ns Symbol Parameter Min. Typ. Max. Unit ILI(1) Input Leakage Current (any input) –1 — 1 μA ILO(2) Output Leakage Current –10 — 10 μA VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V ICC1(3,4,5) Active Power Supply Current — — 40 mA ICC2(3,6) Standby Current — — 5 mA Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with –0.5 to +7.0 V Respect to GND TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V Commercial GND Supply Voltage 0 0 0 V V IH Input High Voltage 2.0 — — V Commercial V IL Input Low Voltage — — 0.8 V Commercial T A Operating Temperature 0 — 70 °C Commercial

1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.

Figure 1. Output Load *Includes jig and scope capacitances.

1. With output deselected. ( OE ≥ VIH)
2. Characterized values, not currently tested.

COMMERCIAL TEMPERATURE RANGE IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after t REF and a valid read can begin. Read Enable (REN) is ignored when the FIFO is empty. OUTPUT ENABLE (OE) — When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high- impedance state. OUTPUTS: FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256 writes for the IDT72200, 512 writes for the IDT72210, 1,024 writes for the IDT72220, 2,048 writes for the IDT72230, and 4,096 writes for the IDT72240. The Full Flag ( FF) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock (WCLK). EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock (RCLK). ALMOST-FULL FLAG (AF) — The Almost-Full Flag (AF) will go LOW when the FIFO reaches the almost-full condition. If no reads are performed after Reset (RS), the Almost-Full Flag (AF) will go LOW after 57 writes for the IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1,017 writes for the IDT72220, 2,041 writes for the IDT72230 and 4,089 writes for the IDT72240. The Almost-Full Flag (AF) is synchronized with respect to the LOW-to- HIGH transition of the Write Clock (WCLK). ALMOST-EMPTY FLAG (AE) — The Almost-Empty Flag (AE) will go LOW when the FIFO reaches the almost-empty condition. If no reads are performed after Reset (RS), the Almost-Empty Flag (AE) will go HIGH after 8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240. The Almost-Empty Flag (AE) is synchronized with respect to the LOW- to-HIGH transition of the Read Clock (RCLK). DATA OUTPUTS (Q 0–Q7) — Data outputs for 8-bit wide data. SIGNAL DESCRIPTIONS INPUTS: Data In (D0–D7) — Data inputs for 8-bit wide data. CONTROLS: RESET (RS) — Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The Full Flag (FF) and Almost-Full Flag (AF) will be reset to HIGH after t RSF. The Empty Flag (EF) and Almost-Empty Flag (AE) will be reset to LOW after t RSF. During reset, the output register is initialized to all zeros. WRITE CLOCK (WCLK) — A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH transition of the Write Clock. The Full Flag (FF) and Almost-Full Flag (AF) are synchronized with respect to the LOW- to-HIGH transition of the Write Clock. The Write and Read Clocks can be asynchronous or coincident. WRITE ENABLE (WEN) — When Write Enable (WEN) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. When Write Enable (WEN) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag ( FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after t WFF, allowing a valid write to begin. Write Enable (WEN) is ignored when the FIFO is full. READ CLOCK (RCLK) — Data can be read on the outputs on the LOW-to- HIGH transition of the Read Clock (RCLK). The Empty Flag ( EF) and Almost-Empty flag (AE) are synchronized with respect to the LOW-to-HIGH transition of the Read Clock. The Write and Read Clocks can be asynchronous or coincident. READ ENABLE (REN) — When Read Enable (REN) is LOW, data is read from the RAM array to the output register on the LOW-to-HIGH transition of the Read Clock (RCLK). When Read Enable ( REN) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. Number of Words in FIFO IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 FF AF AE EF 000 0 0 0 H H L L 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 H H L H 8 to 56 8 to 248 8 to 504 8 to 1,016 8 to 2,040 8 to 4,088 HHHH 57 to 63 249 to 255 505 to 511 1,017 to 1,023 2,041 to 2,047 4,089 to 4,095 H L H H 64 256 512 1,024 2,048 4,096 L L H H TABLE 1 — STATUS FLAGS

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com DEPTH EXPANSION The IDT72420/72200/72210/72220/72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1,024/ 2,048/4,096 words. Depth expansion is possible by using expansion logic to direct the flow of data. A typical application would have the expansion logic alternate data accesses from one device to the next in a sequential manner. Please see the Application Note “DEPTH EXPANSION IDT'S SYNCHRONOUS FIFOs USING RING COUNTER APPROACH” for details of this configuration.

ORDERING INFORMATION

NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. XXXXX DeviceType X Power XX Speed XX Package X Process / Temperature Range Low Power L Commercial BLANK Commercial (0°C to +70°C) TP Plastic Thin DIP (300 mil, P28-2) Clock Cycle Time (t CLK) Speed in Nanoseconds 72420 72200 72210 72220 72230 72240 64x 8 SyncFIFO 256 x 8 SyncFIFO 512 x 8 SyncFIFO 1,024 x 8 SyncFIFO 2,048 x 8 SyncFIFO 4,098 x 8 SyncFIFO 2680 drw14 X G Green DATASHEET DOCUMENT HISTORY 10/03/2000 pgs. 1, 3, 4 and 11. 05/01/2001 pgs. 1, 2, 3, 4 and 11. 02/10/2006 pgs. 1 and 11. 01/08/2009 pg. 11. 07/25/2013 pgs. 1, 3, 9 and 10.