72413L45PG

IDT72413 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: gvasquez
• PDF pages: 11

Technical content

CMOS PARALLEL FIFO WITH FLAGS 64 x 5 FEATURES:

• First-ln/First-Out Dual-Port memory—45MHz
• 64 x 5 organization
• Low-power consumption — Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth
• Half-Full and Almost-Full/Empty status flags
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CMOS technology
• Available in plastic DIP and SOIC
• Green parts available, see ordering information DESCRIPTION: The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis. It is expandable in bit width. All speed versions are cascad-able in depth. The FIFO has a Half-Full Flag, which signals when it has 32 or more words in memory. The Almost-Full/Empty Flag is active when there are 56 or more words in memory or when there are 8 or less words in memory. This device is pin and functionally compatible to the MMI67413. It operates at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers anD graphics controllers. The IDT72413 is fabricated using high-performance CMOS process. This process maintains the speed and high output drive capability of TTL circuits in low-power CMOS. FUNCTIONAL BLOCK DIAGRAM 2748 drw 01 DATAIN (D0-4 FIFO INPUT STAGE 64 x 5 MEMORY ARRAY FIFO OUTPUT STAGE INPUT CONTROL LOGIC REGISTER CONTROL LOGIC OUTPUT CONTROL LOGIC FLAG CONTROL LOGIC (MR) MASTER RESET INPUT READY SHIFT IN (IR) (SI) DATAOUT (Q0-4 ) SHIFT OUT OUPUT READY (SO) (OR) OUPUT ENABLE (OE) HALF-FULL (HF) ALMOST-FULL/ EMPTY (AF/E) OBSOLETE PART NOT RECOMMENDED FORNEW DESIGNS

IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial Unit VTERM Terminal Voltage with –0.5 to +7.0 V Respect to GND TSTG Storage –55 to +125 ° C Temperature IOUT DC Output –50 to +50 mA Current NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V Commercial GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.0 — — V VIL(1) Input Low Voltage — — 0.8 V TA Operating Temperature 0 — 70 ° C Commercial NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions Max. Unit CIN Input Capacitance V IN = 0V 5 pF COUT Output Capacitance V OUT = 0V 7 pF NOTE: 2748 tbl 02 1. Characterized values, not currently tested. PLASTIC DIP (P20-1, ORDER CODE: P) SOIC (SO20-2, ORDER CODE: SO) TOP VIEW HF IR SI Vcc OE SO AF/E OR GND MR 2748 drw 02 IDT72413 Commercial fIN = 45, 35, 25 MHz Symbol Parameter Test Conditions Min. Max. Unit IIL Low-Level Input Current VCC = Max., GND ≤ V I ≤ V CC –10 — µ A IIH High-Level Input Current VCC = Max., GND ≤ VI ≤ VCC — 1 0 µ A VOL Low-Level Output Current VCC = Min. I OL (Q 0-4 ) 24 mA — 0.4 V IOL (IR, OR) (1) 8mA IOL (HF, AF/E) 8mA VOH High-Level Output Current VCC = Min. I OH (Q 0-4 ) –4mA 2.4 — V IOH (IR, OR) –4mA IOH (HF, AF/E) –4mA IOS(2) Output Short-Circuit Current VCC = Max. V O = 0V –20 –110 mA IHZ HIGH Impedance Output Current V CC = Max. V O = 2.4V — 20 µA ILZ LOW Impedance Output Current V CC = Max. V O = 0.4V –20 — µA ICC(3,4) Active Supply Current VCC = Max., OE = HIGH — 60 mA Inputs LOW, f = 25MHz NOTES: 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25MHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. Tested with outputs open (I OUT = 0). 4. For frequencies greater than 25MHz, I CC = 60mA + (1.5mA x [f –25MHz]) DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)

IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5 COMMERCIAL TEMPERATURE RANGE OPERATING CONDITIONS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Commercial IDT72413L45 IDT72413L35 IDT72413L25 tSIH(1) Shift in HIGH Time 2 9 — 9 — 16 — ns tSIL(1) Shift in LOW TIme 2 11 — 17 — 20 — ns tIDS Input Data Set-up 2 0 — 0 — 0 — ns tIDH Input Data Hold Time 2 13 — 15 — 25 — ns tSOH(1) Shift Out HIGH Time 5 9 — 9 — 16 — ns tSOL Shift Out LOW Time 5 11 — 17 — 20 — ns tMRW Master Reset Pulse 8 20 — 30 — 35 — ns tMRS Master Reset Pulse to SI 8 20 — 35 — 35 — ns NOTE: 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Commercial IDT72413L45 IDT72413L35 IDT72413L25 fIN Shift In Rate 2 — 45 — 35 — 25 M H z tIRL(1) Shift In ↑ to Input Ready LOW 2 — 18 — 18 — 28 ns tIRH(1) Shift In ↓ to Input Ready HIGH 2 — 18 — 20 — 25 ns fOUT Shift Out Rate 5 — 45 — 35 — 25 M H z tORL(1) Shift Out ↓ to Output Ready LOW 5 — 18 — 18 — 28 ns tORH(1) Shift Out ↓ to Output Ready HIGH 5 — 19 — 20 — 25 ns tODH(1) Output Data Hold Previous Word 5 5 — 5 — 5 — ns tODS Output Data Shift Next Word 5 — 19 — 20 — 20 ns tPT Data Throughput or "Fall-Through" 4, 7 — 25 — 28 — 40 ns tMRORL Master Reset ↓ to Output Ready LOW 8 — 25 — 28 — 30 ns tMRIRH(3) Master Reset ↑ to Input Ready HIGH 8 — 25 — 28 — 30 ns tMRIRL(2) Master Reset ↓ to Input Ready LOW 8 — 25 — 28 — 30 ns tMRQ Master Reset ↓ to Outputs LOW 8 — 20 — 25 — 35 ns tMRHF Master Reset ↓ to Half-Full Flag 8 — 25 — 28 — 40 ns tMRAFE Master Reset ↓ to AF/E Flag 8 — 25 — 28 — 40 ns tIPH(3) Input Ready Pulse HIGH 4 5 — 5 — 5 — ns tOPH(3) Output Ready Pulse HIGH 7 5 — 5 — 5 — ns tORD(3) Output Ready ↑ HIGH to Valid Data 5 — 5 — 5 — 7 ns tAEH Shift Out ↑ to AF/E HIGH 9 — 28 — 28 — 40 ns tAEL Shift In ↑ to AF/E 9 — 28 — 28 — 40 ns tAFL Shift Out ↑ to AF/E LOW 10 — 28 — 28 — 40 ns tAFH Shift In ↑ to AF/E HIGH 10 — 28 — 28 — 40 ns tHFH Shift In ↑ to HF HIGH 11 — 28 — 28 — 40 ns tHFL Shift Out ↑ to HF LOW 11 — 28 — 28 — 40 ns tPHZ(3) Output Disable Delay 12 — 12 — 12 — 15 ns tPLZ (3) 12 — 12 — 12 — 15 tPLZ (3) Output Enable Delay 12 — 15 — 15 — 20 ns tPHZ(3) 12 — 15 — 15 — 20 NOTES: 1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between V CC and GND with very short lead length is recommended. 2. If the FIFO is full, (IR = HIGH), MR ↑ forces IR to go LOW, and MR ↓ causes IR to go HIGH. 3. Guaranteed by design but not currently tested.

Figure 1. Output Load The FIFO must be reset upon power up using the Master Reset (MR) signal. last valid word read from the FIFO will remain at the FlFOs output when it is empty. the data reaches the output, the Output Ready (OR) goes HIGH. clock cycle) is far less than the delay of a Shift register-based FIFO. Data input lines. The IDT72413 has a 5-bit data input.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 15. 128 x 5 Depth Expansion

ORDERING INFORMATION

Plastic DIP (300 mil, P20-1) Small Outline IC (300 mil, J-bend, SOIC SO20-2) Commercial (0°C to +70°C) Low Power 2748 drw18 Commercial XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK 72413 64 x 5 - FIFO Shift Frequency (fS) Speed in MHz P(3) SO L G(2) X Green Tube or Tray Tape and Reel BLANK X NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available, for specific speeds and packages contact your sales office. 3. For “P”, Plastic Dip, when ordering green package, the suffix is “PDG”. 2748 drw 17 IR SI SO OR IR SI SO OR SHIFT IN INPUT READY DATA IN OUTPUT READY SHIFT OUT DATA OUT D4 Q4 D4 Q4 DATASHEET DOCUMENT HISTORY 07/10/2003 pgs. 1, 2, 3, and 10. 02/11/2009 pgs. 1 and 10. 06/29/2012 pgs. 1, 2, 9 and 10. 11/21/2014 PDN# CQ-14-08 issued. See IDT.com for PDN specifics. 08/08/2019 Datasheet changed to Obsolete Status.

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.