72403L15DG

IDT72401 RENESAS | Alldatasheet

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• Manufacturer or author: lwoods
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT72401 IDT72403 OBSOLETE PARTS CMOS PARALLEL FIFO 64 x 4 FEATURES:

• •• •• First-ln/First-Out Dual-Port memory
• •• •• 64 x 4 organization (IDT72401/72403)
• •• •• RAM-based FIFO with low falI-through time
• •• •• Low-power consumption — Active: 175mW (typ.)
• •• •• Maximum shift rate — 45MHz
• •• •• High data output drive capability
• •• •• Asynchronous and simultaneous read and write
• •• •• Fully expandable by bit width
• •• •• Fully expandable by word depth
• •• •• IDT72403 have Output Enable pin to enable output data
• •• •• High-speed data communications applications
• •• •• High-performance CMOS technology
• •• •• Available in CERDIP, plastic DIP and SOIC
• •• •• Military product compliant to MlL-STD-883, Class B
• •• •• Standard Military Drawing #5962-86846 and 5962-89523 is listed on this function.
• •• •• Green parts available, see ordering information DESCRIPTION: The IDT72401 and IDT72403 are asynchronous high-performance First-ln/First-Out memories organized 64 words by 4 bits. The IDT72403 also has an Output Enable (OE) pin. The FlFOs accept 4-bit data at the data input (D0-D3). The stored data stack up on a first-in/first-out basis. A Shift Out (SO) signal causes the data at the next to last word to be shifted to the output while all other data shifts down one location in the stack. The Input Ready (IR) signal acts like a flag to indicate when the input is ready for new data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal can also be used to cascade multiple devices together. The Output Ready (OR) signal is a flag to indicate that the output remains valid data (OR = HIGH) or to indicate that the FIFO is empty (OR = LOW). The OR can also be used to cascade multiple devices together. Width expansion is accomplished by logically ANDing the IR and OR signals to form composite signals. Depth expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The IR pin of the receiving device is connected to the SO pin of the sending device and the OR pin of the sending device is connected to the Shift In (SI) pin of the receiving device. Reading and writing operations are completely asynchronous allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed makes these FlFOs ideal for high- speed communication and controller applications. Military grade product is manufactured in compliance with the of MIL-STD- 883, Class B. FUNCTIONAL BLOCK DIAGRAM WRITE POINTERINPUT CONTROL LOGIC 2747 drw01 SI DATA IN MASTER RESET WRITE MULTIPLEXER MEMORY ARRAY READ POINTER READ MULTIPLEXER IR D0-3 MR OUTPUT ENABLE DATA IN MASTER RESET SO OR Q0-3 OE (IDT72403 only) OBSOLETE PARTS NOT RECOMMENDED FORNEW DESIGNS

CMOS PARALLEL FIFO 64 x 4, 64 x 5 PIN CONFIGURATIONS NOTE: 1. Pin 1: NC - No Connection IDT72401, OE - IDT72403 IDT72401/IDT72403 PLASTIC DIP (P16-1, ORDER CODE: P) CERDIP (D16-1, ORDER CODE: D) SOIC (SO16-1, ORDER CODE: SO) TOP VIEW Symbol Rating Commercial Military Unit VTERM Terminal Voltage with –0.5 to +7.0 –0.5 to +7.0 V Respect to GND TSTG Storage Temp. –55 to +125 –65 to +150 °C IOUT DC Output Current –50 to +50 –50 to +50 mA Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage Commercial/Military 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.0 — — V VIL(1) Input High Voltage — — 0.8 V TA Operating Temperature Commercial 0 — 70 °C TA Operating Temperature Military –55 — 125 °C IDT72401 IDT72401 IDT72403 IDT72403(5) Commercial Military fIN = 45, 35, 25, 15, 10 MHz f IN = 35, 25, 15, 10 MHz Symbol Parameter Test Conditions Min. Max. Min. Max. Unit IIL Low-Level Input Current VCC = Max., GND ≤ VI ≤ VCC –10 — –10 — µA IIH High-Level Input Current VCC= Max., GND ≤ VI ≤ VCC —1 0— 1 0 µ A VOL Low-Level Output Voltage VCC= Min., IOL = 8mA — 0.4 — 0.4 V VOH High-Level Output Voltage VCC= Min., IOH = –4mA 2.4 — 2.4 — V IOS(1) Output Short-Circuit Current VCC= Max., V O = GND –20 –110 –20 –110 mA IHZ(2) HIGH Impedance Output Current V CC= Max., V O = 2.4V — 20 — 20 µA ILZ(2) LOW Impedance Output Current V CC= Max., V O = 0.4V –20 — –20 — µA ICC(3,4) Active Supply Current VCC= Max., f = 10MHz — 35 — 45 mA ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONS NC/OE(1) IR Vcc SI GND SO OR MR 2747 drw 02 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. NOTES: 1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested. 2. IDT72403 only. 3. Tested with outputs open (I OUT = 0). OE is HIGH for IDT72403. 4. For frequencies greater than 10MHz, I CC = 35mA + (1.5mA x [f –10MHz]) commercial, and I CC = 45mA + (1.5mA x [f –10MHz]) military. 5. Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

CMOS PARALLEL FIFO 64 x 4, 64 x 5 MILITARY AND COMMERCIAL TEMPERATURE RANGES OPERATING CONDITIONS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Commercial Commercial and Military(5) IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10 IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10 tSIH (1) Shift in HIGH Time 2 9 — 9 — 11 — 11 — 11 — ns tSIL Shift in LOW TIme 2 11 — 17 — 24 — 25 — 30 — ns tIDS Input Data Set-up 2 0 — 0 — 0 — 0 — 0 — ns tIDH Input Data Hold Time 2 13 — 15 — 20 — 30 — 40 — ns tSOH (1) Shift Out HIGH Time 5 9 — 9 — 11 — 11 — 11 — ns tSOL Shift Out LOW Time 5 11 — 17 — 24 — 25 — 25 — ns tMRW Master Reset Pulse 8 20 — 25 — 25 — 25 — 30 — ns tMRS Master Reset Pulse to SI 8 10 — 10 — 10 — 25 — 35 — ns tSIR Data Set-up to IR 4 3 — 3 — 5 — 5 — 5 — ns tHIR Data Hold from IR 4 13 — 15 — 20 — 30 — 30 — ns tSOR (4) Data Set-up to OR HIGH 7 0 — 0 — 0 — 0 — 0 — ns AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Commercial Commercial and Military(5) IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10 IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10 fIN Shift In Rate 2 — 45 — 35 — 25 — 15 — 10 M H z tIRL (1) Shift In to Input Ready LOW 2 — 18 — 18 — 21 — 35 — 40 ns tIRH (1) Shift In to Input Ready HIGH 2 — 18 — 20 — 28 — 40 — 45 ns fOUT Shift Out Rate 5 — 45 — 35 — 25 — 15 — 10 M H z tORL (1) Shift Out to Output Ready LOW 5 — 18 — 18 — 19 — 35 — 40 ns tORH (1) Shift Out to Output Ready HIGH 5 — 19 — 20 — 34 — 40 — 55 ns tODH Output Data Hold (Previous Word) 5 5 — 5 — 5 — 5 — 5 — ns tODS Output Data Shift (Next Word) 5 — 19 — 20 — 34 — 40 — 55 ns tPT Data Throughput or "Fall-Through" 4, 7 — 30 — 34 — 40 — 65 — 65 ns tMRORL Master Reset to OR LOW 8 — 25 — 28 — 35 — 35 — 40 ns tMRIRH Master Reset to IR HIGH 8 — 25 — 28 — 35 — 35 — 40 ns tMRQ Master Reset to Data Output LOW 8 — 20 — 20 — 25 — 35 — 40 ns tOOE (3) Output Valid from OE LOW 9 — 12 — 15 — 20 — 30 — 35 ns tHZOE (3,4) Output High-Z from OE HIGH 9 — 12 — 12 — 15 — 25 — 30 ns tIPH (2,4) Input Ready Pulse HIGH 4 9 — 9 — 11 — 11 — 11 — ns tOPH (2,4) Output Ready Pulse HIGH 7 9 — 9 — 11 — 11 — 11 — ns NOTES: 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between V CC and GND with very short lead length is recommended. 2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades. 3. IDT72403 only. 4. Guaranteed by design but not currently tested. 5. Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz.

Data input lines. The IDT72401 and IDT72403 have a 4-bit data input. can be written to the FIFO via the D0-3 lines. be read from the FIFO via the Data Output (Q0-3) lines. FIFO should be cleared with a MR. MR is active LOW. to cascade many FlFOs together, as shown in Figures 10 and 11. cascade many FlFOs together, as shown in Figures 10 and 11. Output enable is used to read FIFO data onto a bus. OE is active LOW. Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output. Figure 1. AC Test Load

1. Characterized values, not currently tested.

1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,

indicating data at the output is not valid.

1. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data

has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.

1. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one

first word and will not appear on the outputs until SO has been brought LOW.

1. When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be

enter the memory until SI goes HIGH.

1. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the

variation of delays of the FIFOs. Figure 11. 192 x 12 Depth and Width Expansion

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com

ORDERING INFORMATION

X Speed X Power X Package X Process/ Temperature Range Blank B P(3) D SO L 72401 72403 Commercial (0°C to+70°C) Military (-55°C to+125°C) Compliant to MIL-STD-883, Class B Plastic DIP CERDIP Small Outline IC Commercial Only Commercial and Military Commercial and Military>72401 only Commercial and Military>72401only Commercial and Military Low Power 64 x 4 FIFO 64 x 4 FIFO Shift Frequency (fs) Speed in MHz 2747 drw 16 300 mil, P16-1 300 mil, D16-1 SOIC, SO16-1 G(2) X Green X Blank Tube or Tray Tape and Reel NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available, for specific speeds and packages contact your sales office. 3. For “P”, Plastic Dip, when ordering green package, the suffix is “PDG”. DATASHEET DOCUMENT HISTORY 07/10/2003 pgs. 2, 3, and 9. 10/27/2005 pgs. 1- 9. 04/25/2008 pgs. 1- 9. 02/11/2009 pg. 9. 06/29/2012 pgs. 1 and 9. 09/05/2014 PDN# CQ-14-06R1 issued. See IDT.com for PDN specifics. 08/22/2019 Datasheet changed to Obsolete Status.

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