723612L15PQFG

IDT723612 RENESAS | Alldatasheet

Document overview

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Technical content

2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.© FEBRUARY 2009 CMOS SyncBiFIFO TM 64 x 36 x 2 IDT723612 OBSOLETE PART COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. DSC-3136/3 OBSOLETE PART NOT RECOMMENDED FORNEW DESIGNS

FEATURES

• •• •• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)
• •• •• Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions
• •• •• Mailbox bypass Register for each FIFO
• •• •• Programmable Almost-Full and Almost-Empty Flags
• •• •• Microprocessor interface control logic
• •• •• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• •• •• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• •• •• Passive parity checking on each port
• •• •• Parity generation can be selected for each port
• •• •• Supports clock frequencies up to 67 MHz
• •• •• Fast access times of 10ns
• •• •• Available in 132-pin plastic quad flat package (PQF) or space- saving 120-pin thin quad flat package (TQFP)
• •• •• Industrial temperature range (–40°C to +85°C) is available
• •• •• Green parts available, see ordering information

DESCRIPTION

The IDT723612 is a monolithic high-speed, low-power CMOS bi-directional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Mail 1 Register Input Register Output Register CLKA CSA W/RA ENA MBA Port-A Control Logic Device Control RST CLKB CSB W/RB ENB MBB Port-B Control Logic MBF1 3136 drw01 Mail 2 Register Write Pointer Read Pointer Status Flag Logic Parity Gen/Check A0 -A 35 RAM ARRAY 64 x 36 Parity Generation Parity Gen/Check Programmable Flag Offset Register Status Flag Logic Input Register Output Register RAM ARRAY 64 x 36Parity Generation Read Pointer PEFB PGB EFB AEB FFB AFB ODD/ EVEN FFA AFA FS0 FS1 EFA AEA PGA PEFA MBF2 Write Pointer FIFO2 FIFO1 B0 -B 36 FUNCTIONAL BLOCK DIAGRAM

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL NOTES: 1. Electrical pin 1 in center of beveled edge. 2. NC - No internal connection 3. Uses Yamaichi socket IC51-1324-828 PIN CONFIGURATIONS GND AEB EFB B GND VCC GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23 117 132 130 129 128 127 126 125 124 123 122 121 120 119 118 131 GND AEA EFA GND VCC GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 3136 drw02 VCC VCC A24 A25 A26 A27 GND A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24

83 AFB

V CC PGA FS0 ODD/EVEN FS1 PEFA MBF2 RST NC GND NC NC NC MBF1 GND PEFB V CC W/RB CLKB ENB CSB FFB GND MBA MBB PGB PQFP(2) (PQ132-1, ORDER CODE: PQF) TOP VIEW Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bi-directional interface between microprocessors and/or buses with synchronous control. The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The Empty Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723612 is characterized for operation from 0°C to 70°C.

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS (CONTINUED) TQFP (PN120-1, ORDER CODE: PF) TOP VIEW NOTES: 1. Pin 1 identifier in corner. 2. NC - No internal connection B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND VCC GND EFB AEB AFB A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND VCC GND EFA AEA 3136 drw03 61 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 AFA FFA CSA ENA CLKA W/RA V CC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF PEFB PGB VCC W/RB CLKB ENB CSB FFB 60 B A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A34 A35 B35 GND B34 B33 B32 B30 B31 GND B29 B28 B27 VCC B26 B25 B24 A32 A33

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL Symbol Name I/O Description A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A. AEA Almost-Empty Flag O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in (Port A) the FIFO2 is less than or equal to the value in the offset register, X. AEB Port-B Almost-Empty O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of words in Flag (Port B) FIFO1 is less than or equal to the value in the offset register, X. AFA Port-A Almost-Full O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty Flag (Port A) locations in FIFO1 is less than or equal to the value in the offset register, X. AFB Port-B Almost-Empty O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty Flag (Port B) locations in FIFO2 is less than or equal to the value in the offset register, X. B0-B35 Port-B Data. I/O 36-bit bidirectional data port for side B. CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port-A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port-B and can be asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW- to-HIGH transition of CLKB. CSA Port-A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port-B Chip Select I B must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. EFA Port-A Empty Flag O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is (Port A) empty, and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory. EFB Port-B Empty Flag O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is (Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory. ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. FFA Port-A Full Flag O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full, (Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. FFB Port-B Full Flag O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full, (Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after reset. FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the Almost-Full flag and almost-Empty flag. MBA Port-A Mailbox I A HIGH level on MBA chooses a mailbox register for a port-A read or write operation. When the Select A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level selects FIFO2 output register data for output. MBB Port-B Mailbox I A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the Select B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output, and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW- to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when the device is reset. MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW- to- HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. PIN DESCRIPTION

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION (CONTINUED) Symbol Name I/O Description ODD/ Odd/Even Parity I Odd parity is checked on each port when ODD/ EVEN is HIGH, and even parity is checked when EVEN Select ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. PEFA Port-A Parity Error O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as Flag (Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs. PEFB Port-B Parity Error O When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as Flag (Port B) B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as theparity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. PGA Port-A Parity I Parity is generated for data reads from port A when PGA is HIGH. Generation The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. PGB Port-B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset. W/RA Port-A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH Select transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. W/RB Port-B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH Select transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(2) Symbol Rating Commercial Unit VCC Supply Voltage Range –0.5 to 7 V VI(2) Input Voltage Range –0.5 to V CC+0.5 V VO(2) Output Voltage Range –0.5 to VCC+0.5 V IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA ICC Continuous Current Through VCC or GND ±500 mA TSTG Storage Temperature Range –65 to 150 °C NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to a bsolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. Parameter Test Conditions Min. Typ. (1) Max. Unit VOH VCC = 4.5V, I OH = –4 mA 2.4 — — V VOL VCC = 4.5V, I OL = 8 mA — — 0.5 V ILI VCC = 5.5V, V I = VCC or 0 — — ±50 μA ILO VCC = 5.5V, V O = VCC or 0 — — ±50 μA ICC(2) VCC 5.5V, I O = 0 mA, V I = VCC or GND — — 1 m A CIN VI= 0, f = 1 MHz — 4 — pF COUT VO = 0, f = 1 MHZ — 8 — pF ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) NOTES: 1. All typical values are at V CC = 5V, TA = 25°C. 2. For additional I CC information, see following page. Symbol Parameter Min. Max. Unit VCC Supply Voltage 4.5 5.5 V VIH HIGH Level Input Voltage 2 – V VIL LOW-Level Input Voltage – 0.8 V IOH HIGH-Level Output Current – –4 mA IOL LOW-Level Output Current – 8 mA TA Operating Free-air Temperature 0 70 °C RECOMMENDED OPERATING CONDITIONS

Figure 1. Typical Characteristics: Supply Current vs Clock Frequency

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial Com’l & Ind’l(1) IDT723612L15 IDT723612L20 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB – 66.7 – 50 MHz tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – ns tCLKH Pulse Duration, CLKA and CLKB HIGH 6 – 8 – ns tCLKL Pulse Duration, CLKA and CLKB LOW 6 – 8 – ns tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 4– 5– n s tENS1 Setup Time, CSA, W/RA before CLKA↑; CSB, W/RB before CLKB↑ 6– 6– n s tENS2 Setup Time, ENA, before CLKA↑; ENB before CLKB↑ 4– 5– n s tENS3 Setup Time, MBA before CLKA↑: MBB before CLKB↑ 4– 5– n s tPGS Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB 4 – 5 – ns before CLKB↑(2 ) tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑(3) 5– 6– n s tFSS Setup Time, FS0/FS1 before RST HIGH 5 – 6 – ns tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 2.5 – 2.5 – ns tENH1 Hold Time, CSA W/RA after CLKA↑; CSB, W/RB after CLKB↑ 2– 2– n s tENH2 Hold Time, ENA, after CLKA↑; ENB after CLKB↑ 2.5 – 2.5 – ns tENH3 Hold Time, MBA after CLKA↑; MBB after CLKB↑ 1– 1– n s tPGH Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB 1 – 1 – ns after CLKB↑(2 ) tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(3) 5– 6– n s tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB 8– 8– n s tSKEW2(4) Skew Time, between CLKA↑ and CLKB↑ For AEA, AEB, AFA, and AFB 14 – 16 – ns NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are avail able by special order. 2. Only applies for a clock edge that does a FIFO read. 3. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween CLKA cycle and CLKB cycle. (Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF Commercial Com’l & Ind’l(1) IDT723612L15 IDT723612L20 Symbol Parameter Min. Max. Min. Max. Unit tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 10 2 12 ns tWFF Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB 21 0 2 1 2 n s tREF Propagation Delay Time, CLKA↑ to EFA and and CLKB↑ to EFB 21 0 2 1 2 n s tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 21 0 2 1 2 n s tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 21 0 2 1 2 n s tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to 1 9 1 12 ns MBF2 LOW or MBF1 HIGH tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3) 31 1 3 1 3 n s tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid 1 11 1 11.5 ns tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 10 3 11 ns tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB 31 1 3 1 2 n s tPOPB(4) Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and 2 11 2 12 ns tPEPE Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to PEFA; W/RB, CSB,1 1 1 1 1 2 n s ENB, MBB, PGB to PEFB tPEPB(4) Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to parity bits ( A8, A17, A26, A35); 3 12 3 13 ns W/RB, CSB, bits (B8, B17, B26, B35) ENB, MBB or PGB to parity tRSF Propagation Delay Time, RST to (AEA, AEB) LOW and (AFA, AFB, MBF1, MBF2)1 1 5 1 2 0 n s HIGH tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH 2 10 2 12 ns to B0-B35 active tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH 1 8 1 9 ns or W/RB LOW to B0-B35 at high impedance. NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are avai lable by special order. 2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3 Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 4. Only applies when reading data from a mail register. (Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL TABLE 3 — PORT-B ENABLE FUNCTION TABLE SIGNAL DESCRIPTIONS RESET The IDT723612 is reset by taking the Reset (RST) input LOW for at least four port-A clock (CLKA) and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW, the Almost- Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-Empty registers (X) with the values selected by the Flag Select (FS0, FS1) inputs. The values that can be loaded into the registers are shown in Table 1. FIFO WRITE/READ OPERATION The state of port-A data A0-A35 outputs is controlled by the port-A Chip Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0- A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table 2). The port-B control signals are identical to those of port A. The state of the port-B data (B0-B35) outputs is controlled by the port-B Chip Select (CSB) and the port-B Write/Read select (W/RB). The B0-B35 outputs are in the high- impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are active when both CSB and W/RB are LOW. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and EFB is HIGH (see Table 3). CSB W/RB ENB MBB CLKB B0-B35 Outputs Port Functions HXXXX I n High-Impedance State None L H L X X In High-Impedance State None LHHL ↑ In High-Impedance State FIFO2 Write LHHH ↑ In High-Impedance State Mail2 Write LLLLX Active, FIFO1 Output Register None LLHL ↑ Active, FIFO1 Output Register FIFO1 read L L L H X Active, Mail1 Register None LLH H ↑ Active, Mail1 Register Mail1 Read (Set MBF1 HIGH) CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Functions HXXXX I n High-Impedance State None L H L X X In High-Impedance State None LHHL ↑ In High-Impedance State FIFO1 Write LHHH ↑ In High-Impedance State Mail1 Write LLLLX Active, FIFO2 Output Register None LLHL ↑ Active, FIFO2 Output Register FIFO2 Read L L L H X Active, Mail2 Register None LLH H ↑ Active, Mail2 Register Mail2 Read (Set MBF2 HIGH) TABLE 2 — PORT-A ENABLE FUNCTION TABLE ALMOST-FULL AND FS1 FS0 RST ALMOST-EMPTY FLAG OFFSET REGISTER (X) HH ↑ 16 HL ↑ 12 LH ↑ 8 LL ↑ 4 TABLE 1 — FLAG PROGRAMMING

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The setup and hold time constraints to the port clocks for the port Chip Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port chip select and write/read select may change states during the setup and hold time window of the cycle. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized by CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY FLAGS (EFA, EFB) The Empty Flag of a FIFO is synchronized to the port clock that reads data from its array. When the Empty Flag is HIGH, new data can be read to the FIFO output register. When the Empty Flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an Empty Flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The Empty Flag of the FIFO is set HIGH by the second LOW-to- HIGH transition of the synchronizing clock, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t SKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle. FULL FLAG (FFA, FFB) The Full Flag of a FIFO is synchronized to the port clock that writes data to its array. When the Full Flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full Flag is LOW and attempted writes to the FIFO are ignored. Synchronized Synchronized to CLKB to CLKA EFB AEB AFA FFA 0L L H H 1 to X H L H H (X+1) to [64–(X+1)] H H H H (64–X) to 63 H H L H

64 H H L L

(X+1) to [64–(X+1)] H H H H (64–X) to 63 H H L H TABLE 4 — FIFO1 FLAG OPERATION TABLE 5 — FIFO2 FLAG OPERATION NOTE: 1. X is the value in the Almost-Empty flag and Almost-Full flag offset register. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a Full Flag monitors a write-pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the Full Flag synchronizing clock. Therefore, a Full Flag is LOW if less than two cycles of the Full Flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full Flag synchroni- zation clock after the read sets the Full Flag HIGH and the data can be written in the following clock cycle. A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t SKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle. ALMOST EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write-pointer comparator that indicates when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An Almost-Empty flag is LOW when the FIFO contains X or less words in memory and is HIGH when the FIFO contains (X+1) or more words. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clocks are required after a FIFO write for the Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchro- nization cycle if it occurs at time t SKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 7 and 8). ALMOST FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO Number of Words in the FIFO1 (1) Number of Words in the FIFO1 (1)

CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL SRAM status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An Almost-Full flag is LOW when the FIFO contains (64-X) or more words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for the Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of words in memory to [64-(X+1)]. An Almost- Full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64- (X+1)]. A second LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchro- nization cycle (see Figure 14 and 15). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0- A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and MBB is HIGH. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When a port's data outputs are active, the data on the bus comes from the FIFO output register when the port Mailbox-select input (MBA, MBB) is LOW and from the mail register when the port mailbox-select input is HIGH. The Mail1 register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and MBB is HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when port-A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. PARITY CHECKING The port-A inputs (A0-A35) and port-B inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a LOW level on the port Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected, and the Parity Error Fags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the Odd/ Even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a LOW level on the corresponding port Parity Error Flag (PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18- A26, and A27-A35 with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. When odd/even parity is selected, a port parity error flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to the bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = HIGH). When a port-A read from the mail2 register with parity generation is selected with W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port- A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port- B reads (PGB = HIGH). When a port-B read from the mail1 register with parity generation is selected with W/RB LOW, CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the port-B parity error flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs. PARITY GENERATION A HIGH level on the port-A Parity Generate select (PGA) or port-B Parity Generate select (PGB) enables the IDT723612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0- A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all thirty-six inputs regardless of the state of the Parity Generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port-A parity generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup and hold time constraints to the port-A Clock (CLKA) and the port-B Parity Generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the port-B Clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port- B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port Write/Read select (W/RA, W/RB) input is LOW, the port mail select (MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, and port Parity Generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register.

Figure 2. Device Reset Loading the X Register with the Value of Eight

1. t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising

CLKA edge and rising CLKB edge is less than t SKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown. Figure 7. EFBEFBEFBEFBEFB Flag Timing and First Data Read when FIFO1 is Empty

1. t SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than t SKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. Figure 8. EFAEFAEFAEFAEFA Flag Timing and First Data Read when FIFO2 is Empty

1. t SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than t SKEW1, then FFA may transition HIGH one CLKA cycle later than shown. Figure 9. FFAFFAFFAFFAFFA Flag Timing and First Available Write when FIFO1 is Full

1. Port-B parity generation off (PGB = LOW).

Figure 15. Timing for Mail1 Register and MBF1MBF1MBF1MBF1MBF1 Flag

Figure 21. Load Circuit and Voltage Waveforms

1. Includes probe and jig capacitance.

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ORDERING INFORMATION

NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. 723612 3136 drw25 64 x 36 x 2 SyncBiFIFO™ XXXXXX Device Type XX X X X Power Speed Package Clock Cycle Time (tCLK) Speed in Nanoseconds Commercial Only Com'l & Ind'l Process/ Temperature Range I(1) BLANK PF PQF L Commercial (0°C to +70°C) Industrial (40°C to +85°C) Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Low Power X G Green DATASHEET DOCUMENT HISTORY 03/05/2002 pgs. 1, 8, 9 and 25. 06/09/2005 pgs. 1, 2, 3 and 25. 02/13/2009 pg. 25. 07/31/2010 PDN# FS-10-04 issued. See IDT.com for PDN specifics. 10/21/2013 Datasheet changed to Obsolete Status.

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