IDT72125_16 IDT | Alldatasheet

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2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2665/1© CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM FEATURES:

  • •••• 25ns parallel port access time, 35ns cycle time
  • •••• 50MHz serial shift frequency
  • •••• Wide x16 organization offering easy expansion
  • •••• Low power consumption (50mA typical)
  • •••• Least/Most Significant Bit first read selected by asserting the FL/DIR pin
  • •••• Four memory status flags: Empty, Full, Half-Full, and Almost- Empty/Almost-Full
  • •••• Dual-Port zero fall-through architecture
  • •••• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
  • •••• Green parts available, see ordering information DESCRIPTION: The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial FIFO. This FIFO features a 16-bit parallel input port and a serial output port with 1,024 word depths, respectively. W 2665 drw01 RESET LOGIC FLAG LOGIC SERIAL OUTPUT LOGIC WRITE POINTER RAM ARRAY 1,024 x 16 READ POINTER D0-15 FF RS EXPANSION LOGIC RSIX RSOX FL/DIR EF HF AEF SOCP SO The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/ tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT’s unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, Full, Half-Full and Almost-Empty/Almost-Full. The Full and Empty flags prevent any FIFO data overflow or underflow conditions. The Half-Full Flag is available in both single and expansion mode configurations. The Almost-Empty/Almost- Full Flag is available only in a single device mode. The IDT72125 is fabricated using submicron CMOS technology.

COMMERCIAL TEMPERATURE RANGE IDT72125 PARALLEL-TO-SERIAL CMOS FIFO 1,024 x 16 PIN CONFIGURATION PIN DESCRIPTIONS PLASTIC THIN DIP (P28, order code: TP) SOIC (SO28, order code: SO) TOP VIEW HF GND RSOX/AEF FL/DIR Vcc SO SOCP W D13 D14 D15 D12 FF EF RSIX D10 D11 RS 2665 drw 02 Symbol Name I/O Description D0–D15 Inputs I Data inputs for 16-bit wide data. RS Reset I When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset. W Write I A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. SOCP Serial Output Clock I A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. FL/DIR First Load/Direction I This is a dual purpose input used in the width and depth expansion configurations. The First Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first device to be loaded with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first. RSIX Read Serial In I In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX Expansion is connected to RSOX (expansion out) of the previous device. SO Serial Output O Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the Direction pin programming. During Expansion the SO pins are tied together. FF Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. EF Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. HF Half-Full Flag O When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to half-full. RSOX/AEF Read Serial O This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF output pin. Out Expansion When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEF is HIGH, the device Almost-Empty, is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a Almost-Full Flag pulse is sent from RSOX to RSIX to coordinate the width, depth or daisy chain expansion. VCC Power Supply Single power supply of 5V. GND Ground Sing le ground of 0V.

IDT72125 PARALLEL-TO-SERIAL CMOS FIFO 1,024 x 16 COMMERCIAL TEMPERATURE RANGE STATUS FLAGS Symbol Description Max Unit VTERM Terminal Voltage with –0.5 to +7.0 V Respect to GND TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA ABSOLUTE MAXIMUM RATINGS(1) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input HIGH Voltage 2 — — V VIL(1) Input LOW Voltage — — 0.8 V TA Operating Temperature 0 — +70 °C RECOMMENDED DC OPERATING CONDITIONS NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. IDT72125 Commercial Symbol Parameter Min. Typ. Max. Unit ILI (1) Input Leakage Current (Any Input) –1 — 1 μA ILO(2) Output Leakage Current –10 — 10 μA VOH Output Logic "1" Voltage IOUT = –2mA(3) 2.4 — — V VOL Output Logic "0" Voltage IOUT = 8mA(4) — — 0.4 V ICC1(5) Active Power Supply Current — 50 100 mA ICC2(5,6,7) Standby Current — 4 8 mA (W = RS = FL/DIR = VIH; SOCP = VIL) ICC3(5,6,7) Power Down Current — 1 6 mA DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0οC to +70οC) Number of Words in FIFO IDT72125 FF AEF HF EF 0H L H L 1–127 H L H H 128–512 H H H H 513–896 H H L H 897–1023 H L L H

1024 L L L H

NOTES: 1. Measurements with 0.4V ≤ V IN ≤ V CC. 2. SOCP = V IL, 0.4 ≤ V OUT ≤ V CC. 3. For SO, I OUT = -4mA. 4. For SO, I OUT = 16mA. 5. Tested with outputs open (I OUT = 0). 7. Measurements are made after reset.

COMMERCIAL TEMPERATURE RANGE IDT72125 PARALLEL-TO-SERIAL CMOS FIFO 1,024 x 16 AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0οC to +70οC) Commercial IDT72125L25 Symbol Parameter Figure Min. Max. Unit tS Parallel Shift Frequency — — 28.5 MHz tSOCP Serial Shift Frequency — — 50 MHz PARALLEL INPUT TIMINGS tWC Write Cycle Time 2 35 — ns tWPW Write Pulse Width 2 25 — ns tWR Write Recovery Time 2 10 — ns tDS Data Set-up Time 2 12 — ns tDH Data Hold Time 2 0 — ns tWEF Write High to EF HIGH 5, 6 — 35 ns tWFF Write Low to FF LOW 4, 7 — 35 ns tWF Write Low to Transitioning HF, AEF 8— 3 5 n s tWPF Write Pulse Width After FF HIGH 7 25 — ns SERIAL OUTPUT TIMINGS tSOCP Serial Clock Cycle Time 3 20 — ns tSOCW Serial Clock Width HIGH/LOW 3 8 — ns tSOPD SOCP Rising Edge to SO Valid Data 3 — 14 ns tSOHZ SOCP Rising Edge to SO at High-Z(1) 33 1 4 n s tSOLZ SOCP Rising Edge to SO at Low-Z(1) 33 1 4 n s tSOCEF SOCP Rising Edge to EF LOW 5, 6 — 35 ns tSOCFF SOCP Rising Edge to FF HIGH 4, 7 — 35 ns tSOCF SOCP Rising Edge to Transitioning HF, AEF 8— 3 5 n s tREFSO SOCP Delay After EF HIGH 6 35 — ns RESET TIMINGS tRSC Reset Cycle Time 1 35 — ns tRS Reset Pulse Width 1 25 — ns tRSS Reset Set-up Time 1 25 — ns tRSR Reset Recovery Time 1 10 — ns EXPANSION MODE TIMINGS tFLS FL Set-up Time to RS Rising Edge 9 7 — ns tFLH FL Hold Time to RS Rising Edge 9 0 — ns tDIRS DIR Set-up Time to SOCP Rising Edge 9 10 — ns tDIRH DIR Hold Time from SOCP Rising Edge 9 5 — ns tSOXD1 SOCP Rising Edge to RSOX Rising Edge 9 — 15 ns tSOXD2 SOCP Rising Edge to RSOX Falling Edge 9 — 15 ns tSIXS RSIX Set-up Time to SOCP Rising Edge 9 5 — ns tSIXPW RSIX Pulse Width 9 10 — ns NOTE: 1. Values guaranteed by design.

  1. Characterized values, not currently tested.
  • Includes scope and jig capacitances.

be programmed to indicate the first device. from incrementing the write pointer and no write operation occurs. Data set-up and hold times must be met with respect to the rising edge of Write. occur simultaneously or asynchronously with read operations. and being clocked out by SOCP. Significant Bit to be read out first.

  1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at t
  2. SOCP should be in the steady LOW or HIGH during t RSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after t RSR.

Figure 1. Reset

  1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half-Full Flag Output, FF = Full Flag Output.

Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com

ORDERING INFORMATION

X Power XX Speed X Package TP SO Plastic Thin DIP (300mil, P28) Small Outline IC (Gull Wing, SOIC, SO28) 25 (50 MHz serial shift rate) L Low Power XXXXX DeviceType 72125 1,024 x 16-Bit Parallel-to-Serial FIFO 2665 drw17 X Process/ Temperature Range BLANK Commercial (0 OC to +70OC) Parallel Access Time (tA) in Nanoseconds Tube or Tray Tape and Reel BLANK X GreenG X DATASHEET DOCUMENT HISTORY 02/10/2016 pgs. 1-11