7207L30PGI8

IDT7203_17 IDT | Alldatasheet

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DSC-2661/19© 2017 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice. NOVEMBER 2017 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9 8,192 x 9, 16,384 x 9 32,768 x 9 and 65,536 x 9 IDT7203 IDT7204 IDT7205 IDT7206 IDT7207 IDT7208 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL, MILITARY AND INDUSTRIAL TEMPERATURE RAN GES LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES:

• •• •• First-In/First-Out Dual-Port memory
• •• •• 2,048 x 9 organization (IDT7203)
• •• •• 4,096 x 9 organization (IDT7204)
• •• •• 8,192 x 9 organization (IDT7205)
• •• •• 16,384 x 9 organization (IDT7206)
• •• •• 32,768 x 9 organization (IDT7207)
• •• •• 65,636 x 9 organization (IDT7208)
• •• •• High-speed: 12ns access time
• •• •• Low power consumption — Active: 660mW (max.) — Power-down: 44mW (max.)
• •• •• Asynchronous and simultaneous read and write
• •• •• Fully expandable in both word depth and width
• •• •• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9
• •• •• Status Flags: Empty, Half-Full, Full
• •• •• Retransmit capability
• •• •• High-performance CMOS technology
• •• •• Military product compliant to MIL-STD-883, Class B
• •• •• Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567 (IDT7203), and 5962-89568 (IDT7204) are listed on this function DESCRIPTION: The IDT7203/7204/7205/7206/7207/7208 are dual-port memory buffers with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the Write (W) and Read (R) pins. The device's 9-bit width provides a bit for a control or parity at the user’s option. It also features a Retransmit (RT) capability that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. They are designed for applications requiring asynchronous and simultaneous read/ writes in multiprocessing, rate buffering and other applications. Military grade product is manufactured in compliance with MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM
• Industrial temperature range (–40 °C to +85 °C) is available (plastic packages only) W WRITE CONTROL READ CONTROLR FLAG LOGIC EXPANSION LOGIC XI WRITE POINTER RAM ARRAY 2,048 x 9 4,096 x 9 8,192 x 9 16,384 x 9 32,768 x 9 65,536 x 9 READ POINTER DATA INPUTS RESET LOGIC THREE- STATE BUFFERS DATA OUTPUTS EF FF XO/HF RS FL/RT 0 (D -D 8 ) 0 (Q -Q 8 ) 2661 drw01
• •• •• Green parts available, see ordering information

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 PIN CONFIGURATIONS Symbol Rating Com'l & Ind'l Military Unit VTERM Terminal –0.5 to +7.0 –0.5 to +7.0 V Voltage with Respect to GND TSTG Storage –55 to + 125 –65 to +155 °C Temperature IOUT DC Output –50 to +50 –50 to +50 mA +Current Reference Order Device Package Type Identifier Code Availability PLASTIC DIP P28-1 P All devices PLASTIC THIN DIP P28-2 T P All except IDT7207/7208 CERDIP D28-1 D All except IDT7208 THIN CERDIP D28-3 T D Only for IDT7203/7204/7205 SOIC SO28-3 SO Only for IDT7204 Reference Order Device Package Type Identifier Code Availability PLCC J32-1 J All devices LCC(1) L32-1 L All ex cept IDT7208 TOP VIEW TOP VIEW NOTE: 1. This package is only available in the military temperature range. NOTES: 1. For RT/RS/XI input, V IH = 2.6V (commercial). For RT/RS/XI input, V IH = 2.6V (military). 2. 1.5V undershoots are allowed for 10ns once per cycle. FF XI GND EF XO/HF Vcc FL/RT RS W R 2661 drw02a Q4Q8 FF XI EF XO/HF NC FL/RT RS INDEX NC W NC Vcc GND NC R 2661 drw02b ABSOLUTE MAXIMUM RATINGS NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V Commercial/Industrial/Military GND Supply Voltage 0 0 0 V VIH(1) Input High Voltage 2.0 — — V Commercial/Industrial VIH(1) Input High Voltage Military 2.2 — — V VIL(2) Input Low Voltage — — 0.8 V Commercial/Industrial/Military TA Operating Temperature Commercial 0 — 70 °C TA Operating Temperature Industrial –40 — 85 °C TA Operating Temperature Military –55 — 125 °C

1. Industrial temperature range product for 15ns and 25ns speed grades are available
2. Industrial temperature range product for 25ns speed grade only is available as a standard

device. All other speed grades are available by special order.

1. Military temperature range product for the 40ns is only available for 7203.
2. Commercial temperature range product for the 12ns not available.
3. Commercial temperature range product for the 12ns, 15ns and 50ns not available.
4. Measurements with 0.4 ≤ V IN ≤ V CC.
5. Tested with outputs open (I OUT = 0).
6. R and W toggle at 20 MHz and data inputs switch at 10 MHz.
7. I CC measurements are made with outputs open.
8. All Inputs = V CC - 0.2V or GND + 0.2V, except R and W, which toggle at 20MHz.
9. This parameter is sampled and not 100% tested.

Figure 1. Output Load *Includes jig and scope capacitances.

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 Commercial Com'l & Ind'l Com'l & Military Commercial Com'l & Ind'l IDT7203L12 IDT7203L15(2) IDT7203L20 IDT7208L20 IDT7203L25(2) IDT7204L12 IDT7204L15(2) IDT7204L20 IDT7204L25(2) IDT7205L12 IDT7205L15(2) IDT7205L20 IDT7205L25(2) IDT7206L15 IDT7206L20 IDT7206L25(3) IDT7207L15 IDT7207L20 IDT7207L25(3) IDT7208L25(3) fS Shift Frequency — 50 — 40 — 33.3 — 33.3 — 28.5 MHz tRC Read Cycle Time 20 — 25 — 30 — 30 — 35 — ns tA Access Time — 12 — 15 — 20 — 20 — 25 ns tRR Read Recovery Time 8 — 10 — 10 — 10 — 10 — ns tRPW Read Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns tRLZ Read LOW to Data Bus LOW(5) 3—5 —5—5—5— n s tWLZ Write HIGH to Data Bus Low-Z(5,6) 3—5 —5—5—5— n s tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — 5 — ns tRHZ Read HIGH to Data Bus High-Z(5) —1 2— 1 5—1 5—1 5—1 8n s tWC Write Cycle Time 20 — 25 — 30 — 30 — 35 — ns tWPW Write Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns tWR Write Recovery Time 8 — 10 — 10 — 10 — 10 — ns tDS Data Set-up Time 9 — 11 — 12 — 12 — 15 — ns tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns tRSC Reset Cycle Time 20 — 25 — 30 — 30 — 35 — ns tRS Reset Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns tRSS Reset Set-up Time(5) 12 — 15 — 20 — 20 — 25 — ns tRTR Reset Recovery Time 8 — 10 — 10 — 10 — 10 — ns tRTC Retransmit Cycle Time 20 — 25 — 30 — 30 — 35 — ns tRT Retransmit Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns tRTS Retransmit Set-up Time(5) 12 — 15 — 20 — 20 — 25 — ns tRTR Retransmit Recovery Time 8 — 10 — 10 — 10 — 10 — ns tEFL Reset to EF LOW —1 2— 2 5—3 0—3 0—3 5n s tHFH, tFFH Reset to HF and FF HIGH — 17 — 25 — 30 — 30 — 35 ns tRTF Retransmit LOW to Flags Valid — 20 — 25 — 30 — 30 — 35 ns tREF Read LOW to EF LOW —1 2— 1 5—2 0—2 0—2 5n s tRFF Read HIGH to FF HIGH — 14 — 15 — 20 — 20 — 25 ns tRPE Read Pulse Width after EF HIGH 12 — 15 — 20 — 20 — 25 — ns tWEF Write HIGH to EF HIGH — 12 — 15 — 20 — 20 — 25 ns tWFF Write LOW to FF LOW —1 4— 1 5—2 0—2 0—2 5n s tWHF Write LOW to HF Flag LOW — 17 — 25 — 30 — 30 — 35 ns tRHF Read HIGH to HF Flag HIGH — 17 — 25 — 30 — 30 — 35 ns tWPF Write Pulse Width after FF HIGH 12 — 15 — 20 — 20 — 25 — ns tXOL Read/Write LOW to XO LOW —1 2— 1 5—2 0—2 0—2 5n s tXOH Read/Write HIGH to XO HIGH — 12 — 15 — 20 — 20 — 25 ns tXI XI Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns tXIR XI Recovery Time 8 — 10 — 10 — 10 — 10 — ns tXIS XI Set-up Time 8 — 10 — 10 — 10 — 10 — ns AC ELECTRICAL CHARACTERISTICS (1) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40 °C to +85°C; Military: VCC = 5V ± 10%, TA = –55 °C to +125°C) NOTES: 1. Timings referenced as in AC Test Conditions. 2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. 3. Industrial temperature range product for 25ns speed grade only is available as a standard device. All other speed grades are available by special order. 4. Pulse widths less than minimum are not allowed. 5. Values guaranteed by design, not currently tested. 6. Only applies to read data flow-through mode.

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 AC ELECTRICAL CHARACTERISTICS (1) (CONTINUED) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40 °C to +85°C; Military: VCC = 5V ± 10%, TA = –55 °C to +125°C) NOTES: 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode. Military Commercial Military Commercial IDT7203L30 IDT7203L35 IDT7203L40 IDT7203L50 IDT7204L30 IDT7204L35 IDT7204L50 IDT7205L30 IDT7205L35 IDT7205L50 IDT7206L30 IDT7206L35 IDT7206L50 IDT7207L30 IDT7207L35 IDT7207L50 IDT7208L35 fS Shift Frequency — 25 — 22.22 — 20 — 15 M H z tRC Read Cycle Time 40 — 45 — 50 — 65 — ns tA Access Time — 30 — 35 — 40 — 50 ns tRR Read Recovery Time 10 — 10 — 10 — 15 — ns tRPW Read Pulse Width(2) 30 — 35 — 40 — 50 — ns tRLZ Read LOW to Data Bus LOW(3) 5— 5 —5— 1 0 — n s tWLZ Write HIGH to Data Bus Low-Z(3,4) 5 — 10 — 10 — 15 — ns tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — ns tRHZ Read HIGH to Data Bus High-Z(3) —2 0 — 2 0—2 5—3 0 n s tWC Write Cycle Time 40 — 45 — 50 — 65 — ns tWPW Write Pulse Width(2) 30 — 35 — 40 — 50 — ns tWR Write Recovery Time 10 — 10 — 10 — 15 — ns tDS Data Set-up Time 18 — 18 — 20 — 30 — ns tDH Data Hold Time 0 — 0 — 0 — 5 — ns tRSC Reset Cycle Time 40 — 45 — 50 — 65 — ns tRS Reset Pulse Width(2) 30 — 35 — 40 — 50 — ns tRSS Reset Set-up Time(3) 30 — 35 — 40 — 50 — ns tRTR Reset Recovery Time 10 — 10 — 10 — 15 — ns tRTC Retransmit Cycle Time 40 — 45 — 50 — 65 — ns tRT Retransmit Pulse Width(2) 30 — 35 — 40 — 50 — ns tRTS Retransmit Set-up Time(3) 30 — 35 — 40 — 50 — ns tRTR Retransmit Recovery Time 10 — 10 — 10 — 15 — ns tEFL Reset to EF LOW —4 0 — 4 5—5 0—6 5 n s tHFH, tFFH Reset to HF and FF HIGH — 40 — 45 — 50 — 65 ns tRTF Retransmit LOW to Flags Valid — 40 — 45 — 50 — 65 ns tREF Read LOW to EF LOW —3 0 — 3 0—3 5—4 5 n s tRFF Read HIGH to FF HIGH — 30 — 30 — 35 — 45 ns tRPE Read Pulse Width after EF HIGH 30 — 35 — 40 — 50 — ns tWEF Write HIGH to EF HIGH — 30 — 30 — 35 — 45 ns tWFF Write LOW to FF LOW —3 0 — 3 0—3 5—4 5 n s tWHF Write LOW to HF Flag LOW — 40 — 45 — 50 — 65 ns tRHF Read HIGH to HF Flag HIGH — 40 — 45 — 50 — 65 ns tWPF Write Pulse Width after FF HIGH 30 — 35 — 40 — 50 — ns tXOL Read/Write LOW to XO LOW —3 0 — 3 5—4 0—5 0 n s tXOH Read/Write HIGH to XO HIGH — 30 — 35 — 40 — 50 ns tXI XI Pulse Width(2) 30 — 35 — 40 — 50 — ns tXIR XI Recovery Time 10 — 10 — 10 — 10 — ns tXIS XI Set-up Time 10 — 15 — 15 — 15 — ns

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 2,048/ 4,096/8,192/16,384/32,768/65,536 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode. EXPANSION IN ( XI ) — This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode. OUTPUTS: FULL FLAG ( FF ) — The Full Flag (FF) will go LOW, inhibiting further write operations, when the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536 writes. EMPTY FLAG ( EF ) — The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG ( XO/HF ) — This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the Write pointer reaches the last location of memory, and an additional XO pulse when the Read pointer reaches the last location of memory. DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data. These outputs are in a high-impedance condition whenever Read (R) is in a HIGH state. SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0–D 8) — Data inputs for 9-bit wide data. CONTROLS: RESET ( RS ) — Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. WRITE ENABLE ( W ) — A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered- to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE ( R ) — A read cycle is initiated on the falling edge of the Read Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high- impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read operations, with the data outputs remaining in a high- impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT ( FL/RT ) — This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device

1. Pointer will Increment if flag is HIGH.
2. XI is connected to XO of previous device. See Figure 14.
3. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output

Figure 14. Block Diagram of 6,144 x 9, 12,288 x 9, 24,576 x 9, 49,152 x 9, 98,304 x 9, 196,608 x 9 FIFO Memory (Depth Expansion)

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com

ORDERING INFORMATION

NOTES: 1. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device for IDT7203/7204/7205, and 25ns speed grade only is available as a standard device for IDT7206/7207/7208. All other speed grades are available by special order. 2. The LCC is only available in the military temperature range. 3. The IDT7208 is only available in commercial speed grades of 20, 25 and 35 ns. 4. Green parts are available. For specific speeds and packages contact your local sales office. LEAD FINISH (SnPb) parts are in EOL proc ess. Product Discontinuation Notice - PDN# SP-17-02 5. For "P", Plastic Dip, when ordering green package, the suffix is "PDG". X Power XX Speed X Package X Process/ Temperature Range Blank Commercial (0°C to +70°C) I(1) B Industrial (− 40° to +85°C) Military (− 55°C to +125°C) Compliant to MIL-STD-883, Class B P(5) TP D TD J L (2) SO Plastic DIP P28-1 Plastic Thin DIP P28-2 (all except 7207/7208) CERDIP D28-1 (all except 7208) Thin CERDIP D28-3 (only for 7203/7204/7205) Plastic Leaded Chip Carrier PLCC J32-1 Leadless Chip Carrier LCC L32-1 (all except 7208) Small Outline IC SOIC SO28-3 (only 7204) (3) 25(3) (3) Commercial 7203/04/05 Only Commercial and (Industrial only 7203/04/05) Commercial and Military Commercial and Industrial Military Only Commercial Only Military 7203 Only Commercial Only XXXX Device Type 7203 ⎯ 7204 ⎯ 7205 ⎯ 7206 ⎯ 7207 ⎯ 7208(3) L Low Power Access Time (tA) Speed in Nanoseconds 2661 drw21 2,048 x9 FIFO 4,096 x 9 FIFO 8,192 x 9 FIFO 16,384 x 9 FIFO 32,768 x 9 FIFO 65,536 x 9 FIFO X G Green(4) X Blank Tube or Tray Tape and Reel DATA SHEET HISTORY 05/10/2001 pgs. 2, 3, 4, 5, 11 and 14. 05/30/2001 pg. 2. 04/03/2006 pgs. 1 and 14. 10/22/2008 pg. 14. 04/22/2010 pgs. 3, 4 and 14. 06/29/2012 pgs. 1 and 14. 11/27/2017 Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018.