7201LA20TP IDT | Alldatasheet

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256 x 9, 512 x 9 and 1,024 x 9 IDT7200L IDT7201LA IDT7202LA IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES ©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-26 79/13 FEATURES:

  • •••• First-In/First-Out dual-port memory
  • •••• 256 x 9 organization (IDT7200)
  • •••• 512 x 9 organization (IDT7201)
  • •••• 1,024 x 9 organization (IDT7202)
  • •••• Low power consumption — Active: 440mW (max.) —Power-down: 28mW (max.)
  • •••• Ultra high speed—12ns access time
  • •••• Asynchronous and simultaneous read and write
  • •••• Fully expandable by both word depth and/or bit width
  • •••• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9
  • •••• Status Flags: Empty, Half-Full, Full
  • •••• Auto-retransmit capability
  • •••• High-performance CEMOS™ technology
  • •••• Military product compliant to MIL-STD-883, Class B
  • •••• Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function
  • •••• Dual versions available in the TSSOP package. For more informa- tion, see IDT7280/7281/7282 data sheet IDT7280 = 2 x IDT7200 IDT7281 = 2 x IDT7201 IDT7282 = 2 x IDT7202 DESCRIPTION: The IDT7200/7201/7202 are dual-port memories that load and empty data on a first-in/first-out basis. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Military grade product is manufactured in compliance with MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM W WRITE CONTROL READ CONTROLR FLAG LOGIC EXPANSION LOGICXI WRITE POINTER RAM ARRAY 256 x 9 512 x 9 1,024 x 9 READ POINTER DATA INPUTS RESET LOGIC THREE- STATE BUFFERS DATA OUTPUTS EF FF XO/HF RS FL/RT (D0-D8) 2679 drw 01 (Q0-Q8)
  • •••• Industrial temperature range (–40oC to +85oC) is available (plastic packages only)
  • •••• Green parts available, see ordering information

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 PIN CONFIGURATIONS RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V Commercial/Industrial/Military GND Supply Voltage 0 0 0 V VIH(1) Input High Voltage Com'l/Ind'l 2.0 — — V VIH(1) Input High Voltage Military 2.2 — — V VIL(2) Input Low Voltage — — 0.8 V Commercial/Industrial/Military TA Operating Temperature Commercial 0 — 70 °C TA Operating Temperature Industrial –40 — 85 °C TA Operating Temperature Military –55 — 125 °C NOTES: 1. For RT/RS/XI input, V IH = 2.6V (commercial). For RT/RS/XI input, V IH = 2.8V (military). 2. 1.5V undershoots are allowed for 10ns once per cycle. ABSOLUTE MAXIMUM RATINGS Symbol Rating Com’l & Ind'l Mil. Unit VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V with Respect to GND T STG Storage –55 to +125 –65 to +155 °C Temperature IOUT DC Output –50 to +50 –50 to +50 mA Current NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Reference Order Package Type Identifier Code PLASTIC DIP (1) P28-1 P PLASTIC THIN DIP P28-2 T P CERDIP(1) D28-1 D THIN CERDIP D28-3 T D SOIC SO28-3 SO TOP VIEW Reference Order Package Type Identifier Code LCC(1) L32- 1 L PLCC J32-1 J TOP VIEW NOTE: 1. The 600-mil-wide DIP (P28-1 and D28-1) and LCC are not available for the IDT7200. W VCC D3 D532 6 D2 D642 5 D1 D752 4 D0 FL/RT62 3 XI RS72 2 FF EF82 1 Q0 XO/HF92 0 Q1 Q710 19 Q2 Q611 18 Q3 Q512 17 Q8 Q413 16 GND R14 15 2679 drw 02a D2 5 D1 6 D0 7 XI 8 FF 9 Q0 10 Q1 11 NC 12 Q2 13 NC FL/RT RS EF XO/HF Q 3 2 1 32 31 30 14 15 16 17 18 19 20 GND NC R W NC VCC D5INDEX 2679 drw 02b

  1. Industrial temperature range product for the 15ns and 25 ns speed grades are available as a standard device.
  2. Military speed grades of 50ns and 80ns are only available for the IDT7201LA.
  3. Measurements with 0.4 ≤ V
  4. Tested with outputs open (I OUT = 0).
  5. Typical I CC1 = 15 + 2*f S + 0.02*CL*fS (in mA) with V CC = 5V, T A = 25 °C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f S/2, CL = capacitive
  6. All Inputs = V CC - 0.2V or GND + 0.2V.
  7. Characterized values, not currently tested.

Figure 1. Output Load

  • Includes scope and jig capacitances.

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 Commercial Com'l & Ind'l(2) Com'l & Mil. Com'l & Ind'l (2) IDT7200L12 IDT7200L15 IDT7200L20 IDT7200L25 IDT7201LA12 IDT7201LA15 IDT7201LA20 IDT7201LA25 IDT7202LA12 IDT7202LA15 IDT7202LA20 IDT7202LA25 t S Shift Frequency — 50 — 40 — 33.3 — 28.5 M H z tRC Read Cycle Time 20 — 25 — 30 — 35 — ns tA Access Time — 12 — 15 — 20 — 25 ns tRR Read Recovery Time 8 — 10 — 10 — 10 — ns tRPW Read Pulse Width(3) 12 — 15 — 20 — 25 — ns tRLZ Read Pulse Low to Data Bus at Low Z(4) 3 —3— 3— 3— n s tWLZ Write Pulse High to Data Bus at Low Z(4,5) 5 —5— 5— 5— n s tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — ns tRHZ Read Pulse High to Data Bus at High Z(4) — 12 — 15 — 15 — 18 ns tWC Write Cycle Time 20 — 25 — 30 — 35 — ns tWPW Write Pulse Width(3) 12 — 15 — 20 — 25 — ns tWR Write Recovery Time 8 — 10 — 10 — 10 — ns tDS Data Set-up Time 9 — 11 — 12 — 15 — ns tDH Data Hold Time 0 — 0 — 0 — 0 — ns tRSC Reset Cycle Time 20 — 25 — 30 — 35 — ns tRS Reset Pulse Width(3) 12 — 15 — 20 — 25 — ns tRSS Reset Set-up Time(4) 12 — 15 — 20 — 25 — ns tRSR Reset Recovery Time 8 — 10 — 10 — 10 — ns tRTC Retransmit Cycle Time 20 — 25 — 30 — 35 — ns tRT Retransmit Pulse Width(3) 12 — 15 — 20 — 25 — ns tRTS Retransmit Set-up Time(4) 12 — 15 — 20 — 25 — ns tRTR Retransmit Recovery Time 8 — 10 — 10 — 10 — ns tEFL Reset to Empty Flag Low — 12 — 25 — 30 — 35 ns tHFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 — 30 — 35 ns tRTF Retransmit Low to Flags Valid — 20 — 25 — 30 — 35 ns tREF Read Low to Empty Flag Low — 12 — 15 — 20 — 25 ns tRFF Read High to Full Flag High — 14 — 15 — 20 — 25 ns tRPE Read Pulse Width after EF High 12 — 15 — 20 — 25 — ns tWEF Write High to Empty Flag High — 12 — 15 — 20 — 25 ns tWFF Write Low to Full Flag Low — 14 — 15 — 20 — 25 ns tWHF Write Low to Half-Full Flag Low — 17 — 25 — 30 — 35 ns tRHF Read High to Half-Full Flag High — 17 — 25 — 30 — 35 ns tWPF Write Pulse Width after FF High 12 — 15 — 20 — 25 — ns tXOL Read/Write to XO Low — 12 — 15 — 20 — 25 ns tXOH Read/Write to XO High — 12 — 15 — 20 — 25 ns tXI XI Pulse Width(3) 12 — 15 — 20 — 25 — ns tXIR XI Recovery Time 8 — 10 — 10 — 10 — ns tXIS XI Set-up Time 8 — 10 — 10 — 10 — ns NOTES: 1. Timings referenced as in AC Test Conditions. 2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 Military Commercial Com'l & Mil.(2) Military(2) IDT7200L30 IDT7200L35 IDT7200L50 IDT7201LA30 IDT7201LA35 IDT7201LA50 IDT7202LA30 IDT7202LA35 IDT7202LA50 IDT7201LA80 t S Shift Frequency — 25 — 22.2 — 15 — 10 M H z tRC Read Cycle Time 40 — 45 — 65 — 100 — ns tA Access Time — 30 — 35 — 50 — 80 ns tRR Read Recovery Time 10 — 10 — 15 — 20 — ns tRPW Read Pulse Width(3) 30 — 35 — 50 — 80 — ns tRLZ Read Pulse Low to Data Bus at Low Z(4) 3—3— 3—3 — n s tWLZ Write Pulse High to Data Bus at Low Z(4, 5) 5—5— 5—5 — n s tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — ns tRHZ Read Pulse High to Data Bus at High Z(4) —2 0—2 0 —3 0— 3 0 n s tWC Write Cycle Time 40 — 45 — 65 — 100 — ns tWPW Write Pulse Width(3) 30 — 35 — 50 — 80 — ns tWR Write Recovery Time 10 — 10 — 15 — 20 — ns tDS Data Set-up Time 18 — 18 — 30 — 40 — ns tDH Data Hold Time 0 — 0 — 5 — 10 — ns tRSC Reset Cycle Time 40 — 45 — 65 — 100 — ns tRS Reset Pulse Width(3) 30 — 35 — 50 — 80 — ns tRSS Reset Set-up Time(4) 30 — 35 — 50 — 80 — ns tRSR Reset Recovery Time 10 — 10 — 15 — 20 — ns tRTC Retransmit Cycle Time 40 — 45 — 65 — 100 — ns tRT Retransmit Pulse Width(3) 30 — 35 — 50 — 80 — ns tRTS Retransmit Set-up Time(4) 30 — 35 — 50 — 80 — ns tRTR Retransmit Recovery Time 10 — 10 — 15 — 20 — ns tEFL Reset to Empty Flag Low — 40 — 45 — 65 — 100 ns tHFH,FFH Reset to Half-Full and Full Flag High — 40 — 45 — 65 — 100 ns tRTF Retransmit Low to Flags Valid — 40 — 45 — 65 — 100 ns tREF Read Low to Empty Flag Low — 30 — 30 — 45 — 60 ns tRFF Read High to Full Flag High — 30 — 30 — 45 — 60 ns tRPE Read Pulse Width after EF High 30 — 35 — 50 — 80 — ns tWEF Write High to Empty Flag High — 30 — 30 — 45 — 60 ns tWFF Write Low to Full Flag Low — 30 — 30 — 45 — 60 ns tWHF Write Low to Half-Full Flag Low — 40 — 45 — 65 — 100 ns tRHF Read High to Half-Full Flag High — 40 — 45 — 65 — 100 ns tWPF Write Pulse Width after FF High 30 — 35 — 50 — 80 — ns tXOL Read/Write to XO L o w —3 0—3 5 —5 0— 8 0 n s tXOH Read/Write to XO High — 30 — 35 — 50 — 80 ns tXI XI Pulse Width(3) 30 — 35 — 50 — 80 — ns tXIR XI Recovery Time 10 — 10 — 10 — 10 — ns tXIS XI Set-up Time 10 — 10 — 15 — 15 — ns AC ELECTRICAL CHARACTERISTICS(1) (Continued) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) NOTES: 1. Timings referenced as in AC Test Conditions 2. Military speed grades of 50ns and 80ns are only available for IDT7201LA. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode.

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). The IDT7200/7201A/7202A can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 256/512/1,024 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 256 writes for IDT7200, 512 writes for the IDT7201A and 1,024 writes for the IDT7202A. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Q 0 – Q8) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a HIGH state. SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0 – D8) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, (i.e., t RSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset (RS). WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after t RFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 – Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after t WEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single

  1. Pointer will increment if flag is HIGH.

Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)

  1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com

ORDERING INFORMATION

X Power X Package X Process/ Temperature Range Blank I B 7200 7201 7202 7280 7281 7282 Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Military (-55oC to +125oC) Compliant to MIL-STD-883, Class B 256 x 9-Bit FIFO 512 x 9-Bit FIFO 1,024 x 9-Bit FIFO 256 x 9-Bit DUAL FIFO 512 x 9-Bit DUAL FIFO 1,024 x 9-Bit DUAL FIFO Commercial Only Commercial and Industrial Commercial and Military Commercial and Industrial Military Only Commercial Only Commercial and (Military only for 7201) Military only for 7201 LA Low Power P TP D TD J SO L Plastic DIP Plastic Thin DIP CERDIP Thin CERDIP Plastic Leaded Chip Carrier SOIC Leadless Chip Carrier Access Time (tA) Speed in Nanoseconds 2679 drw 21 (1) P28-1 P28-2 D28-1 D28-3 J32-1 SO28-3 L32-1 PLCC LCC (7201 & 7202 Only) (7201 & 7202 Only) (7201 & 7202 Only) (2) See 7280/7281/7282 data sheet for details X G(3) Green (4) X Blank Tube or Tray Tape and Reel NOTES: 1. Industrial temperature range product is available for the 15ns and 25ns as a standard product. 2. "A" to be included for IDT7201 and IDT7202 ordering part number. 3. Green parts are available. For specific speeds and packages contact your local sales office. 4. For "P", Plastic Dip, when ordering green package, the suffix is "PDG". DATASHEET DOCUMENT HISTORY 05/02/2001 pgs. 1, 2, 3, 4, 5 and 14. 04/03/2006 pgs. 1 and 14. 10/22/2008 pg. 1. 6/29/2012 pgs. 1 and 14.