71T75602100BG

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Document overview

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Technical content

Features

• 512K x 36, 1M x 18 memory configurations
• Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access)
• ZBT TM Feature - No dead cycles between write and read cycles
• Internally synchronized output buffer enable eliminates the need to control OE
• Single R/ W (READ/WRITE) control pin
• Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
• 4-word burst capability (interleaved or linear)
• Individual byte write ( BW 1 - BW4) control (May tie active)
• Three chip enables for simple depth expansion
• 2.5V power supply (±5%)
• 2.5V I/O Supply (V DDQ)
• Power down controlled by ZZ input
• Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
• Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) IDT71T75602 IDT71T75802 512K x 36, 1M x 18 2.5V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

Description

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Megabit) synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBT TM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71T75602/802 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71T75602/802 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three chip enable pins ( CE 1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed.

6.422 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Definitions(1) NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. Symbol Pin Function I/O Active Description A0-A19 Address Inputs I N/A Synchronous Address inputs. T he address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/ LD is a sync hronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high. R/W Read / Write I N/A R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later . CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. T he effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur . For normal operation, CEN must be sampled low at rising edge of clock. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (when R/W and ADV/ LD are sampled low) the appropriate byte write signal ( BW1-BW4) must be valid. T he byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled high. T he appropriate byte(s) of data are written into the device two cycles later . BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. CE1, CE2 Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE 2 to enable the IDT71T75602/802 (CE1 or CE2 sampled high or CE 2 sampled low) and ADV/ LD low at the rising edge of clock, initiates a deselect cycle. T he ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE 2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered a nd triggered by the rising edge of CLK. LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. OE Output Enable I LOW Asynchronous output enable . OE must be low to read data from the 71T75602/802. Whe n OE is high the I/O pins are in a high-imped ance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low . T MS T est Mode Select I N/A Gives input command for T AP controller . Sampled on rising edge of T DK. T his pin has an internal pullup. TDI Test Data Input I N/A Serial input of registers placed between TDI and TDO. Sampled on ris ing edge of TCK. This pin has an internal pullup. TCK Test Clo ck I N/A Clock input of T AP controller . Each T AP event is clocked. T est inputs are captured on rising edge of T CK, while test outputs are driven from the falling edge of T CK. T his pin has an internal pullup. TDO Test Data Output O N/A Serial output of registers placed between T DI and T DO. T his output is active depending on the state of the T AP controller . TRST JT AG Reset (Optional) IL O W Optional asynchronous JT AG reset. Can be used to reset the T AP controller , but not required. JT AG reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left floating. T his pin has an internal pullup. Only available in BGA package. Z Z Sleep Mode I HIGH Synchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. T his pin has an internal pulldown. VDD Power Supply N/A N/A 2.5V core power supply. VDDQ Power Supply N/A N/A 2.5V I/O Supply. VSS Ground N/A N/A Ground. 5313 tbl 02 Description (cont.) The data bus will tri-state two cycles after the chip is deselected or a write is initiated. The IDT71T75602/802 have an on-chip burst counter. In the burst mode, the IDT71T75602/802 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). The IDT71T75602/802 SRAMs utilize a high-performance 2.5V CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Functional Block Diagram Clk DQ DQ DQ Address A [0:18] Control Logic Address Control DI DO Input Register 5313 drw 01 Clock Data I/O [0:31], I/O P[1:4] D Q Clk Output Register Mux Sel Gate OE CE1, CE2, CE2 R/W CEN ADV/LD BWx LBO 512Kx36 BIT MEMORY ARRAY JTAG TMS TDI TCK TDO TRST(optional) Clk DQ DQ DQ Address A [0:19] Control Logic Address Control DI DO Input Register 5313 drw 01b Clock Data I/O [0:15], I/O P[1:2] D Q Clk Output Register Mux Sel Gate OE CE1, CE2, CE2 R/W CEN ADV/LD BWx LBO 1Mx18 BIT MEMORY ARRAY JTAG TMS TDI TCK TDO TRST(optional)

6.424 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Pin Configuration — 512K x 36 NOTES: 1. Pins 14, 16, and 66 do not have to be connected directly to V DD as long as the input voltage is ≥ VIH. 2. Pins 38, 39 and 43 will be pulled internally to V DD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to V DD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device. Top View

100 TQFP

NOTE: 1. V IL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle. Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.375 2.5 2.625 V VDDQ I/O Supply Voltage 2.375 2.5 2.625 V VSS G r o u n d 000 V VIH Input High Voltage - Inputs 1.7 ____ VDD +0.3 V VIH Input High Voltage - I/O 1.7 ____ VDDQ+0.3 V VIL Input Low Voltage -0.3 (1) ____ 0.7 V 5313 tbl 03 Grade Ambient Temperature(1) VSS VDD VDDQ Commercial 0° C to +70° C OV 2.5V ± 5% 2.5V ± 5% Industrial -40° C to +85° C OV 2.5V ± 5% 2.5V ± 5% 5313 tbl 05 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88 CE1 CE2 BW4 BW3 BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD A18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC / TCK(2,3) NC / TDO(2) NC / TDI(2) NC / TMS(2) LBO A14 A13 A12 A11 A10 VDD VSS I/O31 I/O30 VDDQ VSS I/O29 I/O28 I/O27 I/O26 VSS VDDQ I/O25 I/O24 VSS VDD I/O23 I/O22 VDDQ VSS I/O21 I/O20 I/O19 I/O18 VSS VDDQ I/O17 I/O16 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VDD I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 5313 drw 02 VDD(1) I/O15 I/OP3 VDD(1) I/OP4 A15 A16 I/OP1 VDD(1) I/OP2 ZZ A17 NOTE: 1. During production testing, the case temperature equals the ambient temperature.

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1)Pin Configuration — 1Mx 18 100-Pin TQFP Capacitance (TA = +25°C, f = 1.0MHz) NOTES: 1. Pins 14, 16, and 66 do not have to be connected directly to V DD as long as the input voltage is ≥ VIH. 2. Pins 38, 39 and 43 will be pulled internally to V DD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to V DD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device. Top View NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V DD terminals only. 3. V DDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp up. 7. During production testing, the case temperature equals T A. NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. Symbol Rating Commercial Industrial Unit VTE RM(2) T erminal Voltage with Respect to GND -0.5 to +3.6 -0.5 to +3.6 V VTE RM(3,6) T erminal Voltage with Respect to GND -0.5 to V DD -0.5 to V DD V VTE RM(4,6) T erminal Voltage with Respect to GND -0.5 to V DD +0.5 -0.5 to V DD +0.5 V VTE RM(5,6) T erminal Voltage with Respect to GND -0.5 to V DDQ +0.5 -0.5 to V DDQ +0.5 V TA(7) Operating Ambient T emperature 0 to +70 -40 to +85 oC TBIAS Temperature Under Bias -55 to +125 -55 to +125 oC TST G Storage Temperature -55 to +125 -55 to +125 oC PT Power Dissipation 2.0 2.0 W IOUT DC Output Current 50 50 mA 5313 tbl 06 Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance V IN = 3dV 5 pF CI/O I/O Capacitance V OUT = 3dV 7 pF 5313 tbl 07 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88 CE1 CE2 NC NC BW2 BW1 CE2 VDD VSS CLK R/W CEN OE ADV/LD A19 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO A15 A14 A13 A12 A11 VDD VSS NC NC VDDQ VSS NC I/OP2 I/O15 I/O14 VSS VDDQ I/O13 I/O12 VSS VDD I/O11 I/O10 VDDQ VSS I/O9 I/O8 NC NC VSS VDDQ NC NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS VDD I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC 5313 drw 02a VDD(1) NC NC VDD(1) NC A16 A17 NC VDD(1) A10 ZZ A18 NC / TCK(2,3) NC / TDO(2) NC / TDI(2) NC / TMS(2) Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance V IN = 3dV 7 pF CI/O I/O Capacitance V OUT = 3dV 7 pF 5313 tbl 07a Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance V IN = 3dV 7 pF CI/O I/O Capacitance V OUT = 3dV 7 pF 5313 tbl 07b 165 fBGA Capacitance (TA = +25°C, f = 1.0MHz)

119 BGA Capacitance

(TA = +25°C, f = 1.0MHz)

6.426 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. J3, R5, and J5 do not have to be directly connected to V DD as long as the input voltage is ≥ VIH. 2. U2, U3, U4 and U6 will be pulled internally to V DD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3, U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 3. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device). 4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to V DD. Top View Pin Configuration — 1M X 18, 119 BGA (1,2) Top View Pin Configuration — 512K X 36, 119 BGA (1,2) 12345 6 7 AV DDQ A6 A4 A18 A8 A16 VDDQ BN C C E 2 A3 ADV/LD A9 CE2 NC CN C A 7 A2 VDD A12 A15 NC DI / O 16 I/OP3 VSS NC V SS I/OP2 I/O15 EI / O 17 I/O18 VSS CE1 VSS I/O13 I/O14 FV DDQ I/O19 VSS OE VSS I/O12 VDDQ GI / O 20 I/O21 BW3 A17 BW2 I/O11 I/O10 HI / O 22 I/O23 VSS R/W VSS I/O9 I/O8 JV DDQ VDD VDD(1) VDD VDD(1) VDD VDDQ KI / O 24 I/O26 VSS CLK V SS I/O6 I/O7 LI / O 25 I/O27 BW4 NC BW1 I/O4 I/O5 MV DDQ I/O28 VSS CEN VSS I/O3 VDDQ NI / O 29 I/O30 VSS A1 VSS I/O2 I/O1 PI / O 31 I/OP4 VSS A0 VSS I/OP1 I/O0 RN C A 5 LBO VDD VDD(1) A13 NC TN C N C A 10 A11 A14 NC(3) ZZ UV DDQ NC/TMS(2) NC/TDI(2) NC/TCK(2) NC/TDO(2) NC/TRST(2, 4) VDDQ 5313 tbl 2 5 1234567 AV DDQ A6 A4 A19 A8 A16 VDDQ BN C C E 2 A3 ADV/LD A9 CE2 NC CN C A 7 A2 VDD A13 A17 NC DI / O 8 NC V SS NC V SS I/OP1 NC EN C I / O 9 VSS CE1 VSS NC I/O 7 FV DDQ NC V SS OE VSS I/O6 VDDQ GN C I / O 10 BW2 A18 VSS NC I/O 5 HI / O 11 NC V SS R/W VSS I/O4 NC JV DDQ VDD VDD(1) VDD VDD(1) VDD VDDQ KN C I / O 12 VSS CLK V SS NC I/O 3 LI / O 13 NC V SS NC BW1 I/O2 NC MV DDQ I/O14 VSS CEN VSS NC V DDQ NI / O 15 NC V SS A1 VSS I/O1 NC PN C I / O P2 VSS A0 VSS NC I/O 0 RN C A 5 LBO VDD VDD(1) A12 NC TN C A 10 A15 NC(3) A14 A11 ZZ UV DDQ NC/TMS(2) NC/TDI(2) NC/TCK(2) NC/TDO(2) NC/TRST(2 , 4) VDDQ 53 13 tb l 2 5a

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table(1) Partial Truth Table for Writes(1) NOTES: 1. L = V IL, H = VIH, X = Don’t Care. 2. When ADV/ LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either ( CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all th e internal registers and the I/Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false. 6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. 7. Q - Data read from the device, D - data written to the device. NOTES: 1. L = V IL, H = VIH, X = Don’t Care. 2. Multiple bytes may be selected during the same cycle. 3. N/A for X18 configuration. CEN R/W Chip(5) Enable ADV/LD BWx ADDRESS USED PREVIOUS CYCLE CURRENT CYCLE I/O (2 cycles later) L L Select L Valid External X LOAD WRITE D (7) L H Select L X External X LOAD READ Q (7) L X X H Valid Internal LOAD WRITE / BURST WRITE BURST WRITE (Advance burst counter) (2) D(7) L X X H X Internal LOAD READ / BURST READ BURST READ (Advance burst counter) (2) Q(7) L X Deselect L X X X DESELECT or STOP (3) HiZ L X X H X X DESELECT / NOOP NOOP HiZ H X X X X X X SUSPEND (4) Previous Value 5313 tbl 08 OPERATION R/ W BW1 BW2 BW3(3) BW4(3) READ H X X X X W R I T E A L L B Y T E S LLLLL WRITE BYTE 1 (I/O[0:7], I/O P1)(2) L LHHH WRITE BYTE 2 (I/O[8:15], I/OP2)(2) LHLHH WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3) LHHLH WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3) LHHHL N O W R I T E LHHHH 5313 tbl 09

6.428 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Linear Burst Sequence Table (LBO=VSS) Interleaved Burst Sequence Table (LBO=VDD) Functional Timing Diagram(1) NOTES: 1. This assumes CEN, CE1, CE2, CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Da ta_Out is valid after a clock-to-data delay from the rising edge of clock. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 F i r s t A d d r e s s 00011011 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 11100100 5313 tbl 10 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 F i r s t A d d r e s s 00011011 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 11000110 5313 tbl 11 n+29 A29 C29 D/Q27 ADDRESS(2) (A0 - A18) CONTROL(2) (R/W, ADV/LD, BWx) DATA(2) CYCLE CLOCK n+30 A30 C30 D/Q28 n+31 A31 C31 D/Q29 n+32 A32 C32 D/Q30 n+33 A33 C33 D/Q31 n+34 A34 C34 D/Q32 n+35 A35 C35 D/Q33 n+36 A36 C36 D/Q34 n+37 A37 C37 D/Q35 5313drw 03

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Read Operation(1) Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2) NOTES: 1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 2. H = High; L = Low; X = Don’t Care; Z = High Impedance. Cycle Address R/ W ADV/LD CE(1) CEN BW x OE I/O Comments nA 0 HL L L X X X L o a d r e a d n+1 X X H X L X X X Burst read n+2 A 1 HL L L X L Q 0 Load read n+3 X X L H L X L Q 0+1 Deselect or STOP n + 4 X X H XLXL Q 1 NOOP n+5 A 2 HL L L X X Z L o a d r e a d n+6 X X H X L X X Z Burst read n+7 X X L H L X L Q

2 Deselect or STOP

n+8 A 3 L L LLLL Q 2+1 Load write n+9 X X H X L L X Z Burst write n+10 A 4 L L LLLX D 3 Load write n+11 X X L H L X X D 3+1 Deselect or STOP n+12 X X H X L X X D 4 NOOP n+13 A 5 L L LLLXZ L o a d w r i t e n+14 A 6 HL L L X X Z L o a d r e a d n+15 A 7 L L LLLX D 5 Load write n+16 X X H X L L L Q 6 Burst write n+17 A 8 HL L L X X D 7 Load read n+18 X X H X L X X D 7+1 Burst read n+19 A 9 L L LLLL Q 8 Load write 5313 tbl 12 Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments nA 0 H L L L X X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n + 2 X X X XXXL Q 0 Contents of Address A 0 Read Out 5313 tbl 13

6.4210 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Burst Write Operation(1) Burst Read Operation(1) Write Operation(1) NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments nA 0 H L L L X X X Address and Control meet setup n+1 X X H X L X X X Clock Setup Valid, Advance Counter n+2 X X H X L X L Q 0 Address A 0 Read Out , I nc. C ount n+3 X X H X L X L Q 0+1 Address A 0+1 Read Out , I nc. C ount n+4 X X H X L X L Q 0+2 Address A 0+2 Read Out, Inc. Count n+5 A 1 HL L L X L Q 0+3 Address A 0+3 Read Out, Load A 1 n+6 X X H X L X L Q 0 Address A 0 Read Out , I nc. C ount n+7 X X H X L X L Q 1 Address A 1 Read Out, Inc. Count n+8 A 2 HL L L X L Q 1+1 Address A 1+1 Read Out, Load A 2 5313 tbl 14 Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments nA 0 L L L L L X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n+2 X X X X L X X D 0 Write to Address A 0 5313 tbl 15 Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments nA 0 L L L L L X X Address and Control meet setup n+1 X X H X L L X X Clock Setup Valid, Inc. Count n+2 X X H X L L X D 0 Address A 0 Writ e, I nc. Count n+3 X X H X L L X D 0+1 Address A 0+1 Writ e, I nc. C ount n+4 X X H X L L X D 0+2 Address A 0+2 Writ e, I nc. C ount n+5 A 1 L L LLLX D 0+3 Address A 0+3 Write, Load A 1 n+6 X X H X L L X D 0 Address A 0 Writ e, I nc. Count n+7 X X H X L L X D 1 Address A 1 Write, Inc. Count n+8 A 2 L L LLLX D 1+1 Address A 1+1 Write, Load A 2 5313 tbl 16

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used(1) Write Operation with Clock Enable Used(1) NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments nA 0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A 1 H L L L X X X Clock Valid n+3 X X X X H X L Q 0 Clock Ignored. Data Q 0 is on the bus. n+4 X X X X H X L Q 0 Clock Ignored. Data Q 0 is on the bus. n+5 A 2 HL L L X L Q 0 Address A 0 Read out (bus trans.) n+6 A 3 HL L L X L Q 1 Address A 1 Read out (bus trans.) n+7 A 4 HL L L X L Q 2 Address A 2 Read out (bus trans.) 5313 tbl 17 Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments nA 0 L L L L L X X Address and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A 1 L L LLLXX C l o c k V a l i d . n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A

2 L L LLLX D 0 Write Data D0

n+6 A 3 L L LLLX D 1 Write Data D1 n+7 A 4 L L LLLX D 2 Write Data D2 5313 tbl 18

6.4212 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. Read Operation with Chip Enable Used(1) Write Operation with Chip Enable Used(1) NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE 1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O(3) Comments n X X L H L X X ? Deselected. n+1 X X L H L X X ? Deselected. n+2 A 0 H L L L X X Z Address and Control meet setup. n+3 X X L H L X X Z Deselected or STOP . n+4 A 1 HL L L X L Q 0 Address A 0 Read out. Load A 1. n+5 X X L H L X X Z Deselected or STOP . n+6 X X L H L X L Q 1 Address A 1 Read out. Deselected. n+7 A 2 H L L L X X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STOP . n+9 X X L H L X L Q 2 Address A 2 Read out. Deselected. 5313 tbl 19 Cycle Address R/ W ADV/LD CE(2) CEN BW x OE I/O Comments n X X L H L X X ? Deselected. n+1 X X L H L X X ? Deselected. n+2 A 0 L L L L L X Z Address and Control meet setup. n+3 X X L H L X X Z Deselected or STOP . n+4 A 1 L L LLLX D 0 Address D 0 Write in. Load A 1. n+5 X X L H L X X Z Deselected or STOP . n+6 X X L H L X X D 1 Address D 1 Write in. Deselected. n+7 A 2 L L L L L X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STOP . n+9 X X L H L X X D 2 Address D 2 Write in. Deselected. 5313 tbl 20

6.4214 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Temperature Ranges) NOTES: 1. tF = 1/t CYC. 2. Measured as HIGH above 0.6V DDQ and LOW below 0.4VDDQ. 3. Transition is measured ±200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 5. To avoid bus contention, the output buffers are designed such that t CHZ (device turn-off) is faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than t CHZ, which is a Max. parameter (worse case at 70 deg. C, 2.375V). 200MHz 166MHz 150MHz 133MHz 100MHz Output Parameters Set Up Times Hold Times 5313 tbl 24

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle(1,2,3,4) NOTES: 1. Q (A 1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/ LD LOW. 4. R/ W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. ADV/LD (CEN high, eliminates current L-H clock edge) tCD tHADV Pipeline Read (Burst Wraps around to initial state)tCDCtCLZ tCHZtCD tCDC R/W CLK CEN ADDRESS OE DATAOUT tHE tSE A1 A2 tCH tCL tCYC tSADV tHW tSW tHA tSA tHC tSC Burst Pipeline ReadPipeline Read BW1 - BW4 5313 drw 06 CE1, CE2 (2) Q(A2+3) Q(A2)Q(A2+2)Q(A2+2)Q(A2+1)Q(A2)Q(A1)

6.4216 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. D (A 1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE 2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/ LD LOW. 4. R/ W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals ( BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. Timing Waveform of Write Cycles(1,2,3,4,5) tHE tSE R/W A1 A2 CLK CEN ADV/LD ADDRESS OE DATAIN tHDtSD tCH tCL tCYC tHADV tSADV tHW tSW tHA tSA tHC tSC Burst Pipeline Write Pipeline Write Pipeline Write tHB tSB (Burst Wraps around to initial state) tHDtSD(CEN high, eliminates current L-H clock edge) (2) D(A2+2) D(A2+3)D(A1) D(A2) D(A2) 5313 drw 07 BW1 - BW4 CE1, CE2 D(A2+1)

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. Q (A 1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE 2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals ( BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. Timing Waveform of Combined Read and Write Cycles(1,2,3) tHE tSE R/W A1 A2 CLK CEN ADV/LD ADDRESS CE1, CE2(2) BW1 - BW4 DATAOUT Q(A3)Q(A1) Q(A6) Q(A7) tCD Read tCHZ 5313 drw 08 Write tCLZ D(A2) D(A4) tCDC D(A5) Write tCH tCL tCYC tHW tSW tHA tSA A4A3 tHC tSC tSD tHD tHADV tSADV A6 A7 A8A5 A9 DATAIN tHB tSB OE ReadRead

6.4218 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. Q (A 1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals ( BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. Timing Waveform of CEN Operation(1,2,3,4) tHE tSE R/W A1 A2 CLK CEN ADV/LD ADDRESS BW1 - BW4 OE DATAOUT Q(A3) tCD tCLZ tCHZ tCH tCL tCYC tHC tSC D(A2) tSD tHD tCDC A4 A5 tHADV tSADV tHW tSW tHA tSA tHB tSB DATAIN Q(A1) 5313 drw 09 Q(A1) B(A2) CE1, CE2(2)

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of CS Operation(1,2,3,4) NOTES: 1. Q (A 1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3. 2C E 2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals ( BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. R/W CLK ADV/LD ADDRESS OE DATAOUT Q(A1) tCD tCLZ tCHZ tCDC tCH tCL tCYC tHC tSC tSD tHD A5A3 tSB DATAIN tHE tSE tHA tSA tHW tSW tHB CEN tHADVtSADV 5313 drw 10 Q(A2) Q(A4) D(A3) BW1 - BW4 CE1, CE2 (2)

6.4220 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges JTAG Interface Specification TCK Device Inputs(1)/ TDI/TMS Device Outputs(2)/ TDO TRST(3) tJCD tJDC tJRST tJS tJH tJCYC tJRSR tJF tJCL tJR tJCH M5313 drw 01 x Symbol Parameter Min. Max. Units tJC YC JT AG Clock Input Period 100 ____ ns tJCH JT AG Clock HIGH 40 ____ ns tJCL JT AG Clock Low 40 ____ ns tJR JT AG Clock Rise Time ____ 5(1) ns tJF JT AG Clock Fall Time ____ 5(1) ns tJRST JT AG Reset 50 ____ ns tJR SR JT AG Reset Recovery 50 ____ ns tJCD JT AG Data Output ____ 20 ns tJDC JTAG Data Output Hold 0 ____ ns tJS JT AG Setup 25 ____ ns tJH JT AG Hold 25 ____ ns I5313 tbl 01 Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 JTAG Identification (JIDR) 32 Boundary Scan (BSR) Note (1) I5313 tbl 03 NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. 3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. NOTE: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available by contacting your local IDT sales representative. Characteristics(1,2,3,4) Scan Register Sizes NOTES: 1. Guaranteed by design. 2. AC Test Load (Fig. 1) on external output signals. 3. Refer to AC Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. Instruction Field Value Description Revision Number (31:28) 0x2 Reserved for version number . IDT Device ID (27:12) 0x220, 0x222 Define s IDT part number 71T75602 and 71T75802, respectively. IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT. ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register . I5313 tbl 02 JTAG Identification Register Definitions Instruction Description OPCODE EXTEST Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. 0000 SAMPLE/PRELOAD Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. 0001 DEVICE_ID Loads the JT AG ID register (JIDR) with the vendor ID code and places the register between TDI and TDO. 0010 HIGHZ Places the bypass register (BYR) between T DI and TDO. Forces all device output drivers to a High-Z state. 0011 RESERVED Several combinations are reserved. Do not use codes other than those identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, VALIDATE and BYPASS instructions. 0100 RESERVED 0101 RESERVED 0110 RESERVED 0111 CLAMP Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. 1000 RESERVED Same as above. 1001 RESERVED 1010 RESERVED 1011 RESERVED 1100 VALIDATE Automatically loaded into the instruction register whenever the T AP controller passes through the CAPTURE-IR state. The lower two bits '01' are mand ated by the IEEE std. 1149.1 specification. 1101 RESERVED Same as above. 1110 BYPASS The BYPASS instruction is used to truncate the boundary scan register as a single bit in length. 1111 I5313 tbl 04 Available JTAG Instructions

6.4222 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of OE Operation(1) NOTE: 1. A read operation is assumed to be in progress.

Ordering Information

100-Pin Plastic Thin Quad Flatpack (TQFP) TQFP - Green

119 Ball Grid Array (BGA)

S Power XX Speed XX Package XXXX *200 166 150 133 100 Clock Frequency in Megahertz 5313 drw 12 Device Type 71T75602 71T75802 512Kx36 Pipelined ZBT SRAM 1Mx18 Pipelined ZBT SRAM PF PFG BG BGG X Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Blank Tube or Tray Tape and Reel X * 200MHz available Only for IDT71T75802

6.42 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History Rev Date Pages Description 0 04/20/00 Created New Datasheet 1 05/25/00 Pg.1,14,15,25 Added 166MHz speed grade offering Pg. 1,2,14 Corrected error in ZZ Sleep Mode Pg. 23 AddBQ165 Package Diagram Outline Pg. 24 Corrected 119BGA Package Diagram Outline. Pg. 25 Corrected topmark on ordering information 2 08/23/01 Pg. 1,2,24 Removed reference of BQ165 Package Pg. 7 Removed page of the 165 BGA pin configuration Pg. 23 Removed page of the 165 BGA package diagram outline 3 10/16/01 Pg. 6 Corrected 3.3V to 2.5V in Note 2 10/29/01 Pg. 13 Improved DC Electrical characteristics-parameters improved: Icc, ISB2, ISB3, IZZ. 4 12/21/01 Pg. 4-6 Added clarification to JTAG pins, allow for NC. Added 36M address pin locations. Pg. 14 Revised 166MHz t CDC(min), tCLZ(min) and tCHZ(min) to 1.0ns 5 06/07/02 Pg. 1-3,6,13,20,21 Added complete JTAG functionality. Pg. 2,13 Added notes for ZZ pin internal pulldown and ZZ leakage current. Pg. 13,14,24 Added 200MHz and 225MHz to DC and AC Electrical Characteristics. Updated supply current for Idd, ISB1, ISB3 and Izz. 6 11/19/02 Pg.1-24 Changed datasheet from Advanced Information to final release. Pg.13 Updated DC Electrical characteristics temperature and voltage range table. 7 05/23/03 Pg.4,5,13,14,24 Added I-temp to the datasheet. Pg.5 Updated 165 BGA Capacitance table. 8 04/01/04 Pg. 1 Updated logo with new design. Pg. 4,5 Clarified ambient and case operating temperatures. Pg. 6 Updated pin I/O number order for the 119 BGA. Pg. 23 Updated 119BGA Package Diagram Drawing. 9 10/01/08 Pg. 1,13,14,24 Deleted 225MHz part, added 200MHz Industrial grade and added green packages. Updated the ordering information by removing the “IDT” notation. 10 04/04/12 Pg. 2,22 Updated text on Page 2 last paragraph. Added Note to ordering information and updated to include tube or tray and tape & reel. The IDT logo is a registered trademark of Integrated Device Technology, Inc. All brands or products are the trademarks or regi stered trademarks of their respective owners. ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Techn ology and Motorola Inc. CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com San Jose, CA 95138 fax: 408-284-2775 408-284-4532 www.idt.com