71M6515H

Teridian Semiconductor ...

Energy Meter IC

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Page: 1 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 GENERAL DESCRIPTION The 71M6515H is a high-accuracy analog front end (AFE) IC that provides measurements for four- quadrant 3-phase metering. The combination of a 21-bit sigma-delta A/D converter with a six-input analog front end, a thermally compensated high pre- cision reference and a compute engine results in high accuracy and wide dynamic range. Patented Single-Converter Technology ™ reduces cross talk and cost. This IC also provides RTC and battery backup for time-of-use (TOU) metering. HOST PRO- CESSOR CURRENT VOLTAGE SSI UART, IRQZ VOLTAGE REFERENCE COMPUTE ENGINE RTC Battery RAM TERIDIAN 71M6515H DIO CONTROL Figure 1: Meter block diagram As shown in the block diagram ( Figure 1), the host processor communicates with the 71M6515H through a UART interface using the programmable IRQZ interrupt. The 71M6515H calculates and accu- mulates meter measurements for each accumulation interval. A high-speed synchronous serial port (SSI) is provided to facilitate high-end metering. Integrated rectifying functions on the battery backup circuit enable minimal external component usage and minimum back-up current. Also, eight multi-purpose pins are provided for control of peripherals.

FEATURES

< 0.1% Wh accuracy over temperature and 2000:1 range
Exceeds IEC62053/ANSIC 12.20 specifications.
Precision ultra-stable voltage reference (10PPM/°C)
Single Converter Technology™ reduces cross talk and power consumption
Six sensor inputs—referenced to V3P3
Compatible with CTs, resistive shunts and Rogowski Coil sensors
-90dB THD max.
Digital temperature compensation
Sag detection
Measures Wh, VARh, VAh, Vrms, Irms, V-to-V phase and load angle on each phase
Four-quadrant metering.
Four low-jitter pulse outputs from selectable measurements
Four pulse count registers
Selectable default status for pulse pins
Same calibration data for 46Hz to 64Hz line frequency
Broad CT phase compensation (±7deg) Battery Backup
Protects accumulated data and powers real time clock during power supply outage
Compatible with Li-ion, NiCd, or super-capacitor
Battery backup current 2µA typical at 25°C External Data Interface
UART Control Interface, two selectable data rates
8 general-purpose I/O pins with alarm capability
5 or 10MHz selectable high speed synchronous serial output for DSP interface
IRQ output signal for alarms and end of measure- ment intervals.
Alarms on voltage sag, ov er-voltage, over-current Low System Cost
Power Consumption 30mW @ 3.3V typical
Real-time clock with temperature compensation
Built-in power fault detection
Single 32kHz crystal time base
Single-supply operation (3.3V)
64-lead LQFP package

64 PINS -- 64 TQFP

2.5V to logic V2P5 TMUXOUT TEST GNDA IC TEMP March 3, 2008 CK_GEN VREF VC VX GNDA GNDD V3P3A GNDD V3P3 XIN XOUT OSC (32KHz) CKTEST SYSTEM CLOCKS RTC DATA RAM BATTERY BACKUP SSCLK SSDATA SFR SRDY SSI INTERFACE MUXSYNC CALCULATIONS OUTPUT VALUES: ALARMS: Whr (A, B, C) VARhr (A, B, C) VAhr (A, B, C) Vrms (A, B, C) Irms (A, B, C) Iphase (A, B, C) Frequency (Selected Phase) Temperature Voltage Sag (A, B, C) Zero Cross (Selected Phase) Over-Voltage (All) Over-Current (All) D0-D7 State Change CONTROL PULSEW PULSER VBIAS (1.5V) VBIAS (1.5V) RESERVED IRQZ I/O CONTROL Change of State (D0...D7) GNDD PULSE4 PULSE3 PULSE_INIT BAUDRATE MISC Figure 2: IC Functional Block Diagram

Page: 3 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3D, V3P3A −0.5V to 4.6V |V3P3D – V3P3A| 0V to 0.5V VBAT -0.5V to 4.6V GNDD -0.5V to +0.5V Analog Output Pins: VREF -1mA to 1mA, -0.5V to V3P3A+0.5V V2P5 -1mA to 1mA, -0.5 to 3.0V Analog Input Pins: IA, VA, IB, VB, IC, VC -0.5V to V3P3A+1.0V VFLT, VX -0.5V to V3P3A+0.5V XIN, XOUT -0.5V to 3.0V Digital Input Pins: RX -0.5V to 3.6V D0…D7 -0.5V to 6V All other pins -0.5V to V3P3D+0.5V Operating junction temperature (peak, 100ms) 140 °C Operating junction temperature (continuous) 125 °C Storage temperature −45 °C to 165 °C Solder temperature – 10 second duration 250 °C ESD Stress Pins IA, VA, IB, VB, IC, VC, RX, TX 6kV All other pins 2kV Stresses beyond Absolute Maximum Ratings may cause permanent dam age to the device. These are stress ratings only and functional operation at these or any other conditi ons beyond those indicated under “recommended oper ating conditions” is not implied. Expo sure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. RECOMMENDED OPERATING CONDITIONS PARAMETER CONDITION MIN TYP MAX UNIT 3.3V Supply Voltage (V3P3A, V3P3D)+ Normal Operation 3.0 3.3 3.6 V Battery Backup 0 3.8 V VBAT No Battery Externally Connect to V3P3D Battery Backup 2.0 3.8 V Operating Temperature -40 85 ºC + V3P3A and V3P3D should be shorted together on the circuit board. GNDD and GNDA should also be shorted on the circuit board.

Page: 4 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 LOGIC LEVELS PARAMETER CONDITION MIN TYP MAX UNIT Digital high-level input voltage, VIH 2 V3P3D V Digital low-level input voltage, VIL −0.3 0.8 V Digital high-level output voltage VOH ILOAD = 1mA V3P3D –0.4 V3P3D V ILOAD = 15mA V3P3D- 0.6 V Digital low-level output voltage VOL ILOAD = 1mA 0 0.4 V ILOAD = 15mA 0.8 V Input pull-up current, IIL RESETZ E_RXTX, E_ISYNC/BRKRQ E_RST Other digital inputs VIN=0V 100 100 100 µA µA µA µA Input pull down current, IIH TEST Other digital inputs VIN=V3P3D 100 µA µA SUPPLY CURRENT PARAMETER CONDITION MIN TYP MAX UNIT V3P3A + V3P3D Normal Operation, V3P3A=V3P3D=3.3V VBAT=3.6V 8.8 11.5 mA V3P3A current 3.7 4.7 mA V3P3D current 5.1 6.8 mA VBAT current -300 300 nA VBAT current, VBAT=3.6V Battery backup, ≤25°C V3P3A=V3P3D=0V f OSC = 32kHz 85°C 2 4 µA 4 12 µA VREF PARAMETER CONDITION MIN TYP MAX UNIT VREF output voltage, VNOM(25) Ta = 25ºC 1.193 1.195 1.197 V VREF output impedance ILOAD = 10µA, -10µA 2.5 kΩ VNOM definition A VNOM(T) = VREF(22) + (T-22)TC1 + (T-22)2TC2 V VREF(T) deviation from VNOM(T) ) 40 |, 22 max(| 10) ( ) ( 6 TVNOM T VNOM T VREF Ta = -40ºC to +85ºC -10 +10 PPM/ºC VREF aging ±25 PPM/year

Page: 5 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 2.5V VOLTAGE REGULATOR PARAMETER CONDITION MIN TYP MAX UNIT Voltage Overhead V3P3D-V2P5 Reduce V3P3 until V2P5 drops 200mV 440 mV PSRR ΔV2P5/ΔV3P3D RESETZ =1, ILOAD=0 -3 +3 mV/V RTC PARAMETER CONDITION MIN TYP MAX UNIT Range for date 2000 -- 2255 year RESETZ PARAMETER CONDITION MIN TYP MAX UNIT Reset pulse width 5 µs Reset pulse fall time 1 µs CRYSTAL OSCILLATOR PARAMETER CONDITION MIN TYP MAX UNIT Maximum Output Power to Crystal4 1 µW Xin to Xout Capacitance 3 pF Capacitance to DGND Xin Xout pF pF Watchdog RTC_OK threshold 25 kHz TEMPERATURE SENSOR PARAMETER CONDITION MIN TYP MAX UNIT Nominal Sensitivity (Sn)4 TA=25ºC, TA=75ºC Nominal relationship: N(T)= Sn*T+Nn -900 LSB/ºC Nominal Offset (Nn) 4 40000

0 LSB

N T NT ERR )) 25 ( ) ( () 25 ( −− − = TA = -40ºC to +85ºC -3 +3 ºC PULSE GENERATOR TIMING SPECIFICATIONS PARAMETER CONDITION MIN TYP MAX UNIT PULSEW, PULSER maximum rate APULSE=231-1, WRATE=215-1 7.56 kHz PULSE3, PULSE4 maximum rate PULSE3=231-1, WRATE=215-1 0.15 kHz Pulse count frequency all pulse outputs 0.15 kHz

Page: 6 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 THERMAL CHARACTERISTICS PARAMETER CONDITION VALUE UNIT Thermal resistance, junction to ambient (RθJA ) Air velocity 0 m/s. Part soldered to PCB. 63.7 °C/W UART HOST INTERFACE PARAMETER CONDITION MIN TYP MAX UNIT Baud Rate 19.2 - 38.4 kBaud Character set binary Data Format 8N1 Byte-to-byte delay (6515H times out after maximum delay) Host sending data to 6515H 10 20 ms Byte-to-byte delay 6515H sending data to host 0 0.1 ms Response time to read command 6515H has data ready 0.5 2 ms Response time to read command when 71M6515H is post-processing data Data not ready CE_ONLY = 1 CE_ONLY = 0 and VAH_SELECT = 0 CE_ONLY = 0 and VAH_SELECT = 1 350 ms ms ms ADC CONVERTER, V3P3 REFERENCED PARAMETER CONDITION MIN TYP MAX UNIT Usable Input Range (Vin-V3P3A) -250 250 mV peak Voltage to Current cross talk: )cos(* 106 VcrosstalkVinVin Vcrosstalk ∠ − ∠ Vin = 200mV peak, 65Hz, on VA, VB, or VC Vcrosstalk = largest measurement on IA, IB, or IC -10 +10 µV/V THD (First 10 harmonics) 250mV-pk 20mV-pk Vin=65Hz, 64kpts FFT, Blackman- Harris window -75 -90 dB dB Input Impedance Vin=65Hz 40 90 kΩ Temperature Coefficient of Input Impedance Vin=65Hz 1.7 Ω/°C LSB size 355 nV/LSB Digital Full Scale +884736 LSB ADC Gain Error vs. %Power Supply Variation 3 . 3 / 3 3 100 / 357106 A P V V nVNout INPK Δ Δ Vin=200mV pk, 65Hz V3P3A=3.0V, 3.6V 50 PPM/ Input Offset (Vin-V3P3A) -10 +10 mV

Page: 7 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 RECOMMENDED EXTERNAL COMPONENTS NAME FROM TO FUNCTION VALUE UNIT C1 V3P3A AGND Bypass capacitor for 3.3V supply ≥0.1±20% μF C2 V3P3D DGND Bypass capacitor for 3.3V supply ≥0.1±20% μF XTAL XIN XOUT 32.768kHz crystal – electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capaci- tance 12.5pF 32.768 kHz CXS XIN AGND Load capacitor for crystal (depends on crystal specs and board parasitics). 27±10% pF CXL XOUT AGND 27±10% pF C2P5 V2P5 DGND Bypass capacitor for V2P5 ≥0.1±20% µF FOOTNOTES: 1 This spec is guaranteed, has been verified in production samples, but is not measured in production. 2 This spec is guaranteed, has been verified in production samples, but is measured in production only at DC. 3 This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal re lationship rather than a measured parameter. Correct circuit operation is verified with other spe cs that use this nominal relationship as a reference PIN CONFIGURATION AND PIN FUNCTION TERIDIAN 71M6515H-IGT GNDD RESERVED TMUXOUT /RTM TX SSCLK CKTEST V3P3D SSDATA SFR RESERVED PULSE3 PULSE4

64 GNDD

BAUD_RATE RESERVED MUX_SYNC SRDY GNDD RESERVED VB VREF XIN GNDA V3P3A XOUT GNDA IA VC VFLT VX IC VA IB PULSE_INIT RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GNDD Pins marked RESERVED should be left unconnected during normal use.

Page: 8 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Analog Pin Description Name Pin No. Type Circuit Description IA, IB, IC I 6 Line Current Sense Inputs: Voltage inputs to the internal A/D converter. Typically, they are connected to the output of a current transformer. The input is referenced to V3P3A. Unused pins must be tied to V3P3A. VA, VB, VC I 6 Line Voltage Sense Inputs: Voltage inputs to the internal A/D converter. Typically, they are connected to the output of a resistor divider. The input is referenced to V3P3A. Unused pins must be tied to V3P3A. VFLT 59 I 7 Power Fault Input. This pin must be tied to V3P3A. VX 58 I 6 Auxiliary input (not used). This pin should be tied to VREF. VREF 57 I/O 9 Voltage Reference for the ADC. XIN, XOUT

63 I 8

Crystal Inputs: A 32768Hz crystal should be connected across these pins. Typically, a 15pF capacitor is also connected from each pin to GNDA. See the datasheet of the crystal manufacturer for details. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”. Digital Pin Description Unless otherwise indicated, all inputs and outputs are standard CMOS. Inputs do NOT have internal pull-ups or pull-downs. Name Pin No. Type Circuit Description CKTEST 6 I/O 4 Clock PLL output. Can be enabled and disabled by CKOUT_DSB (see Status Mask). I/O 3, 4 Input/output pins 0 through 7. These pins must be terminated to V3P3D or ground if configured as input pins. D0 through D7 float after reset or power-up and are configured as outputs and driven low 140ms after RESETZ goes high. PULSE4 15 O 4 The fourth pulse generator output PULSE3 14 O 4 The third pulse generator output PULSE_INIT 40 I 3 The pulse output initial power-up voltage (0: 0V, 1: 3.3V), default is 1. This pin must be terminated to V3P3D or ground. BAUD_RATE 16 I 3 The UART baud rate (1: 38.4kbd, 0: 19.2kbd). This pin must be terminated to V3P3D or ground. IRQZ 41 O 4 Interrupt output, low active. A falling edge indicates the end of a measurement frame, as well as alarms. Rises when status word is read. MUXSYNC 25 O 4 Internal signal. MUXSYNC falls at the beginning of each conversion cycle (multiplexer frame). RESETZ 47 I 1 Chip reset: Input pin with internal pull-up resistor, used to reset the chip into a known state. For normal operation, this pin is set to 1. To reset the chip, this pin is driven to 0 for 5 microseconds. No external reset circuitry is necessary for power-up reset.

Page: 9 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Name Pin No. Type Circuit Description UARTCSZ 34 I 3 Enables the UART when 0. The UART is disabled when this pin is set to 1. A positive pulse on this pin will reset the UART. This pin must be terminated to ground. SRDY SFR SSCLK SSDATA I O O O High-Speed Synchronous Interface (SSI). The SRDY input should be tied to ground. SSI frame pulse output, one SSCLK wide. SSI clock output (5MHz or 10MHz selectable). SSI data output, changes on the rising edge of SSCLK. RX 44 I 3 UART serial Interface receiver input. The voltage at this pin must not exceed 3.6V. This pin must be terminated to V3P3D or ground. TX 4 O 4 UART serial Interface transmitter output. TMUXOUT 3 O 4 Digital output test multiplexer. Controlled by TMUX[2:0]. PULSER PULSEW O O Selectable pulse output (default: VARh pulse). Selectable pulse output (default: Wh pulse). Power/Ground Pin Description Name Pin No. Type Description GNDA 49,60 P Analog ground: This pin should be connected directly to the ground plane. GNDD 1,27, 48,62 P Digital ground: These pins must be connected directly to the ground plane. V3P3A 50 P Analog power: A 3.3V analog power supply should be connected to this pin. V3P3D 7 P Digital power supply: A 3.3V digital power supply should be connected to this pin. VBAT 45 P Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D. V2P5 46 O Output of the 2.5V regulator. A 0.1µF capacitor should be connected from this pin to GND. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”. Reserved Pins Pins labeled RESERVED are not to be connected. Name Pin No. Description RESERVED 2,10,11,12, 13,17,18,19, 20,26,28,29, 30,31,32,43, DO NOT CONNECT THESE PINS!

Page: 10 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 I/O Equivalent Circuits Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up GNDD 110K V3P3D CMOS Input V3P3D Digital Input Pin Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down GNDD 110K GNDD CMOS Input V3P3D Digital Input Pin Digital Input Type 3: Standard Digital Input or pin configured as DIO Input GNDD CMOS Input V3P3D Digital Input Pin CMOS Output GNDD V3P3D GNDD V3P3D Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output Digital Output Pin To MUX GNDA V3P3A Analog Input Equivalent Circuit Type 6 : ADC Input Analog Input Pin Comparator Input Equivalent Circuit Type 7: Comparator Input GNDA V3P3A To Comparator Comparator Input Pin VREF Equivalent Circuit Type 9: VREF from internal reference GNDA V3P3A VREF Pin V2P5 Equivalent Circuit Type 10: V2P5 from internal reference GNDD V3P3D V2P5 Pin VBAT Equivalent Circuit Type 12: VBAT Power GNDD Power Down Circuits VBAT Pin Oscillator Equivalent Circuit Type 8: Oscillator I/O To Oscillator GNDD V3P3D Oscillator Pin

0 Deg

60 Deg

-60 Deg

180 Deg

Figure 3: Wh Accuracy, 0.3A - 200A/240V 200100 103 0.3 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.1 1 10 100 1000A % Error

90 Deg

150 Deg

270 Deg

Figure 4: VARh Accuracy for 0.3A to 200A/240V Performance. 13579 1 1 1 3 1 5 1 7 1 9 2 1 2 3 2 5 Harmonic Error [%] 50Hz Harmonic Data 60Hz Harmonic Data Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Figure 5: Meter Accuracy over Harmonics at 240V, 30A

Page: 13 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 FUNCTIONAL DESCRIPTION THEORY OF OPERATION The 71M6515H integrates the primary functional blocks required to implement a solid-state electricity meter front end. Included on-chip are an analog front end (AFE), a digi tal computation engine (CE), a voltage refer ence, a real time clock, and I/O pins. Various current sensor technologies ar e supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils. In a typical application, the 71M6515H s equentially digitizes the voltage inputs on pi ns IA, VA, IB, VB, IC, VC and performs calculations to measure active energy (Wh), reactive energy (VARh), and apparent energy (VAh). In addition to these measurement functions, the real time clock function allows the device to record ti me of use (TOU) metering information for multi-rate applications. The 71M6515H contains a temperat ure-trimmed ultra-precise voltage reference, and the on-chip digital temperature compen- sation mechanism includes a temperature sensor and associated controls for correction of unwanted tem perature effects on measurement. RTC accuracy can be greatly improved by supplying correction coefficients derived from crystal characterization. The combination of both features enables designers to produce electricity meters with exceptional accuracy over the industrial temperature range. Meter Equations The 71M6515H implement s the equations in Table 1. Register EQU specifies the equation to be used. In one sample time, each of the six inputs is converted and the selected equat ion updated. In a typical applicati on, IA, IB, IC are connected to current transformers that sense the cu rrent on each phase of the li ne voltage. VA, VB, and VC ar e typically connected to voltage sensors (resistor dividers) with respect to NEUTRA L. NEUTRAL is to be connect ed to V3P3A, the analog supply voltage. NEUTRAL is the zero reference for all analog measurements. EQU Watt & VAR Formula Application Channels used from MUX sequence Mux State: 0 1 2 3 4 5

0 VA IA 1 element, 2W 1ø IA VA - - - -

1* VA(IA-IB)/2 1 element, 3W 1ø IA VA IB - - -

2 VA IA + VB IB 2 element, 3W 3 øDelta IA VA IB VB - -

3* VA (IA - IB)/2 + VC IC 2 element, 4W 3ø Delta IA VA IB - IC VC 4* VA(IA-IB)/2 + VB(IC-IB)/2) 2 element, 4W 3ø Wye IA VA IB VB IC -

5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye IA VA IB VB IC VC

Note: Equations 1*, 3*, 4* available only when IMAGE = 00 (CT mode). Table 1: Meter Equations Table 2 shows how the elements of the meter are mapped for the six possible equations.

0 VA IA (1 element, 2W 1φ) VA*IA - - IA - -

1 VA*(IA-IB)/2

(1 element, 3W 1φ) VA*(IA-IB)/2 VA*IB - IA-IB IB -

2 VAIA + VBIB

(2 element, 3W 3φ Delta) VA*IA VB*IB - IA IB - VA*(IA-IB)/2 + VC*IC (2 element, 4W 3φ Delta) VA*(IA-IB)/2 - VC*IC IA-IB IB IC VA*(IA-IB)/2 + VB*(IC-IB)/2 (2 element, 4W 3φ Wye) VA*(IA-IB)/2 VB*(IC-IB)/2 IA-IB IC-IB IC VA*IA + VB*IB + VC*IC (3 element, 4W 3φ Wye) VA*IA VB*IB VC*IC IA IB IC Table 2: Meter Element Output Mapping ANALOG FRONT END A/D Converter (ADC) A single delta-sigma A/D converter (ADC) digitizes the inputs to the device. The resolution of the ADC is 21 bits. The ADC operates at 5MHz oversampling rate and pl aces the digital results in CE memory . Each analog input is sampled at 2520Hz. Once each accumulation interval, it refreshes the temperature value that is placed in the TEMP_RAW register. The analog re- ference for all inputs is V3P3A, i.e. the ADC processes voltages between the input pins and V3P3A. Voltage Reference The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques as well as production trims to minimize errors caused by component mismat ch and drift. The result is a voltage output with a predictable temperature coefficient. The CE compensates for temperature char acteristics of the voltage reference by modifying the gain applied to the V and I channels based on the coefficients PPMC and PPMC2. See the section “TEMPERATURE COMPENSATION” for details. DIGITAL COMPUTATION The six ADC outputs are processed and accumulated digitally. The default product summation is based on 42*60 (if the SUM_CYCLES register is set to 60) samples per accumulation inte rval. At the end of each accumulation interval, a ready interrupt (IRQZ) is signaled (if enabled with the READY bit in STMASK), indicating that fresh data is available to the host. For instance, if SUM_CYCLES =30, the IRQZ rate will be 2Hz (500ms). A dedicated 32-bit Computation Engine (CE) performs the precision com putations necessary to accurately measure energy. Internal CE calculations include frequenc y-insensitive offset cancellation on a ll six channels and a frequency insensitive 90 ° phase shifter for VAR calculations. The CE also includes LP F smoothing filters after each product and squaring circuit to attenuate ripple and eliminate beat frequencies between the power line fundamental and the accumulation time. The CE directly calculates Watts, VARs, V2, and I2 and accumulates them for one interval. At the end of each CE comput ation cycle, the accumulat ed data are post-processed to calculate RMS amplitudes, phase angles, and VAh. When post-processing is complete, the IRQZ signal is activated. The minimum combined cycle time for CE and post-processor is 400ms, which makes the maximum frequency for the IRQZ signal 2.5Hz.

Page: 15 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 If the 71M6515H is interfacing to an external DSP (typically, but not necessarily through the SSI interface), the host may turn off post-processing by setting the CE_ONLY bit in the CONFIG word. This will permit setting SUM_CYCLES below its recommended lower limit of 24. SUM_CYCLES may then be reduced to 1, creating an accumulation interval of only 42 samples. The outputs available in CE only mode are limited to temperature, frequency, voltage phases, input signal zero crossings, plus WSUM and VARSUM for each phase and VSQSUM, ISQSUM, and ISQFRACT for each phase. Pulse Generators The chip contains four pulse generators connected to the pins PULSEW, PULSER, PULSE3, and PULSE4 that create low jitter pulses from 32-bit data. The peak time jitter for PULSEW and PULSER is the 397µs MUX frame period, and is independent of the rate of the generator or t he length of time the generator is monitored. Thus, if the pulse generator is monitored for 1 second, the peak jitter is 400PPM. After 10 seconds, the peak jitter is 40PPM. PULSE3 and PULSE4 are updated at a slower rate and have four times higher jitter, i.e. 160PPM after 10 seconds. The average jitter is always zero. If it is attempted to drive either pulse generator faster t han its maximum rate, it will sim ply output at its maximum rate without exhibiting any roll-over characteristics. Pulse generator inputs may be from three sources:

Internal (directly from the CE), PULSEW and PULSER only
External (controlled by the host writing to registers APULSEW, APULSER, APULSE3, APULSE4)
Post-processed values The source is selected individually for each pulse output with the PULSEW_SRC, PULSER_SRC, PULSE3_SRC, and PULSE4_SRC registers. Figure 8 shows internal pulse generation for the PULSEW output selected by writi ng the value 35 into the PULSEW_SRC register. PULSEW_SRC 35: WSUM 0: WSUM 1: WASUM 2: WBSUM 3: WCSUM 4: VARSUM 34: VAR2SUM_E 36: APULSEW HOST CE PULSEW OUTPUT POST PROCESSOR 34: VAR2SUM_E Figure 8: Internal Pulse Generation Selected in the PULSEW_SRC Register Internal data is pulsed out during the accumulation interval immediately following its accumu lation interval. Post-processed values are pulsed out one accumulation interval after that.

Page: 16 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 The pulse generator output rate depends on its input value, WRATE , PULSE_SLOW, and PULSE_FAST. Additionally, its maximum pulse width (negative going pulse) is controlled by PULSEWIDTH. High frequency pulses will have 50% duty cycle until their rate slows enough that their pulse width is limited by PULSEWIDTH. In internal and post-processed modes, the pulse rate, expressed as Kh (Wh per pulse) is given by the formula: Pulse WhX WRATECYCLESSUM In IMAXVMAXKh / 5757 . 1_ 8 _ ⋅ ⋅⋅= where VMAX is the meter voltage corresponding to an input voltage of 176mV (rms) at the VA, VB, and VC input pins , IMAX is the meter current corresponding to an input voltage of 176mV (rms) at the IA, IB, and IC input pins, In_8 is the additional ADC gain (1 or 8), as controlled by the IA_X, IB_X and IC_X bits in the CONFIG register. X is the pulse speed factor determined from Table 3. PULSE_SLOW PULSE_FAST X 0 0 1.5*22=6 0 1 1.5*26=96 1 (default) 1 (default) 1.5 Table 3: Pulse Speed Factor X In external pulse mode, the pulse rate is given by the formula: Rate(Hz) = WRATE * X * input * 35.82*10-12, where input is the value in registers APULSER, APULSEW. APULSE3 or APULSE4, X is the pulse speed factor determined from Table 3. External pulse generation can be seen as providing the raw voltage and current readings equivalent to V in*Iin / LSB directly to the pulse generator. The maximum pulse rate is 7.56kHz for PULSEW and PULSER, and 150Hz for PULSE3 and PULSE4. In external pulse mode, the pulse generators load their data at the beginning of each CE accumulation interval, preserving any partially implemented pulses from the pr evious interval. The source of data is controlled by the entries in the PULSE_SRCS register. PULSER_SRCS contains 8-bit entries for each pulse source, PULSEW, PULSER, PULSE3, and PULSE4. See the register description for details. The procedure for accurate external pulse generation controlled by the host is: 1) Respond to a READY interrupt by reading the accumulated values. 2) Process the accumulated values. 3) Write the processed value(s) to APULSER, APULSEW, APULSE3, or APULSE4. The host must write to APULSER, APULSEW, APULSE3, and APULSE4 before the next READY interrupt for t he pulse generation to be beginning in the following accumulation interval. Figure 9 illustrates pulse generator timing. Regardless of the source, the pulse gener ators should receive new data during each accumulation interval. If this does not occur and if the corresponding bit in the STMASK register is set, an APULSE_ERR interrupt will be issued. The PULSEW, PULSER, PULSE3 and PULSE4 pins are suitable fo r driving LEDs through a current limiting resistor. The LED should be connected so it is on when the pulse pin is low. The pin PULSE_INIT determines the logic level applied to the pul se pins on power-up, i.e. with PULSE_INIT low, the pulse pins will be initialized to low (default = 1).

Page: 17 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 The pulse width P W is controlled with the PULSEWIDTH register for the PULSER and PUL SEW output pins per the following formula: 6 . 2520 12 +⋅= PULSEWIDTHPW The PULSE3 and PULSE4 output pins will always generate pulses with 50% duty cycle. Accumulation 1 Accumulation 2 Accumulation 3 Post 1Post 0 Post 2 READY APULSE write CE Operations Post Processing Pulse -1 Pulse 0 Pulse 1Pulse Generator READY READY XFER XFER XFER Accumulation Interval Post-Processed Data APULSE write APULSE write Accumulation 1 Accumulation 2 Accumulation 3 Post 1Post 0 Post 2 READY CE Operations Post Processing Pulse 0 Pulse 1 Pulse 2Pulse Generator READY READY XFER XFER XFER Accumulation Interval Internal Data (Directly by CE) Accumulation 1 Accumulation 2 Accumulation 3 Post 1Post 0 Post 2 Host 0 READY CE Operations Post Processing Host Processing Pulse -2 Pulse -1 Pulse 0Pulse Generator Host 1 READY Host 2 READY XFER XFER XFER Accumulation Interval External (Host data is transferred to the pulse generator in the first accumulation interval after the next READY) APULSE write APULSE write APULSE write Figure 9: Pulse Generator Timing

Page: 18 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Internal Resources Oscillator The oscillator drives a standard 32.768kHz watc h crystal. Crystals of this type are accurate and do not require a high current oscillator circuit. The 71M6515H oscillator has been designed specifically to handle watch crystals and is compatible with thei r high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Using PLL techniques, all internal clocks, such as the 4.915MHz clock for the ADC and the post-processor, are derived from the watch crystal frequency. Real-Time Clock (RTC) The RTC is driven directly by the crystal oscillator. In the absence of V3P3, it is powered by the battery-backed up supply. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, mont h, and year. The nominal quadratic temperature coefficient of the crystal is automatically compensated in the RTC. The RTC is capable of processing leap years. I/O Peripherals The 71M6515H includes several I/O peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. The I/O peripherals include a UART and digital I/O. Digital I/O The device includes eight pins of general purpose digital I/O (D0…D7). Each pin can be configured independently as an input or output with the D_DIR bits. Inputs are standard CMOS with no pull-ups or pull-downs. Outputs are standard CMOS. The DIO pins are controlled by the D_CONFIG register. Immediately after reset or power-up, D0 through D7 are in tri-state mode (floa ting). 140 ms after reset, D0 through D7 are configured as outputs and driven low. UART Host Interface The UART is a dedicated 2-wire serial inte rface, which can communicate with the host processor. The operation of each pin is as follows: RX: Is the pin accepting the serial input dat a. It inputs data to internal registers. The bytes are input LSB first. The voltage applied to this pin must be restricted to 0 to 3.6V. TX: Is the pin used for serial output data. It outputs the contents of a block of internal regist ers. The bytes are output LSB first. BAUD_RATE: The baud rate can be selected with the BAUD_RATE pin (38.4bps when high, 19.2bps when low). UARTCSZ: This pin enables the UART when low. The UART can be reset by taking UARTCSZ briefly to the high state and then low again. The 71M6515H has several on-chip registers, which can be read and written. All transfers start with a stream of 8-bit bytes (LSB first) from the host on the RX input, followed by a (possibl y null) stream of 8-bit bytes (LSB first) to the host on the T X output (see Figure 10 and Figure 11). The UART is configured as 8N1 (8 bits, no parity, 1 stop bit). If the READY bit in STMASK is enabled, the IRQZ pin can be used to signal data availability to the host. If data read cycles exceeding 1 second are used, care should be taken to prevent data overflow. UART Write Register Operation The registers are written by sending a byte , consisting of a starting register addre ss in the seven MSBs and ‘0’ in the LSB indicating this is a write operation. It is followed by a one byte length of bytes to write. If more bytes arrive than fit in t he addressed register, subsequent regist ers will be written. The bytes are processed in “big-endian” order (i.e. most significant byte first). See Figure 10 (read bits and bytes from left to right).

Page: 20 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 The SSI timing is shown in Figure 12. SCLK (Output) SSDATA (Output) SFR (Output) 31 30 16 15 10 3 1 SSI_BEG 30 16 15 10 3 1 SSI_BEG +1 SSI_END If 16bit fields If 32bit fieldsIf SSI_CKGATE =1 If SSI_CKGATE =1 MUX_STATE Figure 12: SSI Timing (SSI_FPOL = SSI_RDYPOL = 0) Fault and Reset Behavior Reset Mode When RESETZ is pulled low or when VFLT < V3P3/2, all activi ty (i.e. sampling of analog signals, CE, generation of digital outputs) in the chip stops wh ile the analog circuits are active. The except ions are the oscillator and RTC module, which continue to run. Additionally, all I/O Register bits are cleared. As long as VFLT > V3P3/2, the internal 2.5V regulator will continue to provide power to the digital section. Once initiated, the reset mode will persist until the reset timer times out. This will occur in 4100 cycles of the real time cl ock after RESETZ goes high, at which time the 71M6515H will begin executing its preboot and boot sequences. Power Fault Circuit The power fault comparator com pares the voltage at the VFLT pin to V3P3/2. The comparator output internally enables the battery backup protection for oscillator, RTC and RAM during the power fail mode. Temperature Compensation Voltage Reference The internal voltage reference of the 71M6515H is calibrated at 25 °C during device manufacture. The 71M6515H is given additional temperature-related calibrations which further compensate its ADC gain and allow it to achieve 10PPM/°C over ±60°C temperature range. Temperature Sensor The device includes an on-chip temperatur e sensor for determining the temperatur e of the bandgap refer ence. The primary use of the temperature dat a is to determine the magnitude of compensation required to offset t hermal drift in the system. The temperature sensor is read once per accumulation interval. Temperature measurement can be implemented with the following steps: 1) At a known temperature T N, read the TEMP_RAW register and write the value into TEMP_NOM register. 2) Read the DELTA_T register at the known temperature. The obtained value should be <±0.1°C. 3) The temperature T (in °C) at any environment can be obt ained by reading the DELTA_T register and applying the following formula: _ T DELTAT TN + = Temperature Compensation for Energy Measurements TEMP_NOM is one of the calibration parameters that must be loaded by the host in or der to enable temperature measurement and thereby temperature compensation.

Page: 21 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 PPMC and PPMC2, the linear and quadratic compensation coefficients, compensate for te mperature drift in the 71M6515H reference that affects the meter performance. PPMC and PPMC2 describe how the 71M6515H calculations are to respond to temperature. This means they should be the negative of the me ter behavior before compensation. PPMC and PPMC2 are scaled from PPM/ °C and PPM/ °C2 values. See the register description fo r details. Temperatur e compensation can be selected to operate in one of two modes shown in the table below: Temperature Compensation Mode DEFAULT_PPM Bit in CONFIG Register PPMC, PPMC2 Calculation Internal (CE) 1 By post-processor, based on stored VREF characteristics External (host) 0 By host When the part is first powered up, TEMP_NOM , PPMC, and PPMC2 are zero. When the host writes its calibration value into TEMP_NOM (after setting the DEFAULT_PPM bit on the CONFIG register to 1), PPMC and PPMC2 will automatically be initialized to the values that best compensate for the temperature drift of t he internal reference. These parameters will be individually customized for 71M6515H parts. If, for some reason, the host writes to TEMP_NOM again, PPMC and PPMC2 will not be changed since they will no longer be zero. If TEMP_NOM is not loaded by the host, PPMC and PPMC2 are ignored, and their values are permanently held at zero. If TEMP_NOM is zero, no temperature compensation occurs, even if PPMC and PPMC2 are loaded. If the host wishes to provide its own compensation, it should read PPMC and PPMC2 and modify them by merging the additional compensation into to them. In that case, the DEFAULT_PPM bit in the CONFIG register must be zero. Temperature Compensation for the Crystal and RTC The crystal oscillator contributes negligible error to energy calc ulations. However, sometimes s pecifications for the real time clock (RTC) require better accuracy than that provided by the untrimmed watch crystal. The 71M6515H therefore allows calibration of the RTC clock. Calibration requires that fr equency tolerance and frequency stabilit y either be obtained from the manufacturer or be independently measured (t he RTC clock is available on the TMUX pin). Calibration does not change the frequency of the RTC clock, but rather increments or decre ments the clock by one second when sufficient error has accumulated. Positive correction makes the clock run faster. The formula for the RTC correction factor is as follows: CORRECTION [PPM] = TCALC YTCALC Y CALC Y Δ+Δ+ 1000 2 _ 100 1 _ 0 _ Where Y_CALC0 = 10 * crystal frequency deviation from ideal (measured) Y_CALC1 = 100 * crystal skew (nominally zero) Y_CALC2 = 1000 * crystal frequency stability (specified) ΔT = T - Calibration Temperature in °C Calibration Calibration Factors for CT and Resistive Shunt Once installed in a meter, the TERIDIAN 71M6515H IC has to be calibrated for the tolerances of current sensors, voltage dividers and signal conditioning components. The room temperature reading of its temperature sensor must also be entered. These calibration factors must be stor ed by the host and, upon power up, loaded in to the TERIDIAN 71M6515H. Typical calibration constants are listed in Table 4.

Page: 22 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Name Description CAL_IA Gain factors for current and voltage of each phase. CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC TEMP_NOM The value of TEMP_RAW at nominal temperature. PHADJ_A Phase compensation for each current. If phase compensation is 0 or if current sensors have predictable phase, PHADJ may not need to be measured on every meter. PHADJ_B PHADJ_C Table 4: Typical Calibration Parameters (CT) Gain adjustment ( CAL_Xn parameters) is used to compensate for toler ances of components used for signal conditioning, especially the resistive components. A 1% increase in CAL_Xn will cause a 1% increase in the channel gain. The phase compensation circuit in the TERIDIAN 71M6515H is optimized for operation with current transformers (CT’s). These devices have a low frequency pole and theref ore have a slight amount of phase lead at 50 or 60H z—more at 50Hz than at 60Hz. The phase lead diminishes at higher harmonics. When PHADJ_n is calibrated as shown below at either 50Hz or 60Hz, the CT will be correctly compensated from below 25Hz to beyond 1100Hz. This phase compensator is markedly superio r to the more common technique of programming a time delay to compensate for CT phase. The time delay technique results in phase compensation that is correct at only one frequency, and actually amplifies the phase error at harmonics of the frequency. Calibration Factors for Rogowski Coil Sensors If IMAGE is set to 01, i.e. the 71M6515H can be operated with Rogowski Coil sensors. In this case, one more calibration factor per phase is needed. The PHADJ parameters have non-zero defaults and do not obey the same formula used for CT calibration. The feedthrough paramet er has to be determined by a s eparate crosstalk measurement. Table 5 shows the parameters involved in the calibration procedure for the Rogowski sensor. Name Description CAL_IA Gain constants for current and voltage of each phase. CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC TEMP_NOM The value of TEMP_RAW at nominal temperature. PHADJ_A Phase compensation for each current. If phase compensation is 0 or if current sensors have predictable phase, PHADJ may not need to be measured on every meter. PHADJ_B PHADJ_C VFEED_A Feedthrough compensation for each current. VFEED_B VFEED_C Table 5: Typical Calibration Parameters (Rogowski)

Page: 24 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Calibration with Three Measurements The simplest calibration method is to make three measurem ents. Typically, a voltage meas urement and two Watt-hour (Wh) measurements are made. If the voltage measurement has the error E V and the two Wh measurements have errors E 0 and E 60, where E 0 is measured with φL = 0 and E 60 is measured with φL = 60. These values should be simple ratios—not percentage values. They should be zero when the meter is accurate and negative when t he meter runs slow. The fundamental frequency is f 0. T is equal to 1/f S, where f S is the sample frequency (2520.62Hz). Se t all calibration factors to nominal: CAL_IA = 16384, CAL_VA = 16384, PHADJ_A = 0. From the voltage measurement, we determine that 1.Î 1+ =VXV E A We use the other two measurements to determine φS and AXI. 2. 1 ) cos(1) 0 cos( ) 0 cos( 0 −= −−= SXI XV SXI XV A AIV A A IVE φφ 2a. ) cos( S XI XV EA A φ 3. 1) 60 cos( ) 60 cos(1) 60 cos( ) 60 cos( 60 −−= −−= S XI XV SXI XV A AIV A A IVE φφ 3a. [] 1) 60 cos( ) sin( ) 60 sin( ) cos( ) 60 cos( 60 −+= SSXI XVA AE φφ 1 ) sin( ) 60 tan() cos( −+= SXI XVSXI XV A AA A φφ Combining 2a and 3a: 4. ) tan( ) 60 tan( ) 1 (0 0 60 SE E E φ+ + = ) 60 tan( ) 1 () tan( 0 60 −= E E E Sφ 6.Î ⎟⎟ −= − ) 60 tan( ) 1 (tan 0 601 E E E Sφ and from 2a: 7.Î ) cos( SXV XI A EA φ Now that we know the AXV, AXI, and φS errors, we calculate the new calibration voltage gain coefficient from the previous ones: XV NEW A V CALV CAL __ =

Page: 25 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 We calculate PHADJ from φS, the desired phase lag: [] ⎥ − − −− ) 2 cos( ) 2 1 ( 1 ) tan( ) 2 sin( ) 2 1 ( ) 2 cos( ) 2 1 ( 2 ) 2 1 ( 1 ) tan(2 92 9 T fT f T fPHADJ S S πφπ πφ Finally, we calculate the new calibration current gain coefficient, including compensation for a slight gain increase in the phase calibration circuit. 2 9 92020 ) 2 1 ( ) 2 cos( ) 2 1 ( 2 1 )) 2 cos( ) 2 1 ( 22 2 (21 1__ −−− − +− − − −++ T f T fPHADJPHADJA I CALI CAL XI NEW π π Calibration with Five Measurements The five measurement method provides more orthogonality between the gain and phase error derivations. This method involves measuring E V, E0, E180, E60, and E 300. Again, set all calibration factors to nominal, i.e. CAL_IA = 16384, CAL_VA = 16384, PHADJ_A = 0.. First, calculate AXV from EV: 1.Î 1+ =VXV E A Calculate AXI from E0 and E180: 2. 1 ) cos(1) 0 cos( ) 0 cos( 0 −= −−= SXI XV SXI XV A AIV A A IVE φφ 3. 1 ) cos(1) 180 cos( ) 180 cos( 180 −= −−= SXI XV SXI XV A AIV A A IVE φφ 4. 2 ) cos(2180 0 −= + SXI XVA A E Eφ ) cos( 2 2180 0 S XI XV E EA A φ + += 6.Î ) cos( 1 2 ) (180 0 SXV XI A E EA φ + += Use above results along with E60 and E300 to calculate φS. 7. 1) 60 cos( ) 60 cos( 60 −−= IV A A IVE SXI XV φ 1 ) sin( ) 60 tan() cos( −+= SXI XVSXI XV A AA A φφ 8. 1) 60 cos( ) 60 cos( 300 −− − −= IV A A IVE SXI XV φ 1 ) sin( ) 60 tan() cos( −−= SXI XVSXI XV A AA A φφ

Page: 26 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Subtract 8 from 7: 9. ) sin( ) 60 tan(230060 SXI XVA A E E φ= − use equation 5: 10. ) sin( ) 60 tan() cos( 2180 0 30060 S S E EE E φφ + += − 11. ) tan( ) 60 tan( ) 2( 180 030060 SE E E E φ+ + = − 12.Î ⎟⎟ + + −= − ) 2)( 60 tan( ) (tan 180 0 300601 E E E E Sφ Now that we know the AXV, AXI, and φS errors, we calculate the new calibration voltage gain coefficient from the previous ones: XV NEW A V CALV CAL __ = We calculate PHADJ from φS, the desired phase lag: [] ⎥ − − −− ) 2 cos( ) 2 1 ( 1 ) tan( ) 2 sin( ) 2 1 ( ) 2 cos( ) 2 1 ( 2 ) 2 1 ( 1 ) tan(2 92 9 T fT f T fPHADJ S S πφπ πφ Finally, we calculate the new calibration current gain coefficient, including compensation for a slight gain increase in the phase calibration circuit. 2 9 92020 ) 2 1 ( ) 2 cos( ) 2 1 ( 2 1 )) 2 cos( ) 2 1 ( 22 2 (21 1__ −−− − +− − − −++ T f T fPHADJPHADJA I CALI CAL XI NEW π π Alternative Calibration Procedures It is possible to implement a fast calibration based on only one measurement with a zero- degree load angle. Details can be found in the TERIDIAN Application Note AN_651X_022 (Calibration Procedures). Calibration Procedure for Rogowski Sensor Rogowski coils generate an output signal that is the derivative of the input current. The 6515H Rogowski module implemented in the Rogowski CE image digitally compensates for this effect and has the usual gain and phase calibration adjustments. Additionally, calibration adjustments are provided to eliminate voltage coupling from the sensor input. Current sensors built from Rogowski coils have relatively hi gh output impedances that are susceptible to capacitive coupling from the large voltages pr esent in the meter. The most dominant coupling is usually capac itance between the primary of the coil and the coil’s output. This coupling adds a component proportional to the derivative of voltage to the sensor output. This effect is compensated by the voltage coupling calibration coefficients. As with the CT procedure, the calibration procedure for Rogowski sensors uses the meter’s display to calibrate the voltage path and the pulse outputs to perform the remaining energy calibrations. The calibration procedure must be performed to each phase separately, making sure that the pulse generator is driven by the accumulated real energy fo r just that phase. In other words, the pulse generator input should be set to WhA, WhB, or WhC, depending on the phase being calibrated. The IC has to be configured for Rogowski mode ( IMAGE=01). In preparation of the calibration, a ll calibration parameters are set to their default values. VMAX and IMAX are set to reflect the system design parameters. WRATE and PULSE_SLOW, PULSE_FAST are adjusted to obtain the desired Kh. For details on calibrating a meter for Rogowski coil sensors, see the TERIDIAN Application Note AN_6515_036.

Page: 27 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Meter Design - Scaling of Measured Values An actual meter will always use sensors that scale the voltages and cu rrents managed by the meter to small voltages that can be processed by the 71M6515H. This scaling is reflected in the system parameters VMAX and IMAX. Scaling is physically implemented with resistor dividers for the voltage signals and current transformers, shunt resistors or Rogowski coils for the current signals. IMAX is the RMS meter current that resu lts in 250mV peak signal (or 177mV RMS) at the ADC input (IA, IB, IC pins). VMAX is the RMS meter voltage that results in 250mV peak signal at the ADC input (VA, VB, VC pins). In_8 is either 1 or 8, depending on In_8x, the ADC gain configuration bit for element n (see IA_8, IB_8, IC_8) in the CONFIG register. Only the host is aware of the system parameters VMAX and IMAX , while the CE and the post-processor know signal amplitudes only as values relative to their maximum peak levels (250mV). This makes the host itself responsible for translating the measured values from the 71M 6515H registers into real-world values by applying the parameters VMAX, IMAX and In_8. Equally, the host is responsible for non-vo latile storage of accumulated energy val ues, calibration factors, default settings e t cetera. Measured values and values determining t he function of the 71M6515H, as controlled by the r egisters described in the following section, are often stated as fractions or multiples of the system parameters VMAX, IMAX and In_8. Host Interface - REGISTER DESCRIPTION Communication between the host and the 71M6515H is established by writing to and r eading from the registers described in this section. The registers are accessible via the UART (see UART Write and Read Operation). The tables below contain the registers that can be accessed by the host to obtain data from the 71M6515H or to control and configure the IC. Bits with a W (write) direction are written by the host. Bits with R (read) direction can only be read by the host. Write operations attempted to read-only regi sters will result in the CMD_IGNORED bit set in the STATUS register. Unless stated otherwise, all registers are four bytes (32 bits), 2’s complement, and have a range of (2 31-1) to -(231-1). Register Groups Each register belongs to one of the following functional groups:

Pulse Generation
Calibration
Control of Basic Functions
Temperature
Temperature Compensation
Output Signals
Accumulated Energy and V/I Values
Alarms and Thresholds
Time (RTC)
Test
Digital I/O Control (pins D0…D7)

Page: 28 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Registers in Alphabetical Order Name Address (hex) R/W Default Group Comment APULSEW APULSER APULSE3 APULSE4 0x30 0x31 0x32 0x33 R/W R/W R/W R/W Pulse Generation Control CAL_IA CAL_VA 0x24 0x25 R/W R/W

214 Calibration

CAL_IB CAL_VB 0x26 0x27 R/W R/W CAL_IC CAL_VC 0x28 0x29 R/W R/W CE_DATA 0x63 R/W N/A Control of Basic Functions CE_DATA_ADDR 0x61 R/W N/A Control of Basic Functions CE_DATA_INC 0x65 R/W N/A Control of Basic Functions CE_PROG 0x62 R/W N/A Control of Basic Functions CE_PROG_ADDR 0x60 R/W N/A Control of Basic Functions CE_PROG_INC 0x64 R/W N/A Control of Basic Functions CONFIG 0x16 R/W 0 Control of Basic Functions CREEP_THRSLD 0x1D R/W 6000 Alarms and Thresholds DEG_SCALE 0x1C R/W 22721 Temperature D_CONFIG 0x1A R/W 15 I/O Control FREQ_DELTA_T 0x11 R N/A Outputs, Temperature GAIN_ADJ 0x4E R 16384 Temperature Compensation IASQFRACT IBSQFRACT ICSQFRACT 0x4A 0x4B 0x4C R R R N/A N/A N/A Outputs IASQSUM IBSQSUM ICSQSUM 0x39 0x3A 0x3B R R R N/A N/A N/A Outputs INSQFRACT 0x4D R N/A Outputs INSQSUM 0x3C R N/A Outputs IPHASE_ABC 0x0F R N/A Outputs Uses the post- processor IRMS_A IRMS_B IRMS_C 0x0C 0x0D 0x0E R R R N/A N/A N/A Outputs Uses the post- processor KVAR 0x2F R 6444 Calibration Do not change MAIN_EDGE_ COUNT 0x35 R N/A Outputs OP_TIME 0x1E R/W 0 Time

Page: 29 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Name Address (hex) R/W Default Group Comment PHADJ_A PHADJ_B PHADJ_C 0x2A 0x2B 0x2C R/W R/W R/W CT: 0 CT: 0 CT: 0 Calibration Defaults are –3973 for Rogowski operation PPMC1_2 0x1B R/W 0 Temperature Compensation PULSE3_4_ CNTS 0x42 R N/A Outputs PULSE_SRCS 0x43 R/W Pulse Generation Control PULSEW_R_ CNTS 0x41 R N/A Outputs PULSE_WIDTH 0x34 R/W 50 Pulse Generation Control QUANT_W QUANT_VAR QUANT_I 0x36 0x37 0x38 R/W R/W R/W Calibration RTC_DATE 0x20 R/W N/A Time RTC_TIME_DAY 0x1F R/W N/A Time RTM 0x21 R/W 0 Test SAG 0x2E R/W 80,

26000 Alarms and Thresholds

0x14 R N/A Control of Basic Functions STMASK 0x15 R/W 0 Control of Basic Functions TEMP_NOM 0x13 R/W 0 Outputs TEMP_RAW 0x12 R N/A Outputs VASQSUM VBSQSUM VCSQSUM 0x3D 0x3E 0x3F R R R N/A N/A N/A Outputs VAH_A VAH_B VAH_C 0x06 0x07 0x08 R R R N/A N/A N/A Outputs Uses the post- processor VARH_A VARH_B VARH_C 0x03 0x04 0x05 R R R N/A N/A N/A Outputs VFEED_A VFEED_B VFEED_C 0x44 0x45 0x46 R/W R/W R/W Calibration VI_PTHRESH 0x17 W 21000 Alarms and Thresholds VI_THRESH 0x40 W 21000 Alarms and Thresholds

Page: 30 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Name Address (hex) R/W Default Group Comment VPHASE_ABC 0x10 R N/A Outputs VRMS_A VRMS_B VRMS_C 0x09 0x0A 0x0B R R R N/A N/A N/A Outputs Uses the post- processor WH_A WH_B WH_C 0x00 0x01 0x02 R R R N/A N/A N/A Outputs WRATE 0x2D R/W 683 Pulse Generation Control Y_DEG0 0x18 R/W 0 Temperature Compensation Holds Y_CALC0 Y_DEG1_2 0x19 R/W 0 Temperature Compensation Holds Y_CALC1 and Y_CALC2

Page: 32 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 At high pulse rates, duty cycle is 50%. At rates less than 1/(2*PWmax), the negative going pulse width is PWmax. The allowed range is 0 to 231-1. The pulse width for the PULSE3 and PULSE4 outputs is always at a 50% duty cycle. The initial voltage level of the pulse pins is defined with the PULSE_INIT pin. Value in Pulse Source Register (hex) (dec) Name Description 0x00 0 WSUM The signed sum: W0SUM + W1SUM + W2SUM 0x01 1 WASUM The sum of Wh samples from individual wattmeter elements. LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh 0x02 2 WBSUM 0x03 3 WCSUM 0x04 4 VARSUM The signed sum: VAR0SUM + VAR1SUM + VAR2SUM 0x05 5 VARASUM The sum of VARh samples from individual wattmeter elements. LSB = 9.4045*10 -13 VMAX IMAX / In_8 VARh 0x06 6 VARBSUM 0x07 7 VARCSUM 0x08 8 VASUM The sum of VAh samples from individual samples. 0x09 9 VAASUM The sum of VAh samples from individual wattmeter elements. LSB = 9.4045*10 -13 VMAX IMAX / In_8 VAh 0x0A 10 VABSUM 0x0B 11 VACSUM 0x0C 12 INSQSUM The sum of the square of the calculated neutral current. ∑ + + . ) (2 2 1 0I I I LSB = 9.4045*10-13 IMAX2 / In_82 A2h 0x0D 13 IASQSUM The sum of squared current samples from each element. LSB = 9.4045*10 -13 IMAX2 / In_82 A2h 0x0E 14 IBSQSUM 0x0F 15 ICSQSUM Table 6: Pulse Sources Defined by the PULSE_SRCS Register (1/2)

Page: 33 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Value in Pulse Source Register (hex) (dec) Name Description 0x10 16 VASQSUM The sum of squared voltage samples from each element. LSB = 9.4045*10-13 VMAX2 V2h 0x11 17 VBSQSUM 0x12 18 VCSQSUM 0x13 19 WSUM_I Imported Energy: W0SUM_I + W1SUM_I + W2SUM_I 0x14 20 WASUM_I Imported energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh 0x15 21 WBSUM_I 0x16 22 WCSUM_I 0x17 23 VARSUM_I Imported VARh: VAR0SUM_I + VAR1SUM_I + VAR2SUM_I 0x18 24 VARASUM_I Exported reactive energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 VARh 0x19 25 VARBSUM_I 0x1A 26 VARCSUM_I 0x1B 27 WSUM_E Exported Energy: W0SUM_E + W1SUM_E + W2SUM_E 0x1C 28 WASUM_E Exported energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh 0x1D 29 WBSUM_E 0x1E 30 WCSUM_E 0x1F 31 VARSUM_E Exported VARh: VAR0SUM_E + VAR1SUM_E + VAR2SUM_E 0x20 32 VARASUM_E Exported reactive energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 VARh 0x21 33 VARBSUM_E 0x22 34 VARCSUM_E 0x23 35 Internal (CE) Connects the pulse generator to the WSUM or VARSUM values internally calculated by the CE. Not selectable for PULSE3 and PULSE4 pulse generators. 0x24 36 External (host) Indicates that the host will provide values in the APULSER, APULSEW, APULSE3, and APULSE4 registers and that the pulse generator should be up- dated on the next READY interrupt.. Table 6: Pulse Sources Defined by the PULSE_SRCS Register (2/2) WRATE (0x2D) This register controls the rate of the pulse generation for the PULSEW, PULSER, PUSE3 and PULSE4 output pins. The inverse pulse rate, expressed as Wh per pulse is: Pulse WhX WRATECYCLESSUM In IMAXVMAXKh / 5757 . 1_ 8 _ ⋅ ⋅⋅= (X = value formed by PULSE_SLOW and PULSE_FAST bits in the CONFIG register)

Page: 34 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Registers Used for Calibration CAL_IA (0x24), CAL_VA (0x25), CAL_IB (0x26), CAL_VB (0x27), CAL_IC (0x28), CAL_VC (0x29): These registers adjust the gain for the current and voltage measurements of each phase for the purpose of calibration. The calibration factors have to be stored by the host and written to the registers of the 71M6515H after power-up. The allowed range is (215 – 1) to –(215 – 1). The default value of 16384 equals unity gain. If a voltage measurement of phase C is higher than expected, CAL_VC has to be adjusted to: CAL_VC = 16384 / (1 + error) Error must be expressed as a fraction, not a percentage value. If the percent error is +3.5%, the relative error is 0.035, and the calibration factor becomes: CAL_VC = 16384 / (1 + 0.035) = 15829.952, which is rounded up to15830. KVAR (0x2F) This register holds the relative gain of the VAR calculation with respect to the Watt calculation. The value should always be 6444. PHADJ_A (0x2A), PHADJ_B (0x2B), PHAD_C (0x2C) These registers hold the phase correction factors for channels A, B, and C. The val ues are used by the CE to compensate for phase errors induced by current transformers. The allowed range is (2 15-1) to -(2 15-1). See the Calibration Procedure section for applicable values. If the CE is operated in Rogowski Coil mode, no phase compensation should be required. The default value is not zero and should need to be changed only slightly, if at all. See the Calibration section for details. QUANT_W (0x36), QUANT_VAR (0x37), QUANT_I (0x38) These registers hold DC values that ar e added to each calculated product in order to compensate for internal quantization (a very small amount) and external noise. These values are normally set to zero . The LSB values for these variable are listed in Table 7. Variable LSB Value Unit QUANT_W (VMAX IMAX/ In_8)* 1.04173*10-9 W QUANT_VAR (VMAX IMAX / In_8)* 1.04173*10-9 VAR QUANT_I (IMAX2 / In_82)* 5.08656*10-13 A (rms) Table 7: LSB Values for QUANT Variables Nonlinearity is most noticeable at low currents, and can result from input noise and trunc ation. Nonlinearities can be eliminated using the QUANT_W register. The error can be seen as the presence of a virtual constant noise current that becomes dominant at small load currents. The value to be used for QUANT_W can be determined by the following formula: LSB IMAXVMAX In I Verror WQUANT ⋅⋅ ⋅ ⋅ − = 8 _100_ Where error = observed error at a given voltage (V) and current (I), VMAX = voltage scaling factor, as described in section Scaling of Measured Values IMAX = current scaling factor, as described in section Scaling of Measured Values LSB = QUANT LSB value = 1.04173*10-9W

Page: 35 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Example: For a Wh measurement, an error of +1% was observed at 1A. If VMAX is 600V and IMAX = 208A, and if the measurement was taken at 240V, we determine QUANT_W as follows: 18460 10 04173 . 1 208 600 1 240100 _ 9 − = ⋅ ⋅ ⋅ − = −WQUANT The negative value obtained by the calculation will compensate for the positive error. It does not matter which current value is chosen as long as the corresponding error value is significant (5% error at 0.2A used in the above equation will produce the same result for QUANT_W). Input noise and truncation can cause si milar errors in the VAR calculati on that can be eliminated using the QUANT_VAR register. VFEED_A (0x44), VFEED_B (0x45), VFEED_C (0x46) These registers hold the com pensation factors for feedthrough used for calib rating Rogowski coils. The allowed range is (215-1) to -(215-1). See the section on Rogowski Coil Calibration for details. Registers Controlling Basic Function and Settings of the 71M6515H CONFIG (0x16) The four bytes written to this regist er determine the basic operati on of the 71M6515H. The functi on of the 28 bits used for this register are explained below: Bit 0: This bit ( VAH_SELECT) determines the method used by the post-processor for determining the apparent energy measured in VAh. If the bit is 0 (default), the calculation is based on VRMS, IRMS and the time (t) per the formula: VAh = V RMS * IRMS * t The accuracy of the result can be improv ed for low currents by setting Bit 0 to 1. The calculation is then based on the Wh and VARh values per the formula:

22 VARh Wh VAh+ =

Using the calculation method above, high accuracy can be achieved for low currents. Bit 3: This bit ( RTM_EN) enables the Real-Time Monitor function when set to 1.When used, the RTM si gnal is available at the TMUX pin. Bit 4: This bit (CE_EN) enables the CE when set to 1. The CE has to be enabled for most metering functions. Bits 7-5: These three bits (EQU) define the equation (see table below) to be implemented by the CE. EQU Watt & VAR Formula Application

0 VA IA 1 element, 2W 1ø

1* VA(IA-IB)/2 1 element, 3W 1ø

2 VA IA + VB IB 2 element, 3W 3 øDelta

3* VA (IA - IB)/2 + VC IC 2 element, 4W 3ø Delta 4* VA(IA-IB)/2 + VB(IC-IB)/2) 2 element, 4W 3ø Wye

5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye

Page: 36 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Bits 13-8: These six bits (SUM_CYCLES) define the length of the accumulation interval τ per the formula: 6 . 2520 42_ ⋅= CYCLESSUMτ Allowed values are 24 (400ms) through 60 (1000ms), unless the post-processor is disabled. Bit 8 is the LSB. It is important to note that the length of the accumulation interval, as determined by SUM_CYCLES, is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, the resulting accumulation interval is: msHzHz 75 . 99962 . 2520 2520 32768 42 60 ==⋅=τ This means that accurate time measurements should be based on the RTC, not the accumulation interval. Bit 14: This bit ( CKOUT_DISB) disables the CKOUT pin when set. The CKOUT pin can be used for diagnostics. For EMC compliance and power saving reasons, CKOUT_DISB should always be set. Bit 15: This bit ( ADC_DIS) disables the ADC when set, e.g. to save power. Of course, no metering or measuring can be performed with the ADC disabled. Bits 18-16: These three bits ( TMUX) select the source for the TMUX di agnostic output pin. For EMC compliance and power saving reasons, TMUX should be zero (default) if unused. Bit 18 TMUX2 Bit 17 TMUX1 Bit 16 TMUX0 TMUX Signal Selected for the TMUX Pin 0 0 0 0 GND 0 0 1 1 MUX_SYNC 0 1 0 2 RTM 0 1 1 3 RTC Output 1 0 0 4 CE_BUSY 1 0 1 5 XFER_BUSY 1 1 0 6 VX_OK (Comparator Output) 1 1 1 7 V3P3/2 =1.5V internal analog voltage Bits 20-19: These two bits (F_SELECT) select the phase that is to be used for frequency measurement. The frequency will be shown in bits 31-16 of the FREQ_DELTA_T register (and as bit 4 of the STATUS word – in this form as a digitized zero crossing signal). Bit 20 F_SELECT1 Bit 19 F_SELECT0 F_SELECT Phase Selected 0 0 0 Phase A 0 1 1 Phase B 1 0 2 Phase C 1 1 3 Not allowed Since the signal at t he input selected with F_SELECT is used to synchronize filters and other processing stages in the CE, accuracy for most measurements will be reduced if no voltage is pr esent at the selected phase input. Accuracy can be established by selecting the phase that carries a stable signal (A, B, or C). Bit 21: This bit ( CE_ONLY) disables the post-processor when set to 1. When the post-processor is disabled, the time- intensive computations of IPHASE, IR MS, VAh and VRMS are not performed, and therefore smaller accumulation times (SUM_CYCLES < 24) are permitted. In this case, the host is responsible for calculating IPHASE, IRMS, VAh and VRMS.

Page: 37 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Bits 23-22: These two bits ( IMAGE) select the code to be used by the CE . The CE can be operated in standard mode when using CTs and/or shunt resistor sens ors or in Rogowski mode when using Rogowski coil sensors. In order to switch the operation mode, the CE has to be disabled first by clearing the CE_EN bit. Bit 23 IMAGE 1 Bit 22 IMAGE 0 IMAGE CE Code Selected 0 0 0 Standard (CT/shunt) 0 1 1 Rogowski coil 1 0 2 Standard (CT/shunt) 1 1 3 Standard (CT/shunt) Bit 24: This bit (RESET), when reset, forces all internal states of the 71M6515H to their power-up default. Bits 26-25: These two bits ( PULSE_SLOW, PULSE_FAST ) modify the speed of the pulse generator. PULSE_SLOW and PULSE_FAST determine the factor X in the equation used for Kh as shown in the table below. PULSE_SLOW PULSE_FAST X 0 0 1.5*22 = 6 0 1 1.5*26 = 96 1 0 1.5*2-4 = 0.09375 1 (default) 1 (default) 1.5 PULSE_SLOW and PULSE_FAST will affect the operation of all four pulse outputs. See t he Pulse Generation section for details. Bits 29-27: These three bits ( IA_8X, IB_8X, IC_8X) apply an additional gain of 8 to the IA, IB, and IC channels when set to 1. This is a useful tool when very small signals are encountered, as is the case when using current shunt resistors with very low resistance while operating at low curr ents. Care must be taken to avoid cli pping. If the input to the meter exceeds IMAX/8, clipping will occur. These bits should normally be zero, unless additional gain following the ADC stage is needed. Bit 30: This bit ( DEFAULT_PPM) defines the source of te mperature com pensation. When DEFAULT_PPM is 1, the 71M6515H will automatically apply compensation coefficients derived from the st ored VREF temperature characteristics to the PPMC and PPMC2 registers. When DEFAULT_PPM is zero, the host is allowed to write its own values to the PPMC and PPMC2 registers. STATUS (0x14) The four bytes in this register reflect the status of the various measurement functions of the 71M6515H. This register is read only. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in the STATUS register is set. Bit 0: This bit (BOOTUP) signals a request from the 71M6515H to the host to be initialized. Bit 1: This bit (SAGA ), when set, indicates that the voltage applied to phase A has sagged below SAGTHR. See the for SAG register for a detailed description. Bit 2: This bit (SAGB), when set, indicates that the voltage applied to phase B has sagged below SAGTHR. Bit 3: This bit (SAGC), when set, indicates that the voltage applied to phase C has sagged below SAGTHR. Bit 4: This bit ( F0) follows the polarity of the input voltage selected with the F_SELECT bits in the CONFIG register. It represents a smoothed, filtered and squared copy of the fundamental waveform. Bit 5: This bit ( MAXV), when set, indicates that a voltage great er than the voltage lim it defined in the VI_PTHRESHOLD register had been detected in the previous accumulation interval. Bit 6: This bit ( MAXI), when set, indicates that a current greater than the current limit defined in the VI_PTHRESHOLD register had been detected in the previous accumulation interval.

Page: 38 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Bit 7: This bit (1SECI, toggles every second. It is controlled by the RTC. Bit 8: This bit ( VXEDGE), when set, indicates a change in state of VX co mparator. This bit is updated every accumulation interval. Bit 9: This bit ( DEDGE), when set, indicates a change in state of any selected DIO pin. This bit is updated every accumulation interval. Pins have to be configured to generate the DEDGE flag using the DIO_INT_CTRL bits in the D_CONFIG register. Bit 10: This bit ( XOVF), when set, indicates that the host failed to read at least one of the Wh values. Between interrupts (indicated by the READY bit in the STATUS word), the 71M6515H expects the hos t to read at least one of the WATTHR_A, WATTHR_B, or WATTHR_C values. Bit 11: This bit (READY), when set, indicates that the 71M6515H has fresh out put values ready for the host. Setting this bit in STMASK will enable the hardware interrupt output pin IRQZ. Bit 14-12: These bits (bit 12 for phase A, bit 13 for phase B, bit 14 for phase C), when set, indicate that the energy received from element A, B, or C is below the creep threshold defined in the CREEP_THRSHLD register or that the current in elements A, B, or C is below the th reshold defined in bits 15-0 of the START_THRESHLD register. The creep condition flagged by bits 14-12 of the STATUS register indicates that Wh, VARh, and IRMS measurements of element A, B, or C have been zeroed out. Consequently, accumulation did not occur. Bit 15: This bit ( CMD_IGNORED), when set, indicates that the 71M6515H ignored the last command received from the host. The reason can be any type of command incompatibility, e.g. attempts to write to a read-only register. Bit 16: This bit ( PULSEW_ERR), when set, indicates that the pulse generator PU LSEW is configured for external (host) input, but did not receive an update during the previous accumulation interval. Bit 17: This bit (PULSER_ERR), when set, indicates that the pulse generator PULSER is configured for external (host) input, but did not receive an update during the previous accumulation interval. Bit 18: This bit (PULSE3_ERR), when set, indicates that the pulse generator PULSE3 is configured for external (host) input, but did not receive an update during the previous accumulation interval. Bit 19: This bit (PULSE4_ERR), when set, indicates that the pulse generator PULSE4 is configured for external (host) input, but did not receive an update during the previous accumulation interval. STMASK (0x15) The four bytes in this register enable interrupts when the corresponding bit in the STATUS register is set. The default value for STMASK is zero. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in the STATUS register is set. Interrupts indicated by IRQZ do not necessar ily have to be synchronized with accumulation intervals. For example, the toggling of a signal app lied to the DIO pins (D0…D7), w hen the interrupt is enabled with the DIO_INT_CTRL register, can cause an interrupt at any time.

Page: 39 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Registers Controlling Temperature Measurement and Compensation DEG_SCALE (0x1C) This register holds the scale factor used to calculate the internal temperature value provided by the tem perature sensor to temperature in degrees Celsius (°C). The default value is 22721 and should not be changed. FREQ_DELTA_T (0x11) This register holds frequency and temperature information in two bytes each. 31 16 15 0 FREQUENCY (see Output Registers) DELTA_T Bits 15-0: These bits ( DELTA_T) represent the temperature information relative to the value stored in the TEMP_NOM register. One LSB is equivalent to 0.1°C. The formula used for DELTA_T is: DELTA_T = -DEGSCALE*2-22*(TEMP_RAW-TEMP_NOM) TEMP_NOM (0x13) This register holds the nominal (refer ence) temperature. During calibration, the host must write the value read from TEMP_RAW to TEMP_NOM in order to enable temperature compensation. See the Meter Calibration section for details. The temperature available in register DELTA_T is based on the difference between the cu rrent temperature, as provided in TEMP_RAW, and the reference temperature provided by TEMP_NOM. TEMP_RAW (0x12) This read-only register holds the raw temperature provided by the temperature sensor on the 71M6515H chip. During calibration, the host must write the value read from TEMP_RAW to TEMP_NOM in order to enable temperature compensation. Example: At calibration time, the raw temperature value of 853030 was read from the TEMP_RAW register and written to the TEMP_NOM register. At a later time, the raw temperature register reads 844866. The 71M6515H calculates the temperature difference to: DELTA_T = -DEGSCALE*2-22*(TEMP_RAW-TEMP_NOM) = 44 This value is interpreted as +4.4°C. PPMC1_2 (0x1B) This register holds the linear and squar ed compensation factors for the ADC te mperature compensat ion. The allowed range is (2 15 – 1) to – (215 – 1). Both words are reset to zero if TEMP_NOM equals zero. 31 16 15 0 PPMC = ADC linear factor (PPMC = 26.84 * PPM/°C ) PPMC2 = ADC quadratic factor (PPMC2 = 1374 * PPM/°C2) Changes to PPMC1_2 by the host are only allowed if the DEFAULT_PPM bit in the CONFIG register is zero. If additional temperature compensation by the host, e.g. for external components, is required, the procedure is as follows: 1) The host sets the DEFAULT_PPM bit in the CONFIG register to 1 and then reads PPMC and PPMC2. 2) The host then adds t he compensation factors to PPMC and PPMC2, resets the DEFAULT_PPM bit in the CONFIG register to 0 and then writes the modified values to PPMC and PPMC2.

Page: 40 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Y_DEG0 (0x18) This register holds the cons tant compensation factor for the RTC temperature compensati on. One LSB is equivalent to 0.1PPM. Bits 31-16: These bits (Y_CALC0) represent the constant compensation factor. Y_DEG1_2 (0x19) This register holds the linear and quadratic compensation factors for the RTC temperature compensation. 31 16 15 0 Y_CALC1 = linear compensation factor. One LSB is equi- valent to 0.01PPM/° Y_CALC2 = quadratic compensation factor. One LSB is equivalent to 0.001PPM/°C Both Y_DEG0 and Y_DEG1_2 can be used to compensate the RTC to be accurate over the whole temperature range by characterizing the crystal. Registers for Output Signals PULSEW_R_CNTS (0x41) This register contains the pulse count for the PULSEW and PULSER output pins for the past accumulation interval. The counters will be cleared at the beginning of each accumulation interval and then start counting up with each generated pulse. Bit 15-0: The counter for the PULSER (VARh) generator. Bit 31-16: The counter for the PULSEW (Wh) generator. 31 16 15 0 Counter for the PULSEW generator (Wh) Counter for the PULSER generator (VARh) At pulse rates that do not result in generation of whole counts per accumulation interval, e.g. 3 1/3 pulses, the count equivalent to the next lower natural number will be generated until the residue accumulates to a full count, i.e. the pulse sequence generated will be 3, 3, 3, 4, 3, 3, 3, 4… PULSE3_4_CNTS (0x42) This register contains the pulse count for the PULSE3 and PULSE4 output pins for the accumulation interval. The counters will be cleared at the beginning of each accumulation interval and then start counting up with each generated pulse. Bit 15-0: The counter for the PULSE4 generator. Bit 31-16: The counter for the PULSE3 generator. 31 16 15 0 Counter for the PULSE3 generator Counter for the PULSE4 generator IASQSUM (0x39), IBSQSUM (0x3A), ICSQSUM (0x3B) These registers hold the sum of the s quared current samples collected during the previous accumulation interval. The values for IASQSUM, IBSQSUM, and ICSQSUM are provided directly by the CE and are not post-processed. The magnitude of the accumulated samples is determined by: h A In IMAXLSB 2 13 10 4045 . 9 8 _ −⋅=

Page: 41 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 IASQFRACT (0x4A), IBSQFRACT (0x4B), ICSQFRACT (0x4C) These read-only registers hold the difference between the 10-bit residual squared current sum of the current accumulation interval and the 10-bit residual squared curr ent sum of the previous interval. If IASQSUM, IBSQSUM, or ICSQSUM are used to calculate current, the value obtained over several accumulation intervals will be accurate due to averaging, but the individual values will have a higher uncertainty than when using IASQFRACT, IBSQFRACT, and ICSQFRACT. The most accurate calculation of the squared current for a phase X (IXSQ) uses the formula: IXSQ = IXSQSUM + 2-10 IXSQFRACT INSQFRACT (0x4D) This register holds the difference between the 10-bit residual squared neutral currents of the current accumulation interval and the 10-bit residual squared neutral currents of the previous interval. The value can be used to improve the accuracy of the squared neutral current reading by applying the formula: INSQ = INSQSUM + 2-10 INSQFRACT INSQSUM (0x3C) This register holds the sum of the s quare of the calculated neutra l current collected during t he previous accumulation interval. The calculation is implementing the following equation: ()∑ + + = 2 1 0I I IINSQSUM The magnitude of the accumulated samples is determined by: h A In IMAXLSB 2 13 10 4045 . 9 8 _ −⋅= IPHASE_ABC (0x0F) This register holds voltage-to-current phase information for all three phases . Positive phase means lagging current (inductive load). One LSB is equivalent to 1 degree. The range is from (2 8 – 1) to –(2 8 – 1). Since the phase calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. Bits 8-0: These bits (IPHASE_C) represent the voltage-to-current phase angle in phase C. Bits 17-9: These bits (IPHASE_B) represent the voltage-to-current phase angle in phase B. Bits 26-18: These bits (IPHASE_A) represent the voltage-to-current phase angle in phase A. IRMS_A (0x0C), IRMS_B (0x0D), IRMS_C (0x0E) These registers hold the post-pr ocessed RMS current for each phase. Only t he 16 most significant bits are used. The magnitude of the values is determined by: rms A CYCLESSUM In IMAXLSB _ 8 _ 10 8781 . 69−⋅= Since the RMS calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. If higher precision is required, the host must calculate the RMS currents from the values in the IASQSUM, IBSQSUM, and ICSQSUM registers. For even higher precision, the IASQFRACT, IBSQFRACT, ICSQFRACT registers should be used.

Page: 42 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Example: The register IRMS_C reads the value 2,079,670. Assuming IM AX to be 208A, and using the formula above, we determine the RMS current of phase C to: AI RMS 0385 . 0 208 10 8781 . 62079670 =⋅⋅ = VASQSUM (0x3D), VBSQSUM (0x3E), VCSQSUM (0x3F) These registers hold the sum of the s quared voltage samples collected during the previous accumulation interval. The values for VASQSUM, VBSQSUM, and VCSQSUM are provided directly by the CE and are not post-processed. The magnitude of the accumulated samples is determined by: h VVMAXLSB 2 132 10 4045 . 9−⋅= VAH_A (0x06), VAH_B (0x07), VAH_C (0x08) These registers hold the apparent energy collected during the previous accu mulation interval. The magnitude of the accumulated samples is determined by: VAhIn IMAXVMAXLSB 8 _10 4045 . 913−⋅ = Since the VAh calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. VARH_A (0x03), VARH_B (0x04), VARH_C (0x05) These registers hold the reactive energy collected during the previous accumu lation interval. The magnitude of the accumulated samples is determined by: VARhIn IMAXVMAXLSB 8 _10 4045 . 913−⋅ = VPHASE_ABC (0x10) This register holds the phase angle between the voltages of phases A/C and A/B. The LSB is one degree. Bits 15-0: These bits (VPHASE_AC) hold the phase angle between VA and VC. Bits 31-16: These bits (VPHASE_AB) hold the phase angle between VA and VB. VRMS_A (0x09), VRMS_B (0x0A), VRMS_C (0x0B) These registers hold the post- processed RMS voltage for each phase. Only t he 16 most significant bits are used. The magnitude of the values is determined by: rms V CYCLESSUM VMAXLSB 10 8781 . 69−⋅= Since the RMS calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. If higher precision is required, t he host must calculate the RMS vo ltages from the values in the VASQSUM, VBSQSUM, and VCSQSUM registers. Example: The register VRMS_B reads the value 425,778,000. Assumi ng VMAX to be 600V, and using the formula above, we determine the RMS voltage of phase B to: VVRMS 85 . 226 600 10 8781 . 6425778000 =⋅⋅=

Page: 43 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 WH_A (0x00), WH_B (0x01), WH_C (0x02) These registers hold the real energy colle cted during the previous accumulation interval. The magnitude of the values is determined by: WhIn IMAXVMAXLSB 8 _10 4045 . 913−⋅ = Example: The register WH_A reads the value 236,675 for one accumulati on interval of one second. Assuming 600V for VMAX, 208A for IMAX, and unity gain, we determine the real energy to be: E = 236,675*600*208*9.4045*10-13 Wh = 0.0277781Wh. By multiplying with 3,600, we get 100Wh/h, which means the applied power is 100W. FREQ_DELTA_T (0x11) This register holds frequency and temperature information in two bytes each. Bits 31-16: These bits ( FREQUENCY) represent the frequenc y of the input signal selected with the F_SELECT bit of the CONFIG register. One LSB is equivalent to 0.1Hz. MAIN_EDGE_CNT (0x35) This register holds the number of zero cr ossings of the input phase selected by the F_SELECT bits in the CONFIG register detected in the previous accumulation interval. The value in MAIN_EDGE_CNT can be used by the host to correct its own RTC or to synchronize events to the line voltage. Registers Controlling Alarms and Thresholds CREEP_THRSLD (0x1D) The four bytes written to this regist er determine the creep threshold. Setting a creep threshold helps suppressing I2H, Wh and VARh readings when the values of WSUM and VARSUM are determined to be below the creep threshold. Example: The creep threshold of a meter operating with an a ccumulation interval of 1000ms is to be configured to be 15mA at 240V. The meter is using a VMAX of 600V, an IMAX of 208A, and is not using the additional gain of 8. The numerical value for the CREEP_THRSLD register is to be determined. With 15mA, the power per phase will be 3.6W, or 0.001Wh per second. With the LSB of WSUM readings given as 9.4045*10-13*VMAX*IMAX [Wh], we determine the value to: n = 0.001Wh / (9.4045*10-13*VMAX*IMAX /In_8 Wh) = 8520.2 The rounded down value of 8520 is written to the CREEP_THRSLD register. SAG (0x2E) This register holds the voltage and timing threshold for sag detection. Bits 15-0: These bits ( SAG_CNT) hold the sag count. A sag conditi on must persist for at least SAG_CNT samples before a sag alarm is generated. The allowed range is 1 to (2 15-1), and the default is 80 (31.7m s). The time period defined by SAG_CNT is: T = SAG_CNT*397μs Bits 31-16: These bits ( SAGTHR) hold the voltage threshold that is to be app lied for sag detection. The peak voltage must exceed SAGTHR once each SAG_CNT samples in order to prevent a SAG warning. One LSB is defined as: VMAXLSB 9 1610 2 8798 . 7−⋅ ⋅ =

Page: 44 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Example: A meter operating at 50Hz and 240V (RMS) is suppos ed to apply a sag threshold of 180V (RMS) for at least four periods before a sag warning is issued. VMAX is 600V. Which values are to be selected for SAG? Four periods translate to T = 4 * 20ms = 80ms. This means that SAG_CNT = T/397μs = 202. 180V (RMS) translate to 255V (peak), so SAGTHR is determined by 823 600 10 2 8798 . 7 255255 916 = ⋅ ⋅ = = −LSBSAGTHR START_THRESHLD (0x40) This register holds the voltage and current thresholds that apply to the ca lculation of frequency, zero crossings, voltage phase and energy values. If the current is below the value stored in I_START, calculation of RMS current, and energy (Wh, VARh and VAh) is suppressed. Bits 15-0: These bits ( I_START) hold the threshold to be applied for under-current. If ISQSUM< I_START , all post- processed values are set to zero for that phase. This includes reported values for Wh, VARh, VAh, IRMS, VPHASE, IPHASE, PULSER, PULSEW, PULSE3 and PULSE4. This applies only if CREEP_THRSLD is not set to zero. One LSB is defined as: h AIn IMAXLSB 2 13 10 4045 . 98 _ −⋅ ⋅ = Elements with ISQSUM< I_START will set the creep bits in the STATUS register. Bits 31-16: These bits ( V_START). hold the threshold to be applied for under-voltage. If VRMS< V_START, the values for frequency (register FREQ_DELTA_T ), zero crossings (register MAIN_EDGE_CNT), and voltage phase (register V_PHASE_ABC) are set to zero. Additionally, if VRMS< V_START, the reported value of VRMS is set to zero. One LSB is defined as: h VVMAXLSB 2 1316 2 10 4045 . 9 2−⋅ ⋅ ⋅ = Elements with VRMS< V_START will not set the creep bits in the STATUS register. VI_PTHRESHOLD (0x17) This register holds the threshold for over-voltage and over-current alarms. Bits 15-0: These bits ( I_PTHRESHOLD) hold the threshold to applied for over-cu rrent alarm. The threshold comparison is applied to the upper 16 bits of the values in IRMS: One LSB is defined as: rms A CYCLESSUM In IMAXLSB _ 8 _ 10 76 . 4506−⋅= Bits 31-16: These bits ( V_PTHRESHOLD). hold the threshold to applied for ove r-voltage alarm. The threshold comparison is applied to the upper 16 bits of the values in VRMS One LSB is defined as: rms V CYCLESSUM VMAXLSB 10 76 . 4506−⋅= Example: A meter designed with VMAX=600V and IMAX=208A is supposed to apply an overvoltage threshold of 520V (RMS) and an over-current threshold of 400A (RMS). Which values are to be selected for V_PTHRESHOLD and I_PTHRESHOLD?

Page: 45 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 893 , 14 600 10 76 . 450 520520_ 6 = = = − CYCLESSUM LSBPTHRESHOLDV 046 , 33 208 10 76 . 450 400400_ 6 = = = − CYCLESSUM LSBPTHRESHOLDI Registers Controlling Time and RTC Functions OP_TIME (0x1E) This register holds the operating time expressed in 1/100 hours. The register will be reset to zero whenever the host writes time or date to the RTC. RTC_DATE (0x20) This register holds the date information provided by the RTC. The register can be written to in order to set the date. Bits 15-8: These bits contain the year information (0 to 255). The value 0 represents the year 2000. Bits 23-16: These bits contain the month information (01 to 12). The value 01 represents January. Bits 31-24: These bits contain the day of month information (01 to 31). RTC_TIME_DAY (0x1F) This register holds the time and day information provided by t he RTC. The register can be wri tten to in order to set the time. Bits 7-0: These bits contain the day of the week (01 to 07). The value 01 represents Sunday. Bits 15-8: These bits contain the hour information (00 to 23). The value 00 represents midnight. Bits 23-16: These bits contain the minutes information (00 to 59). Bits 31-24: These bits contain the seconds information (00 to 59). Example: The value 200835 is read from the OP_TIME register. This means t hat the meter has been running since the last reset or power-up for t = 800850/100h = 8008.50h or 8,008h and 30 minutes (333.6875 days or 333 days and 16.5h). Registers Used for Test Functions RTM (0x21) This register controls the Real-Time Monitor. When the RTM_EN bit in the CONFIG register is set, the values of CE RAM locations specified with the RTM register can be routed to the TMUX pin as a serial data stream. The TMUX bits in the CONFIG register must be set to 3 in order to select the RTM output for the TMUX pin. Bits 7-0: These bits (RTM3) select the CE address for RTM3. Bits 15-8:. These bits (RTM2) select the CE address for RTM2. Bits 23-16: These bits (RTM1) select the CE address for RTM1. Bits 31-24: These bits (RTM0) select the CE address for RTM0.

Page: 46 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 SSI (0x22) This register controls the f unction of the Serial Synchronous Interface (SSI). The function of the SSI is described in the Internal Resources section of this data sheet. If the SSI is enabled (bit 23, SSI_EN, in the SSI register), a block of CNT words starting at the address BEG will be transmitted each 397µs. Bits 7-0: These bits (CNT) select the number of CE RAM address locations to be transmitted. The value in CNT must be >= Bits 15-8: These bits (BEG) define the start address of the transfer region of the CE data RAM address. Bit 16: This bit must be set to zero. Bit 17: This bit must be set to zero. Bit 18: This bit (SSI_FPOL) defines the polarity of the SFR pulse signal (0: positive, 1: negative). Bits 20-19: These bits (SSI_FSIZE) define the frame pulse format as follows: Bit 20 Bit 19 SSI_FSIZE SSI Frame Pulse Format 0 0 0 Once at beginning of SSI sequence 0 1 1 Every 8 bits 1 0 2 Every 16 bits 1 1 3 Every 32 bits Bit 21: This bit (SSI_CGATE) enables the clock to be gated. When low, the SSCLK signal is active continuously, when high, the SSCLK signal is held low when no data is being transferred. Bit 22: This bit (SSI_10M) defines the speed of the SSCLK signal: 0: 5MHz, 1: 10MHz. Bit 23: This bit (SSI_EN), when set to 1, enables the SSI interface. Registers Used for I/O Control D_CONFIG (0x1A) This register holds three bytes that are used to manipulate the DIO pins of the 71M6515H. Bits 7-0: These bits ( DIO_VALUE) form the data register for the DIO pins D0 through D7. When a byte is written to DIO_VALUE, the pins configured as outputs (using the D_DIR register) will change their state accordingly. Pins configured as inputs will ignore the byte written to DIO_VALUE. Reading DIO_VALUE will return a byte that reflects the state of all pins regardless whether they are configured as inputs or outputs. Bits 15-8: These bits are not used Bits 23-16: These bits (D_DIR) define the data direction. Bit 0 controls the D0 pin, bit 7 controls the D7 pin. Setting the bit corresponding to a pin to 1 makes the pin an output, clearing it to 0 makes it an input. Bits 31-24: These bits (DIO_INT_CTRL) form a mask enabling the DEDGE interrupt (bit 9 of the STATUS word register). Bit 8 controls the D0 pin, bit 15 controls the D7 pin. Setting the bit corresponding to a pin to 1 enables the DEDGE interrupt, clearing the bit disables the interrupt. If the bit in DIO_INT_CTRL is set and a transition from high to low or from low to high occurs, the DEDGE interrupt bit in the STATUS word register will be set in the following accumulation interval.

Page: 47 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Example: DIO pins D0 through D3 are to be configured as out puts, while D4 through D7 are to be inputs. DIO7 must generate a DEDGE interrupt when the input value changes, and D0 through D3 must apply the hexadecimal pattern 0x05. This makes the selection for the D_CONFIG registers as follows: DIO_INTCTRL = 0x80, D_DIR = 0x0F, DIO_VALUE = 0x05 The values are combined into the 32-bit pattern 0x800F0005. Example: D0 through D5 are to be configured as outputs, while D6 and D7 ar e to be inputs. D6 and D7 must generate a DEDGE interrupt when their input value changes. This makes the selection for the D_CONFIG registers as follows: DIO_INTCTRL = 0xC0, D_DIR = 0x3F The values are combined into the 32-bit pattern 0xC03F0000.

Page: 48 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Registers in Numerical Order Address Name Address Name Address Name 0x00 WH_A 0x20 RTC_DATE 0x40 START_THRESHLD 0x01 WH_B 0x21 RTM 0x41 PULSEW_R_CNTS 0x02 WH_C 0x22 SSI 0x42 PULSE3_4_CNTS 0x03 VARH_A 0x23 RESERVED 0x43 PULSE_SRCS 0x04 VARH_B 0x24 CAL_IA 0x44 VFEED_A 0x05 VARH_C 0x25 CAL_VA 0x45 VFEED_B 0x06 VAH_A 0x26 CAL_IB 0x46 VFEED_C 0x07 VAH_B 0x27 CAL_VB 0x47 0x08 VAH_C 0x28 CAL_IC 0x48 0x09 VRMS_A 0x29 CAL_VC 0x49 0x0A VRMS_B 0x2A PHADJ_A 0x4A IASQFRACT 0x0B VRMS_C 0x2B PHADJ_B 0x4B IBSQFTACT 0x0C IRMS_A 0x2C PHADJ_C 0x4C ICSQFRACT 0x0D IRMS_B 0x2D WRATE 0x4D INSQFRACT 0x0E IRMS_C 0x2E SAG 0x4E GAIN_ADJ 0x0F IPHASE_ABC 0x2F KVAR 0x10 VPHASE_ABC 0x30 APULSEW 0x11 FREQ_DELTA_T 0x31 APULSER 0x12 TEMP_RAW 0x32 APULSE3 0x13 TEMP_NOM 0x33 APULSE4 0x14 STATUS 0x34 PULSE_WIDTH 0x15 STMASK 0x35 MAIN_EDGE_CNT 0x60 CE_PROG_ADDR 0x16 CONFIG 0x36 QUANT_W 0x61 CE_DATA_ADDR 0x17 VI_PTHRESH 0x37 QUANT_VAR 0x62 CE_PROG 0x18 Y_DEG0 0x38 QUANT_I 0x63 CE_DATA 0x19 Y_DEG1_2 0x39 IASQSUM 0x64 CE_PROG_INC 0x1A D_CONFIG 0x3A IBSQSUM 0x65 CE_DATA_INC 0x1B PPMC1_2 0x3B ICSQSUM 0x1C DEG_SCALE 0x3C INSQSUM 0x1D CREEP_THRSLD 0x3D VASQSUM 0x1E OP_TIME 0x3E VBSQSUM 0x1F RTC_TIME_DAY 0x3F VCSQSUM

Page: 52 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Methods of Control Two different methods of control can be used by the host processor: 1) Synchronization using the IRQZ pin of the 71M6515H (interrupt or DIO pin polling method, see Figure 20): a. Interrupt Method: The IRQZ pin of the 71M6515H is connected to a pin of the host processor that can generate an interrupt for the host processor. This is the easiest method for synchronization between the 71M6515H and the host. The CONFIG register of the 71M6515H is set up to generate an interrupt on the IRQZ pin whenever fresh data are ready, and the interrupt service routine of the host processor reads the fresh data out of the 71M6515H. b. DIO pin polling method : The IRQZ pin of the 71M6515H is connected to a DIO pin of the host processor. The host processor polls the status of the DIO pin as frequently as possible or through a timer-based polling method. The CONFIG register of the 71M6515H is set up to have the IRQZ pin to go low on every fresh data ready status, and the timer-serviced polling of the host processor will monitor the status of the DIO pin and initiate the serial communication when IRQZ is detected. For this method to be effective, the firmware of the host processor must maintain the timer interrupt to be the highest priority, followed by the serial communications priority. 2) Polling the READY bit in the STATUS word of the 71M6515H (status polling method, see Figure 21). This method requires that the host processor utilizes a timer with 1ms to 5ms resolution tied into the highest-priority interrupt. The interrupt service routine must initiate reading the STATUS register, preferably at least every 10ms, in order to monitor the READY bit, but the host processor must wait for the response of each status request. Otherwise, the STATUS register read operations will be stacked in the 71M6515H resulting in multiple responses. If a delayed response is received upon a STATUS register read, the host processor will know that the 71M6515H is within its post-processing period, which makes it necessary hat the host waits for the response. Every time the READY bit in the STATUS register is not set, indicating that data is not available, the host should poll again 200ms 400ms 80ms read command from host read command from host post-processor active post-processor active 6515H data 6515H data time80ms IRQZ 300ms 500ms Figure 20: Timing Diagram (Using IRQZ, SUM_CYCLES = 12) The communication between the 71M6515H and the host processor can always be reset without disturbing the metering function by utilizing the UARTCSZ and BAUDRATE pins. Configuring the BAUDRATE pi n without resetting the UART buffers is not recommended. The UART of the 71M 6515H can be “reset” by pulling the UARTCSZ pin low. This will force the UART back into the default configuration while clearing all buffers (UART buffers, UART-related buffers in the firmware).

Page: 53 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 1000ms 2000ms 330ms read commands from host read commands from host 6515H not ready 6515H not ready post-processor active post-processor active 330ms 6515H data 6515H data time Figure 21: Timing Diagram (Host Polling) Communication Steps for Interrupt Method: The following is a list of commands required from the host processor to establish communication with the 71M6515H. 1) Establish host baud rate and data format as required by the 71M6515H. 2) Configure the DIO pins (D0… D7), if required, using the D_CONFIG register 3) Configure the 71M6515H by selecting the CE image (bits 23-22), equat ion (bits 7-5), pulse rate (bits 26-25), followed by enabling the CE (bit 4 in the CONFIG register). The bit pattern sent to CONFIG should have all bits set to their default state, as given in the Register Table. 4) Write the TEMP_RAW value obtained at calibration into the TEM_NOM register to enable temperature compensation. 5) Write the calibration coefficients into registers CAL_IA, CAL_VA, CAL_IB, CAL_VB, CAL_C, CAL_VC, PHADJ_A, PHADJ_B, PHADJ_C. Write calibration values to the VFEED_A/B/C registers if the Rogowski image is used. 6) Configure WRATE with the value required to generate the desired pulse rate. 7) Establish creep, sag and over/under voltage/current th resholds, if necessary, by writing values to the CREEP_THRSLD, SAG, VI_PTHRESH, and VI_THRSHLD registers. 8) Set the READY bit in the status mask STMASK in order to enable the generation of interrupts on the IRQZ pin. 9) Read at least one accumulated value register ( WATTH_X, or VAH_X, or VARH_X). 10) Wait for the IRQZ pin to go low. 11) After receiving the interrupt, read at least one accumulated value register ( WATTH_X, or VAH_X, or VARH_X) in order to maintain interrupt generation. Read the bits in the STATUS word to detect potential faul ts (overflow signaled by the XOVF flag or uninitialized condition signaled by the BOOTUP flag) or warnings and ev ents (sag, creep, excessive voltage or current, DIO signal changes). If necessary, take corrective action. 12) After reading the required data from the 71M6515H, configuration changes should be made, if necessary. These con- figuration changes should be completed before the pre-processing period begins again.

Page: 54 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Timing The fundamental factor for a ll timing considerations is SUM_CYCLES, which determines the length of the accumulation interval for the 71M6515H per the equation: Hz CYCLESSUM 6 . 2520 42_ ⋅=τ The default setting for SUM_CYCLES is 60, which yields an accumulation interval close to 1,000ms. A conservative minimum number for SUM_CYCLES is 24, which yields an accumulation interval close to 400ms. Both calculations by the post-processor in the 71M6515H and the communication bet ween 71M6515H and the host have to be completed within the accumulation interval. If an accumulation interval has passed, and the energy values have not been read by the host, they are lost forever. In order to analyze the timing of the co mmunication between the 71M6515H and the host, it is useful to know the basic timing requirements of the post-processor of the 71M6515H. Some timing parameters are listed in Table 8. CE_ONLY VAh Calculation Resulting Calculation Time Disabled Vector method:

22 VARh Wh VAh+ = 350ms

Disabled Vrms*Irms method 80ms Enabled X 40ms Table 8: Post-processor Timing As can be seen in Table 8, the calculation time can be great ly reduced if the VAh values ar e calculated using the method of multiplying Vrms by Irms (by resetting bit 0 in the CONFIG register), which is less accurate at low currents. Further improvement can be achieved by disabling the post-processor using the CE_ONLY bit in the CONFIG register. This is possible for applications where the registers IPHASE, IRMS, VAh and VRMS are not required. It becomes clear now that the minimum value of 24 for SUM_CYCLES, equivalent to a 400ms accumulation interval, accom- modates the worst-case scenario, using the vector method, which requires 350ms post-processing time. This setting leaves around 50ms for the communication to take place between the 71M6515 and the host. If the simpler Irms*Vrms method is chosen for VAh, a lower value can be selected for SUM_CYCLES. Lower values for SUM_CYCLES, for example 12, yielding a 200ms accumulation interval, are possible, leaving still 120ms for host communications, as long as the Vrms*Irms method for VAh is used. Some other timing parameters are listed in Table 9. Parameter Value Comment Time from power-up to UART being functional 370ms ±10% Time from HW reset to UART being functional 370ms ±10% Time from soft reset to UART being functional 245ms ±10% Soft reset = RESET bit in CONFIG register is set high. Time from UARTCSZ pin low to UART being functional 20ms UARTCSZ is polled just before the 71M6515H checks its data buffer for a command. This means that the command latency specified in the Electrical Specifi- cations section also applies to the UARTCSZ pin. Table 9: UART Timing Parameters

Page: 55 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 PACKAGE OUTLINE 11.7 12.3 0.60 Typ. 1.40 1.60 11.7 12.3 0.00 0.20 9.8 10.2 0.50 Typ. 0.14 0.28 PIN No. 1 Indicator NOTE: Controlling dimensions are in mm

Ordering Information

PART DESCRIPTION ORDER NO. PACKAGING MARK 71M6515H 64-Pin LQFP Lead-Free, 0.1% accuracy 71M6515H-IGT/F 71M6515H-IGT 71M6515H 64-Pin LQFP Lead-Free, 0.1% accuracy, T&R 71M6515H-IGTR/F 71M6515H-IGT

REVISION HISTORY

Rev. 1.0 October 26, 2005 First publication. Rev. 1.1 December 11, 2006 Changed capacitor values for XIN/XOUT Corrected addresses for CE_DATA and made addresses CE_DATA etc. visible in table “Registers in Numerical Order”. Changed frequency range to 46-64Hz and “Real-time clock for TOU” to “Real-time clock with temperature compensation” on title page. Added complete chapter on communication between host and 6515H. Changed pin name V1 to VFLT in Electrical Specification. Consolidated spelling for CREEP_THRSLD register. Added explanation for X in formula for WRATE. Added information on processing time for registers involving post-processing. Changed default value for WRATE to 683. Deleted note on low-pass filter in the CE in CONFIG register description. Added note at CONFIG register description stating that phase with stable voltage can be selected with F_SELECT to avoid inaccurate measurements and note stating that PULSE_SLOW and PULSE_FAST affect all four pulse sources. Added diagram “Connections between 71M6515H and host”. Rev. 1.2 March 15, 2007 Added I/O Equivalent Circuit diagrams and circuit type numbers in Pin Descriptions. Added note in Pin Descriptions stating that the voltage at RX must not exceed 3.6V. Added VREF aging data. Clarified polarity of SSDAT and SSCLK pins. Rev. 1.3 August 17, 2007 Changed recommended value for capacitors at XIN/XOUT to 22pF. Changed recommended crystal to ECS ECX-3TA series. Added note on exact length of default accumulation interval. Corrected bit locations for D_CONFIG register. Added note in pin description for D0-D7 and Digital I/O” section: D0 through D7 float after reset or power-up and are configured as outputs and driven low 140ms after RESETZ goes high. Updated default values for VIPTHRESH and VI_THRESH. Rev. 1.4 March 5, 2008 Changed pin and register names to PULSEW and PULSER and updated block diagram (Figure 2), updated pin-out diagram with corrected pin names. Removed COMPARATOR table in ELECTRICAL SPECIFICATIONS. Changed note for SRDY in pin description table to “SRDY should be tied to ground”, deleted Figure 13 (SRDY function) and removed all text describing the function of SRDY (except that SRDY should be grounded), deleted Figure 13 (SSI Timing w/ SRDY) and removed references to SRDY in Figure 12. Consolidated spelling of Y_CALC etc. constants in section “Temperature Com- pensation for the Crystal and RTC” and in the register tables. Added reference to fast calibration procedure (AN_651X_022). Added diagrams for metering configurations. Improved Table 6 and explanation of PULSE_SRC register. Changed capacitor values for XIN/XOUT to 27pF and added recommended load capacitance value (12.5pF). Changed register name at location 0x38 from QUANT_V to QUANT_I. Removed non lead-free packages from Ordering Information. Updated Teridian street address. Added text at explanation of bits 14-12 of the STATUS register stating that these bits are also set when the current is below the threshold defined by bits 15-0 of the START_THRESHLD register. Added at explanation of START_THRESHLD : “Elements with VRMS< V_START will not set the creep bits in the STATUS register” and “Elements with ISQSUM< I_START will set the creep bits in the STATUS register”. Added value for Rθ JA in Electrical Specification.

Page: 57 of 57 © 2005-2008 TERIDIAN Semiconductor Corporation V1.4 Final Data Sheet: This Final Data Sheet is proprietary to TERIDIAN Semi conductor Corporation (TSC) and se ts forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligati on regarding future manufacture, unless agreed t o in writing. If and when manufactured and sold, this product is sold s ubject to the terms and conditions of sale supplied at the ti me of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notic e. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com 3/13/2008

Product Information

71M6515H specifications and overview.

Summary

Energy Meter IC

Description

Energy Meter IC

Source title 71M6515H Datasheet(PDF) - Teridian Semiconductor Corporation

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71M6515H

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71M6515H TERIDIAN | Alldatasheet

Document overview

Technical content

FEATURES

64 PINS -- 64 TQFP

0 LSB

64 GNDD

63 I 8

0 Deg

60 Deg

180 Deg

90 Deg

150 Deg

270 Deg

0 VA IA 1 element, 2W 1ø IA VA - - - -

2 VA IA + VB IB 2 element, 3W 3 øDelta IA VA IB VB - -

5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye IA VA IB VB IC VC

0 VA IA (1 element, 2W 1φ) VA*IA - - IA - -

1 VA*(IA-IB)/2

2 VA*IA + VB*IB

214 Calibration

26000 Alarms and Thresholds

22 VARh Wh VAh+ =

0 VA IA 1 element, 2W 1ø

2 VA IA + VB IB 2 element, 3W 3 øDelta

5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye

22 VARh Wh VAh+ = 350ms

Ordering Information

REVISION HISTORY

71M6515H specifications and overview.

More parts from the same family.

2 VAIA + VBIB