7164L20DG8

IDT7164S_16 IDT | Alldatasheet

Document overview

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Technical content

Features

◆ ◆◆ ◆◆ High-speed address/chip select access time – Military: 20/25/35/45/55/70/85/100ns (max.) – Industrial: 20/25ns (max.) – Commercial: 20/25ns (max.) ◆ ◆◆ ◆◆ Low power consumption ◆ ◆◆ ◆◆ Battery backup operation – 2V data retention voltage (L Version only) ◆ ◆◆ ◆◆ Produced with advanced CMOS high-performance technology ◆ ◆◆ ◆◆ Inputs and outputs directly TTL-compatible ◆ ◆◆ ◆◆ Three-state outputs ◆ ◆◆ ◆◆ Available in 28-pin DIP, CERDIP and SOJ ◆ ◆◆ ◆◆ Military product compliant to MIL-STD-883, Class B ◆ ◆◆ ◆◆ Green parts available, see ordering information

Description

The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K x 8. It is fabricated using high-performance, high-reliability CMOS tech- nology. Address access times as fast as 20ns are available and the circuit offers a reduced power standby mode. When CS1 goes HIGH or CS2 goes LOW, the circuit will automatically go to, and remain in, a low-power stand- by mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT7164 is packaged in a 28-pin 300 mil CERDIP, a 28-pin 600 mil CERDIP, 300mil Plastic DIP and 300mil SOJ Military grade product is manufactured in compliance with MIL-STD- 883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Functional Block Diagram ADDRESS DECODER 65,536 BIT MEMORY ARRAY I/O CONTROL 2967 drw 01WE CS VCC GND I/O0 I/O7 CONTROL LOGICOE CS1 A12 0 7 IDT7164S IDT7164L CMOS Static RAM 64K (8K x 8-Bit)

CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Pin Descriptions Absolute Maximum Ratings(1) Truth Table(1,2,3) Recommended Operating Temperature and Supply Voltage Recommended DC Operating Conditions Name Description A0 - A 12 Address I/O0 - I/O7 Data Input/Output CS1 Chip Select CS2 Chip Select WE Write Enable OE Output Enable GND Ground VCC Power 2967 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed VCC + 0.5V. Symbol Rating Com'l. Mil. Unit VTE RM(2) T erminal Voltage with Respect to GND T A Operating Temperature 0 to +70 -55 to +125 oC TBIAS Temperature Under Bias -55 to +125 -65 to +135 oC TSTG Storage Temperature -55 to +125 -65 to +150 oC PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 2967 tbl 02 NOTES: 1. CS 2 will power-down CS1, but CS1 will not power-down CS2. 2. H = V IH, L = VIL, X = don't care. 3. V LC = 0.2V, VHC = VCC - 0.2V WE CS 1 CS2 OE I/O Function X H X X High-Z Deselected - Standby (I SB) X X L X High-Z Deselected - Standby (I SB) X VHC VHC or VLC X High-Z Deselected - Standby (I SB1) XX V LC X High-Z Deselected - Standby (I SB1) H L H H High-Z Output Disabled HL H L D ATA OUT Read Data LLHX D ATAIN Write Data 2967 tbl 03 Grade Temperature GND Vcc Military -55 OC to +125OC0 V 5 V ± 10% Industrial -40 OC to +85 OC0 V 5 V ± 10% Commercial 0 OC to +70OC0 V 5 V ± 10% 2967 tbl 04NOTE: 1. V IL (min.) = –1.5V for pulse width less than 10ns, once per cycle. Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input HIGH Voltage 2.2 ____ VCC + 0.5 V VIL Input LOW Voltage -0.5 (1) ____ 0.8 V 2967 tbl 05 Pin Configurations DIP/SOJ Top View 2967 drw 02 A12 CD28 SD28 PJG28 PTG28 I/O0 I/O1 VCC WE A11 OE A10 CS1 I/O7 I/O2 GND I/O6 I/O5 I/O4 I/O3 NC CS2

6.42 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Capacitance (TA = +25°C, f = 1.0MHz) NOTE: 1. This parameter is determined by device characterization, but is not production tested. Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance V IN = 0V 8 pF CI/O I/O Capacitance V OUT = 0V 8 pF 2967 tbl 06 NOTES: 1. All values are maximum guaranteed values. 2. f MAX = 1/t RC (all address inputs are cycling at f MAX); f = 0 means no address input lines are changing. l o b m ySr e t e m a r aPr e w o P 0 2 S 4 6 1 7 0 2 L 4 6 1 7 5 2 S 4 6 1 7 5 2 L 4 6 1 7 I 1 C C t n e r r u C y l p p u S r e w o P g n i t a r e p O S C1 V =L I S C ,2 V =H I n e p O s t u p t u O , V C C f , . x a M == 0 ) 2 ( S0 010 110 110 90 110 1 1 A m L0 90 010 010 90 010 0 1 I 2 C C t n e r r u C g n i t a r e p O c i m a n y D S C1 V =L I S C ,2 V =H I n e p O s t u p t u O , V C C f = f , . x a M =X A M) 2 ( S0 710 710 810 710 710 8 1 A m L0 510 510 610 510 510 6 1 I B S t n e r r u C y l p p u S r e w o P y b d n a t S , ) l e v e L L T T (S C1 > V H I S C ,2 < V L I, V , n e p O s t u p t u OC C f = f , . x a M =X A M) 2 ( S0 20 20 20 20 20 2 A m L 335335 I 1 B S t n e r r u C y l p p u S r e w o P y b d n a t S l l u F 0 = f , ) l e v e L S O M C () 2 (V ,C C . x a M = . 1 S C1 > V C H S C d n a2 > V C H r o , S C . 22 < V C L S5 15 10 25 15 10 2 A m L2 .02 .01 2 .02 .01 7 0 l b t 7 6 9 2 l o b m ySr e t e m a r aPr e w o P 5 3 S 4 6 1 7 5 3 L 4 6 1 7 5 4 S 4 6 1 7 5 4 L 4 6 1 7 5 5 S 4 6 1 7 5 5 L 4 6 1 7 0 7 S 4 6 1 7 0 7 L 4 6 1 7 0 0 1 / 5 8 S 4 6 1 7 0 0 1 / 5 8 L 4 6 1 7 I 1 C C t n e r r u C y l p p u S r e w o P g n i t a r e p O S C1 V =L I S C ,2 V =H I n e p O s t u p t u O , V C C f , . x a M == 0 ) 2 ( S0 010 010 010 010 0 1 A m L0 90 90 90 90 9 I 2 C C t n e r r u C g n i t a r e p O c i m a n y D S C1 V =L I S C ,2 V =H I n e p O s t u p t u O , V C C f = f , . x a M =X A M) 2 ( S0 610 610 610 610 6 1 A m L0 410 315 210 210 2 1 I B S t n e r r u C y l p p u S r e w o P y b d n a t S , ) l e v e L L T T (S C1 > V H I S C ,2 < V L I, V , n e p O s t u p t u OC C f = f , . x a M =X A M) 2 ( S0 20 20 20 20 2 A m L 5555 5 I 1 B S t n e r r u C y l p p u S r e w o P y b d n a t S l l u F 0 = f , ) l e v e L S O M C () 2 (V ,C C . x a M = . 1 S C1 > V C H S C d n a2 > V C H r o , S C . 22 < V C L S0 20 20 20 20 2 A m L 1111 1 8 0 l b t 7 6 9 2

Figure 2. AC Test Load

1. This parameter is guaranteed by device characterization, but is not production tested.

ICCDR Data Retention Current MIL.

6.42 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested. l o b m ySr e t e m a r a P 0 2 S 4 6 1 7 0 2 L 4 6 1 7 5 2 S 4 6 1 7 5 2 L 4 6 1 7 t i n U. n iM. x aM. n iM. x a M e l c y C d a e R t C R e m i T e l c y C d a eR0 2 _ _ _ _ 5 2 _ _ _ _ s n t A A e m i T s s e c c A s s e r d d A _ _ _ _ 9 1 _ _ _ _ 52s n t 1 S C A) 1 ( e m i T s s e c c A 1 - t c e l e S p i h C _ _ _ _ 0 2 _ _ _ _ 52s n t 2 S C A) 1 ( e m i T s s e c c A 2 - t c e l e S p i h C _ _ _ _ 5 2 _ _ _ _ 03s n t 2 , 1 Z L C) 2 ( Z - w o L n i t u p t u O o t 2 , 1 - t c e l e S p i hC5 _ _ _ _ 5 _ _ _ _ s n t E O d i l a V t u p t u O o t e l b a n E t u p t u O_ _ _ _ 8 _ _ _ _ 21s n t Z L O) 2 ( Z - w o L n i t u p t u O o t e l b a n E t u p t uO0 _ _ _ _ 0 _ _ _ _ s n t 2 , 1 Z H C) 2 ( Z - h g i H n i t u p t u O o t 2 , 1 - t c e l e S p i h C_ _ _ _ 9 _ _ _ _ 31s n t Z H O) 2 ( Z - h g i H n i t u p t u O o t e l b a s i D t u p t u O_ _ _ _ 8 _ _ _ _ 01s n t H O e g n a h C s s e r d d A m o r f d l o H t u p t uO5 _ _ _ _ 5 _ _ _ _ s n t U P) 2 ( e m i T p U r e w o P o t t c e l e S p i hC0 _ _ _ _ 0 _ _ _ _ s n t D P) 2 ( e m i T n w o D r e w o P o t t c e l e s e D p i h C_ _ _ _ 0 2 _ _ _ _ 52s n e l c y C e t i r W t C W e m i T e l c y C e t i rW0 2 _ _ _ _ 5 2 _ _ _ _ s n t 2 , 1 W C e t i r W - f o - d n E o t t c e l e S p i hC5 1 _ _ _ _ 8 1 _ _ _ _ s n t W A e t i r W - f o - d n E o t d i l a V s s e r d dA5 1 _ _ _ _ 8 1 _ _ _ _ s n t S A e m i T p u - t e S s s e r d dA0 _ _ _ _ 0 _ _ _ _ s n t P W h t d i W e s l u P e t i rW5 1 _ _ _ _ 1 2 _ _ _ _ s n t 1 R W ( e m i T y r e v o c e R e t i r WS C1, E W)0 _ _ _ _ 0 _ _ _ _ s n t 2 R W S C ( e m i T y r e v o c e R e t i r W2)5 _ _ _ _ 5 _ _ _ _ s n t Z H W) 2 ( Z - h g i H n i t u p t u O o t e l b a n E e t i r W_ _ _ _ 8 _ _ _ _ 01s n t W D p a l r e v O e m i T e t i r W o t a t aD0 1 _ _ _ _ 3 1 _ _ _ _ s n t 1 H D e m i T e t i r Wm o r f d l o H a t aD( S C1, E W)0 _ _ _ _ 0 _ _ _ _ s n t 2 H D S C ( e m i T e t i r Wm o r f d l o H a t a D2)5 _ _ _ _ 5 _ _ _ _ s n t W O) 2 ( e t i r W - f o - d n E m o r f e v i t c A t u p t uO4 _ _ _ _ 4 _ _ _ _ s n 2 1 l b t 7 6 9 2

CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested. l o b m ySr e t e m a r a P 5 3 S 4 6 1 7 5 3 L 4 6 1 7 5 4 S 4 6 1 7 5 4 L 4 6 1 7 5 5 S 4 6 1 7 5 5 L 4 6 1 7 0 7 S 4 6 1 7 0 7 L 4 6 1 7 0 0 1 / 5 8 S 4 6 1 7 0 0 1 / 5 8 L 4 6 1 7 e l c y C d a e R t C R e m i T e l c y C d a eR5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8_ _ _ _ s n t A A e m i T s s e c c A s s e r d d A_ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 58s n t 1 S C A) 1 ( e m i T s s e c c A 1 - t c e l e S p i h C_ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 58s n t 2 S C A) 1 ( e m i T s s e c c A 2 - t c e l e S p i h C_ _ _ _ 0 4 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 58s n t 2 , 1 Z L C) 2 ( Z - w o L n i t u p t u O o t 2 , 1 - t c e l e S p i hC5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t E O d i l a V t u p t u O o t e l b a n E t u p t u O_ _ _ _ 8 1 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ 04s n t Z L O) 2 ( Z - w o L n i t u p t u O o t e l b a n E t u p t uO0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t 2 , 1 Z H C) 2 ( Z - h g i H n i t u p t u O o t 2 , 1 - t c e l e S p i h C_ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 53s n t Z H O) 2 ( Z - h g i H n i t u p t u O o t e l b a s i D t u p t u O_ _ _ _ 5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 53s n t H O e g n a h C s s e r d d A m o r f d l o H t u p t uO5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t U P) 2 ( e m i T p U r e w o P o t t c e l e S p i hC0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t D P) 2 ( e m i T n w o D r e w o P o t t c e l e s e D p i h C_ _ _ _ 5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 58s n e l c y C e t i r W t C W e m i T e l c y C e t i rW5 3 _ _ _ _ 5 4 _ _ _ _ 5 5 _ _ _ _ 0 7 _ _ _ _ 0 0 1 / 5 8_ _ _ _ s n t 2 , 1 W C e t i r W - f o - d n E o t t c e l e S p i hC5 2 _ _ _ _ 3 3 _ _ _ _ 0 5 _ _ _ _ 0 6 _ _ _ _ 5 7 _ _ _ _ s n t W A e t i r W - f o - d n E o t d i l a V s s e r d dA5 2 _ _ _ _ 3 3 _ _ _ _ 0 5 _ _ _ _ 0 6 _ _ _ _ 5 7 _ _ _ _ s n t 1 R W ( e m i T y r e v o c e R e t i r WS C1, E W)0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t 2 R W S C ( e m i T y r e v o c e R e t i r W2)5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t Z H W) 2 ( Z - h g i H n i t u p t u O o t e l b a n E e t i r W_ _ _ _ 4 1 _ _ _ _ 8 1 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 53s n t W D p a l r e v O e m i T e t i r W o t a t aD5 1 _ _ _ _ 0 2 _ _ _ _ 5 2 _ _ _ _ 0 3 _ _ _ _ 5 3 _ _ _ _ s n t 1 H D e m i T e t i r W m o r f d l o H a t aD( S C1, E W)0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ 0 _ _ _ _ s n t 2 H D S C ( e m i T e t i r W m o r f d l o H a t a D2)5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ 5 _ _ _ _ s n t W O) 2 ( e t i r W - f o - d n E m o r f e v i t c A t u p t uO4 _ _ _ _ 4 _ _ _ _ 4 _ _ _ _ 4 _ _ _ _ 4 _ _ _ _ s n 3 1 l b t 7 6 9 2

6.42 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. Timing Waveform of Read Cycle No. 2(1,2,4) Timing Waveform of Read Cycle No. 3(1,3,4) ADDRESS CS1 OE DATAOUT CS2 tRC tAA tOH tACS2 tCLZ2(5) tOE tACS1 tCLZ1(5) tOLZ (5) tCHZ2(5) tOHZ (5) tCHZ1(5) DATA VALID 2967 drw 05 2967 drw 06 ADDRESS DATAOUT tRC tAA tOH tOH DATA VALID DATAOUT tACS2 (5) CS1 CS2 tCLZ2 tACS1 (5)tCLZ1 tPU tPD ICC ISB tCHZ2(5) tCHZ1(5) DATA VALID POWER SUPPLY CURRENT 2967 drw 07

CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5) Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1) NOTES: 1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS 2. 2. t WR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS 2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS1 LOW transition or CS 2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t WP or (t WHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified t WP. 6. Transition is measured ±200mV from steady state. ADDRESS tWC tWHZ(6) 2967 drw 08 CS1 DATAOUT CS2 tAS tAW tWR1(2) WE tWP tOW(6) DATAIN tDH1,2tDW DATA VALID (3) (5) ADDRESS CS1 CS2 tWC tAS WE tCW tWR2(2) tAW DATAIN tDH1,2tDW DATA VALID tWR1(2) (4) 2967 drw 09

6.42 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges

Ordering Information

Low VCC Data Retention Waveform 2967 drw 10 DATA RETENTION MODE 4.5V 4.5V VDR ≥ 2V VIH VIH tRtCDR VCC CS VDR X Power XX Speed XXX Package X Process/ Temperature Range Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant with MIL-STD-883, Class B Y TP D TD 300 mil SOJ (PJG28) 300 mil Plastic DIP (PTG28) 600 mil CERDIP (CD28) 300 mil CERDIP (SD28) S L Standard Power Low Power Device Type 7164 2967 drw 11 X G(2) Green Blank Tube Tape and Reel X 100 Commercial, Industrial & Military Commercial, Industrial & Military Military Only Military Only Military Only Military Only Military Only Military Only Speed in nanoseconds NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office.

CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Datasheet Document History 01/13/00 Updated to new format Pp. 1, 2, 3, 5, 10 Added Industrial Temperature range offerings Pp. 1, 3, 9 Removed commercial 70ns speed grade offering Pp. 1, 3, 6, 10 Added 100ns speed grade specification details Pg. 3 Revised notes and footnotes in DC Electrical tables Pp. 5, 6 Revised notes and footnotes in AC Electrical tables Pg. 8 Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes Pp. 9, 10 Separated Ordering Information into commercial, industrial, and military offerings Pg. 11 Added Datasheet Document History 08/09/00 Not recommended for new designs 02/01/01 Removed "Not recommended for new designs" 12/07/01 Pg. 10 Add PJ28 to Industrial temperature. 09/30/04 Pg. 9,10 Added "restricted hazardous substance device" to ordering information. 11/16/06 Pg.3 Added industrial temp power limits for 20ns part. Changed power limits for 25ns part for commercial and industrial. Changed power limits for commercial and industrial for 35ns part. Pg.10 Added 20ns part to ordering information. Refer to PCN SR-0602-01 02/20/07 Pg. 9, 10 Added L generation die step to data sheet ordering information. 04/27/11 Pg. 1-3,5,6,9 Obsoleted 24-pin 600 mil, 15ns for Commercial and 35ns for Industrial & Commercial. Added Tape and Reel to Ordering information and updated description of Restricted hazardous substance device to Green. 10/30/13 Pg. 1 In the Description: Removed reference to IDT's fabrication and removed "the latest revision of". 12/06/16 Pg. 2 Removed half moon from the pin configuration diagram for all packages to reflect pin 1 orientation and added dot at pin 1 Updated the package codes in the DIP/SOJ pin configuration Pg. 9 Updated the package codes in the Ordering Information Updated the BLANK designator from "Tube and Tray" to "Tube" in Ordering Information Pg. 1 & 9 Added standard footnotes to Ordering Information with instructions for ordering Industrial temp and Green parts The IDT logo is a registered trademark of Integrated Device Technology, Inc. CORPORATE HEADQUARTERS for SALES:

6024 Silver Creek Valley Road 800-345-7015 or

San Jose, CA 95138 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: sramhelp@idt.com 408-284-4532