IDT7130SA_16 IDT | Alldatasheet

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Technical content

Features

◆◆ ◆◆ ◆◆ ◆◆ High-speed access – Commercial: 20/25/35/55/100ns (max.) – Industrial: 25/55/100ns (max.) – Military: 25/35/55/100ns (max.) ◆ Low-power operation – IDT7130/IDT7140SA — Active: 550mW (typ.) — Standby: 5mW (typ.) – IDT7130/IDT7140LA — Active: 550mW (typ.) — Standby: 1mW (typ.) ◆ MASTER IDT7130 easily expands data bus width to 16-or- more-bits using SLAVE IDT7140 Functional Block Diagram NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor. ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ ◆◆ On-chip port arbitration logic (IDT7130 Only) ◆ BUSY output flag on IDT7130; BUSY input on IDT7140 ◆ INT flag for port-to-port communication ◆ Fully asynchronous operation from either port ◆ Battery backup operation–2V data retention (LA only) ◆ TTL-compatible, single 5V ±10% power supply ◆ Military product compliant to MIL-PRF-38535 QML ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin PLCC, and 64-pin STQFP and TQFP ◆◆◆ ◆◆ Green parts available, see ordering information

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or- more-bit memory system applications results in full-speed, error- free operation without the need for additional discrete logic. Both devices provide two independent ports with separate con- trol, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these de- vices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual- Port typically consuming 200µW from a 2V battery. The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade products are manufactured in compli- ance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Pin Configurations(1,2,3) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. F48 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. L48(4) 424140393837363534333231 7 8 9 101112131415161718 2689 drw 03L GND CER CEL OEL A0L OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O3L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L INTL BUSYL R/WL R/WR BUSYR INTR VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R I/O7L I/O6L I/O5L I/O4L INDEX 42 41 40 39 38 37 36 35 34 33 32 31 7 8 9 10 11 12 13 14 15 16 17 18 2689 drw 03F GND CER CEL OEL A0L OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O3L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L INTL BUSYL R/WL R/WR BUSYR INTR VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R I/O7L I/O6L I/O5L I/O4L F48(4)

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. C48 package body is approximately .62 in x 2.43 in x .15 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Configurations(1,2,3) (con't.) 1 48 IDT7130/40 P or C P48(4,5) C48(4,5) 2689 drw 02 GND I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R I/O7L I/O6L I/O5L I/O4L CER CEL OEL A0L INTL BUSYL R/WL R/WR BUSYR INTR VCC OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O3L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 4. This package code is used to reference the package diagram. J52(4) N/C GND N/C N/C CER CEL OEL A0L OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R 46454443424140393837363534 I/O3L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L 8 9 1011121314151617181920 2689 drw 04 INTL BUSYL R/WL R/WR BUSYR INTR I/O6R VCC I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R I/O7L I/O6L I/O5L I/O4L

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PP64 package body is approximately 10 mm x 10 mm x 1.4mm. PN64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram PP64 & PN64(4) 8 9 10 11 1213 14 15161 2 3 4 5 6 7 46 454443 42 4140 39 383736 35 344748 33 I/O6R N/C A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R OER N/C N/C I/O2L A0L OEL A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L N/C N/C 2689 drw 05 N/C N/C N/C N/C N/C N/C GND N/C N/C GND N/C R/WR CER VCC VCC BUSYL INTL I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R R/WL CEL BUSYR INTR

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Symbol Rating Commercial & Industrial Military Unit VTE RM(2) T erminal Voltage with Respect to GND T BIAS Te m p e ra tur e Under Bias -55 to +125 -65 to +135 oC TSTG Storage Te m p e ra tur e -65 to +150 -65 to +150 oC IOUT DC Output Current 50 50 mA 2689 tbl 01 Recommended DC Operating Conditions NOTES: 1. V IL (min.) > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(2) V VIL Input Low Voltage -0.5 (1) ____ 0.8 V 2689 tbl 02 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. Capacitance (TA = +25°C, f = 1.0MHz) STQFP and TQFP Packages Only Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance V IN = 3dV 9 pF COUT Output Capacitance V OUT = 3dV 10 pF 2689 tbl 05 Recommended Operating Temperature and Supply Voltage(1) NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. Grade Ambient Temperature GND Vcc Military -55 OC to +125OC0 V 5 . 0 V + 10% Commercial 0 OC to +70OC0 V 5 . 0 V + 10% Industrial -40 OC to +85OC0 V 5 . 0 V + 10% 2689 tbl 03 Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) NOTE: 1. At Vcc < 2.0V leakages are undefined. Symbol Parameter Test Conditions 7130SA 7140SA 7130LA 7140LA UnitMin. Max. Min. Max. LI| Input Leakage Current (1) VCC = 5.5V, V IN = 0V to V CC ___ 10 ___ 5µ A |ILO| Output Leakage Current(1) VCC - 5.5V, CE = V IH, VOUT = 0V to V CC VOL Output Low Voltage (I/O0-I/O7)I OL = 4mA ___ 0.4 ___ 0.4 V VOL Open Drain Output Low Voltage ( BUSY, INT) I VOH Output High Voltage I OH = -4mA 2.4 ___ 2.4 ___ V 2689 tbl 04

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%) NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. PLCC , TQFP and STQFP packages only. 3. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vcc = 5V, T A=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port "A". 7130X20(2) 7140X20(2) Com'l Only 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military I CC Dynamic Operating Current (Both Ports Active) CEL and CER = V IL, Outputs Disabled f = fMAX(3) COM'L SA LA 110 110 250 200 110 110 220 170 110 110 165 120 mA MIL & IND SA LA ____ ____ ____ ____ 110 110 280 220 110 110 230 170 I SB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = V IH f = fMAX(3) COM'L SA LA mA MIL & IND SA LA ____ ____ ____ ____ I SB2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = VIH(6 ) Active Port OutputsDisabled, f=f MAX(3) COM'L SA LA 165 125 150 115 125 mA MIL & IND SA LA ____ ____ ____ ____ 160 125 150 115 I SB3 Full Standby Current (Both Ports - CMOS Level Inputs) CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or COM'L SA LA 1.0 0.2 1.0 0.2 1.0 0.2 mA MIL & IND SA LA ____ ____ ____ ____ 1.0 0.2 ____ ____ ____ ____ ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(6) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = f MAX(3) COM'L SA LA 155 115 145 105 110 mA MIL & IND SA LA ____ ____ ____ ____ 155 115 145 105 2689 tbl 06a 7130X55 7140X55 Com'l, Ind & Military 7130X100 7140X100 Com'l, Ind & Military Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit I CC Dynamic Operating Current (Both Ports Active) CE L and CER = V IL, Outputs Disabled f = fMAX(3) COM'L SA LA 110 110 155 110 110 110 155 110 mA MIL & IND SA LA 110 110 190 140 110 110 190 140 I SB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = V IH f = fMAX(3) COM'L SA LA mA MIL & IND SA LA I SB2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = VIH(6) Active Port Outputs Disabled, f=f MAX(3) COM'L SA LA 110 110 mA MIL & IND SA LA 125 125 I SB3 Full Standby Current (Both Ports - CMOS Level Inputs) CE L and CER > VCC - 0.2V, VIN > VCC - 0.2V or COM'L SA LA 1.0 0.2 1.0 0.2 mA MIL & IND SA LA 1.0 0.2 1.0 0.2 ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VCC - 0.2V (6) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) COM'L SA LA 100 mA MIL & IND SA LA 110 110 2689 tbl 06b

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Data Retention Waveform VCC CE 4.5V 4.5V DATA RETENTION MODE tCDR tR VIH VIH VDR VDR 2.0V 2692 drw 06 Data Retention Characteristics (LA Version Only) NOTES: 1. V CC = 2V, TA = +25°C, and is not production tested. 2. t RC = Read Cycle Time 3. This parameter is guaranteed but not production tested. 7130LA/7140LA Symbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention 2.0 ___ ___ V ICCDR Data Retention Current VCC = 2.0V, CE > VCC -0.2V MIL. & IND. ___ 100 4000 µA tCDR(3) Chip Deselect to Data Retention Time VIN > VCC -0.2V or V IN < 0.2V 0 ___ ___ ns tR(3) Operation Recovery Time t RC(2) ___ ___ ns 2689 tbl 07

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Operating Temperature Supply Voltage Range(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. PLCC, TQFP and STQFP packages only. 3. 'X' in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. 7130X20(2) 7140X20(2) Com'l Only 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military READ CYCLE t tPU Chip Enable to Power Up Time (4) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (4) ____ 20 ____ 25 ____ 35 ns 2689 tbl 09a 7130X55 7140X55 Com'l, Ind & Military 7130X100 7140X100 Com'l, Ind & Military UnitS y m b o l P a r a m e t e r M i n .M a x .M i n .M a x . READ CYCLE t tAA Address Access Time ____ 55 ____ 100 ns tACE Chip Enable Access Time ____ 55 ____ 100 ns tAO E Output Enable Access Time ____ 25 ____ 40 ns tOH Output Hold from Address Change 3 ____ 10 ____ ns tLZ Output Low-Z Time(1,4) 5 ____ 5 ____ ns tHZ Output High-Z Time(1,4) ____ 25 ____ 40 ns tPU Chip Enable to Power Up Time (4) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (4) ____ 50 ____ 50 ns 2689 tbl 09b

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 2, Either Side(3) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. R/ W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last t AOE, tACE, tAA, and tBDD. Timing Waveform of Read Cycle No. 1, Either Side(1) ADDRESS DATAOUT tRC tOH PREVIOUS DATA VALID tAA tOH DATA VALID 2689 drw 08 tBDDH (2,3) BUSYOUT NOTES: 1. R/ W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. t BDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last t AOE, tACE, tAA, and tBDD. CE tACE tAOE tHZtLZ tPD VALID DATA tPU 50% OE DATAOUT CURRENT ICC ISS 50% 2689 drw 09 (4) (1) (1) (2) (2) (4)tLZ tHZ

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Operating Temperature Supply Voltage Range(5) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. PLCC, TQFP and STQFP packages only. 3. For MASTER/SLAVE combination, t WC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. 'X' in part numbers indicates power rating (SA or LA). Symbol Parameter 7130X20(2) 7140X20(2) Com'l Only 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military WRITE CYCLE t tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tWZ Write Enable to Output in High-Z (1) ____ 10 ____ 10 ____ 15 ns tOW Output Active from End-of-Write (1) 0 ____ 0 ____ 0 ____ ns 2689 tbl 10a Symbol Parameter 7130X55 7140X55 Com'l, Ind & Military 7130X100 7140X100 Com'l, Ind & Military UnitMin. Max. Min. Max. WRITE CYCLE t WC Write Cycle Time (3) 55 ____ 100 ____ ns tEW Chip Enable to End-of-Write 40 ____ 90 ____ ns tAW Address Valid to End-of-Write 40 ____ 90 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width (4) 30 ____ 55 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 20 ____ 40 ____ ns tHZ Output High-Z Time(1) ____ 25 ____ 40 ns tWZ Write Enable to Output in High-Z (1) ____ 25 ____ 40 ns tOW Output Active from End-of-Write (1) 0 ____ 0 ____ ns 2689 tbl 10b

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5) NOTES: 1. R/ W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or tWP) of CE = VIL and R/W = VIL. 3. t WR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state. 6. Timing depends on which enable signal ( CE or R/W) is asserted last. 7. This parameter is determined by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8) tWC ADDRESS OE CE R/W DATAOUT DATAIN tAS(6) tOW tDW tDH tAW tWP(2) tHZ(7) (4) (4) tWZ(7) tHZ(7) 2689 drw 10 tWR(3) tWC ADDRESS CE R/W DATAIN tAS(6) tEW(2) tWR(3) tDW tDH tAW 2689 drw 11

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range(7) NOTES: 1. PLCC, TQFP and STQFP packages only. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY." 3. To ensure that the earlier of the two ports wins. 4. t BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'. 6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 7. 'X' in part numbers indicates power rating (S or L). 7130X20(1) 7140X20(1) Com'l Only 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military BUSY TIMING (For MASTER IDT 7130) t BAA BUSY Access Time from Address ____ 20 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 20 ns tBDC BUSY Disable T ime from Chip Enable ____ 20 ____ 20 ____ 20 ns tWDD Write Pulse to Data Delay(2) ____ 40 ____ 50 ____ 60 ns tDDD Write Data Valid to Read Data Delay (2) ____ 30 ____ 35 ____ 35 ns tAPS Arbitration Priority Set-up Time (3) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (4) ____ 25 ____ 35 ____ 35 ns BUSY INPUT TIMING (For SLAVE IDT 7140) tWDD Write Pulse to Data Delay(2) ____ 40 ____ 50 ____ 60 ns tDDD Write Data Valid to Read Data Delay (2) ____ 30 ____ 35 ____ 35 ns 2689 tbl 11a 7130X55 7140X55 Com'l, Ind & Military 7130X100 7140X100 Com'l, Ind & Military S y m b o l P a r a m e t e r M i n .M a x .M i n .M a x . U n i t BUSY TIMING (For MASTER IDT 7130) t BAA BUSY Access Time from Address] ____ 30 ____ 50 ns tBDA BUSY Disable Time from Address ____ 30 ____ 50 ns tBAC BUSY Access T ime f rom C h ip En able ____ 30 ____ 50 ns tBDC BUSY Disable Time from Chip Enable ____ 30 ____ 50 ns tWH Write Hold After BUSY(6) 20 ____ 20 ____ ns tWDD Write Pulse to Data Delay(2) ____ 80 ____ 120 ns tDDD Write Data Valid to Read Data Delay (2) ____ 55 ____ 100 ns tAPS Arbitration Priority Set-up Time (3) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (4) ____ 55 ____ 65 ns BUSY INPUT TIMING (For SLAVE IDT 7140) tWB Write to BUSY Input(5) 0 ____ 0 ____ ns tWH Write Hold After BUSY(6) 20 ____ 20 ____ ns tWDD Write Pulse to Data Delay(2) ____ 80 ____ 120 ns tDDD Write Data Valid to Read Data Delay (2) ____ 55 ____ 100 ns 2689 tbl 11b

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4) NOTES: 1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". Timing Waveform of Write with BUSY(3) NOTES: 1. t WH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A". BUSY"B" 2689 drw 13 R/W"A" tWP tWH tWB R/W"B" (2) (1) tWC tWP tDW tDH tBDD tDDD tBDA tWDD ADDR"B" DATAOUT"B" DATAIN"A" ADDR"A" MATCH VALID MATCH VALID R/W"A" BUSY"B" tAPS(1) 2689 drw 12 tBAA

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range(2) NOTES: 1. PLCC, TQFP and STQFP package only. 2. 'X' in part numbers indicates power rating (SA or LA). Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) Timing Waveform by BUSY Arbitration Controlled by Address Match Timing(1) tAPS ADDR 'A' AND 'B' ADDRESSES MATCH tBAC tBDC CE'B' CE'A' BUSY'A' 2689 drw 14 (2) BUSY'B' ADDRESSES DO NOT MATCHADDRESSES MATCH tAPS ADDR'A' ADDR'B' 2689 drw 15 (2) tBAA tBDA tRC OR tWC NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only). 7130X20(1) 7140X20(1) Com'l Only 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military INTERRUPT TIMING t 2689 tbl 12a

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges tINS ADDR'A' INT'B' INTERRUPT ADDRESS tWC tAS R/W'A' tWR 2689 drw 16 (3) (3) (2) (4) INT Set: Timing Waveform of Interrupt Mode(1) NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interrupt Truth Table II. 3. Timing depends on which enable signal ( CE or R/W) is asserted last. 4. Timing depends on which enable signal ( CE or R/W) is de-asserted first. INT Clear: Operating Temperature and Supply Voltage Range(1) NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 7130X55 7140X55 Com'l, Ind & Military 7130X100 7140X100 Com'l, Ind & Military Symbol Parameter Min. Max. Min. Max. Unit INTERRUPT TIMING t tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 45 ____ 60 ns tINR Interrupt Reset Time ____ 45 ____ 60 ns 2689 tbl 12b tRC INTERRUPT CLEAR ADDRESSADDR'B' OE'B' tINR INT'A' 2689 drw 17 tAS (3) (3)

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Truth Table I — Non-Contention Read/Write Control(4) Truth Tables Truth Table II — Interrupt Flag(1,4) Truth Table III — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSY R outputs are driving LOW regardless of actual logic level on the pin. NOTES: 1. A 0L – A10L ≠ A0R – A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = V IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE Inputs(1 ) FunctionR/W CE OE D0-7 X H X Z Port Disabled and in Power-Down Mode, I SB2 or I SB4 XH X Z CER = CEL = V IH, Power-Down Mode, I SB1 or I SB3 LLX D A T A IN Data on Port Written into Memory (2) HLL D A T A OUT Data in Memory Output on Port (3) H L H Z High Impedance Outputs 2689 tbl 13 Left Port Right Port FunctionR/WL CEL OEL A9L-A0L INTL R/WR CER OER A9R-A0R INTR LLX3 F FXXXX X L (2) Set Right INTR Flag X X XXX X L L 3 F F H (3) Reset Right INTR Flag XXX X L (3) LLX 3 F E X S e t L e f t INTL Flag XLL3 F E H (2) X X X X X Reset Left INTL Flag 2689 tbl 14 Inputs Outputs FunctionCEL CER A0L-A9L A0R-A9R BUSYL(1 ) BUSYR(1 ) X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit (3) 2689 tbl 15

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. 3. For "P", plastic DIP, when ordering green package the suffix is "PDG". Datasheet Document History 03/15/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations 06/08/99: Changed drawing format 08/02/99: Page 2 Corrected package number in note 3 09/29/99: Page 2 Fixed pin 1 in DIP pin configuration 11/10/99: Page 1 & 18 Replaced IDT logo 06/23/00: Page 4 Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Page 10 Changed ±500mV to 0mV in notes 01/08/02: Page 1 Added Ceramic Flatpack to 48-pin package offerings Page 2 & 3 Added date revision to pin configurations Page 4, 5, 8, 10, Removed industrial temp option footnote from all tables 12,14 & 15 48-pin Plastic DIP (P48) 48-pin Sidebraze DIP (C48) 52-pin PLCC (J52) 48-pin LCC (L48) 48-pin Ceramic Flatpack (F48) 64-pin TQFP (PN64) 64-pin STQFP (PP64) 7130 7140 Speed in nanoseconds 8K (1K x 8-Bit) MASTER Dual-Port RAM 8K (1K x 8-Bit) SLAVE Dual-Port RAM Commercial PLCC, TQFP and STQFP Only Commercial, Industrial & Military Commercial & Military Commercial, Industrial & Military Commercial, Industrial & Military 2689 drw 19 Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML P C J L F PF TF 100 LA SA Low Power Standard Power G (2) Green (3) XXXX Device Type A 999 A A Power Speed Package Process/ Temperature Range A A Blank Tube or Tray Tape and Reel

IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History (cont'd) 01/08/02: Page 5, 8, 10, 12, & 14 Added industrial temp for 25ns to DC & AC Electrical Characteristics Page 5, 8, 10, 12, & 14 Removed industrial temp for 35ns to DC & AC Electrical Characteristics Page 18 Added industrial temp for 25ns and removed industrial temp for 35ns in ordering information Updated industrial temp option footnote Page 1 & 19 Replaced IDT TM logo with IDT ® logo 01/11/06: Page 1 Added green availability to features Page 18 Added green indicator to ordering information Page 1 & 19 Replaced old IDT TM with new IDT TM logo 04/14/06: Page 18 Added "PDG" footnote to the ordering information 10/21/08: Page 18 Removed "IDT" from orderable part number 01/21/13: Page 2 Added L48-1 package and F48-1 package pin configurations with corresponding foot notes Page 13, 18, 19 & 20 Typo/corrections Page 20 Added T & Reel indicator to ordering information 05/20/16: Page 2 Split the F48 and L48 pin configuration, creating two separate pin configurations: F48 pin ceramic flatpack rotated 90 degrees counterclockwise, removed footnote 5 reference and L48 LCC rotated 90 degrees clockwise to reflect pin 1 orientation and added dot at pin 1, removed footnote 5 reference Page 3 P48 plastic DIP and C48 sidebrazed DIP, removed half moon and to reflect pin 1 orientation added dot at pin 1 Page 4 J52 PLCC rotated 90 degrees clockwise to reflect pin 1 orientation added dot at pin 1, removed footnote 5 reference Page 5 PN64 TQFP and PP64 STQFP, chamfer removed, rotated 90 degrees counterclockwise to reflect pin 1 orientation and added dot at pin 1, removed footnote 5 reference Page 20 All incidences of -1 , -2 have been removed from the datasheet The IDT logo is a registered trademark of Integrated Device Technology, Inc. CORPORATE HEADQUARTERS for SALES: for Tech Support:

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