7106

UTC7106 UTC | Alldatasheet

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UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R502-018,B ABSOLUTE MAXIMUM RATINGS(Ta=25℃) PARAMETER SYMBOL RATINGS UNIT Supply Voltage (V+ ~ V-) V DD 15 V Analog Input Voltage (Either Input) (Note 1) V I,ANG V+ ~ V- V Reference Input Voltage (Either Input) V I,REF V+ ~ V- V Operating Temperature Range T OP 0 ~ +70 ℃ THERMAL INFORMATION PARAMETER SYMBOL RATINGS UNIT Thermal Resistance (Tyical, Note 2) DIP-40 QFP-44 θ JA (°C/W) Maximum Junction Temperature T J 150 °C Maximum Storage Temperature Range T STG -65 ~ +150 °C Maximum Lead Temperature (Soldering 10s) (QFP-44 only) T LOAD 300 °C Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ±100μA. Note 2: θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. ELECTRICAL CHARACTERISTICS (Note 3) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading R Z V IN=0.0V, Full Scale=200mV -000.0 ±000.0 +000.0 Digital Reading Ratiometric Reading R R V IN=VREF, VREF=100mV 999 999/1000 1000 Digital Reading Rollover Error E R -VIN=+VIN≒200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale ±0.2 ±1 Counts Linearity L Full Scale=200mV or Full Scale=2V Maximum Devi- ation from Best Straight Line Fit (Note 5) ±0.2 ±1 Counts Common Mode Rejection Ratio CMRR VCM=1V,VIN=0V, Full Scale=200mV(Note 5) 50 μV/V Noise V N VIN=0V,Full Scale=200mV (Peak-To-Peak Value Not Exceeded 95% of Time) 15 μV Leakage Current Input I L V IN=0(Note 5) 1 10 pA Zero Reading Drift D ZR VIN=0, 0℃ ~ 70 ℃ (Note 5) 0.2 1 μV/℃ Scale Factor Temperature Coefficient ΦT,S (Ext.Ref.0ppm/℃) (Note 5) 1 5 ppm/℃ End Power Supply Character V+ Supply Current IEP V IN=0 1.0 1.8 mA COMMON Pin Analog Common Voltage V COM 25kΩ Between Common and Positive Supply (With Respect to +Supply) 2.4 3.0 3.2 V

UTC UNISONIC TECHNOLOGIES CO., LTD. 4 QW-R502-018,B PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Temperature Coefficient of Analog Common ΦT,A 25kΩ Between Common and Positive Supply (With Respect to +Supply) 80 ppm/℃ DISPLAY DRIVER Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage V D,PP V+ ~ V-=9V(Note 4) 4 5.5 6 V Note 3: Unless otherwise noted, specifications apply to the UTC 7106 at T a=25℃, fCLOCK=48kHz, UTC 7106 is tested in the circuit of Figure 1. Note 4: Back plane drive is in phase with segment drive for”off”segment,180 degrees out of phase for”on” segment .Frequency is 20 times conversion rate. Average DC component is less than 50mV. Note 5: Not tested, guaranteed by design. TYPICAL APPLICATIONS AND TEST CIRCUITS (LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE) 20 21 40V+ AB4 POL OSC 1 OSC 2 OSC 3 TEST REF HI REF LO C REF+ CREF - COM IN HI IN LO A-Z BUFF INT BP UTC 7106 DISPLAY R3 C4 R4 C1 IN + - C2 R2 C3 DISPLAY C1=0.1μF C2=0.47μF C3=0.22μF C4=100pF C5=0.02μF R1=24kΩ R2=47kΩ R3=91kΩ R4=1kΩ R5=1MΩ + - DESIGN INFORMATION SUMMARY SHEET *OSCILLATOR FREQUENCY fosc=0.45/RC COSC>50pF, ROSC>50kΩ fOSC (Typ)=48kHz *OSCILLATOR PERIOD tOSC=RC/0.45 *INTEGRATION CLOCK FREQUENCY

UTC UNISONIC TECHNOLOGIES CO., LTD. 5 QW-R502-018,B fCLOCK=fOSC/4 *INTEGRATION PERIOD tINT=1000×(4/fOSC) *60/50Hz REJECTION CRITERION tINT/t60Hz or tINT/t50Hz=Integer *OPTIMUM INTEGRATION CURRENT IINT=4μA *FULL SCALE ANALOG INPUT VOLTAGE VINFS (Typ)=200mV or 2V *INTEGRATE ESISTOR R INT= VINFS/ IINT *INTEGRATE CAPACITOR CINT=(tINT)(IINT)/ VINT *INTEGRATOR OUTPUT VOLTAGE SWING VINT=(tINT)(IINT)/ CINT *VINT MAXIMUM SWING (V- + 0.5V)<V INT<(V+ - 0.5V), VINT (Typ)=2V *DISPLAY COUNT COUNT=1000 ×VIN/VREF *CONVERSION CYCLE tCYC=tCLOCK×4000 tCYC=tOSC×16,000 When fOSC=48kHz, tCYC=333ms *COMMON MODE INPUT VOLTAGE (V- + 1V)<VIN<(V+ - 0.5V) *AUTO-ZERO CAPACITOR 0.01μF<CAZ<1μF *REFERENCE CAPACITOR 0.1μF<CREF<1μF *VCOM Biased between Vi and V- *VCOM≒V+ - 2.8V Regulation lost when V+ to V- <≒6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. *POWER SUPPLY: SINGLE 9V V+ - V- =9V

UTC UNISONIC TECHNOLOGIES CO., LTD. 6 QW-R502-018,B VGND≒V+ - 4.5V Digital supply is generated by internal parts. *DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. TYPICAL INTEGRATOR AMPLIFIER OUTPUT WAVEFORM (INT PIN) DE-INTEGRATE PHASE 0 - 1999 COUNTS SIGNAL INTEGRATE PHASE FIXED

1000 COUNTS

(COUNTS) 2999-1000 TOTAL CONVERSION TIME=4000 × tCLOCK=16,000 × tosc DETAILED DESCRIPTION ANALOG SECTION Figure 1 shows the Analog Section for the UTC 7106. Each measurement cycle is divided into three phases. They are(1) auto-zero(A-Z), (2)signal integrate (INT)and (3)de-integrate(DE). AUTO-ZERO PHASE During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor C AZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparat or is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case. the offset referred to the input is less than 10 μV. SIGNAL INTEGRATE PHASE During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. if, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. DE-INTEGRATE PHASE The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: DISPLAY COUNT=1000( V IN/ VREF ). DIFFERENTIAL INPUT The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst

of either supply without loss of linearity. FIGURE 1. ANALOG SECTION coefficient (0.001%/V), low output impedance (≒15Ω), and a temperature coefficient typically less than 80ppm/ ℃. reference can easily be added, as shown in Figure 1. analog COMMON, it should be since this removes the common mode voltage from the reference system.

makes the system slightly quieter and also avoids a divider network on the input. possibilities, and serve to illustrate the exceptional versatility of these A/D converters. FIGURE 7. USING THE INTERNAL REFERENCE

FIGURE 8. RECOMMENDED COMPONENT VALUES

A sillicon diode-connected transistor has a temperature coefficient of about -2mV/ ℃. FIGURE 9. USED AS A DIGITAL CENTIGRADE THERMOMETER

FIGURE 10. CIRCUIT FOR DEVELOPING UNDERRANGE AND

Test is used as a common-mode reference level to ensure compatiblity with most op amps. FIGURE 11. AC TO DC CONVERTER WITH UTC 7106 and reliable and may be changed without notice.