70V3389S4BCG8

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◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5ns (max) ◆ Pipelined output mode ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) – Fast 4.2ns clock to data out – 1.8ns setup to clock and 0.7ns hold on all control, data, and address inputs @ 133MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ LVTTL- compatible, single 3.3V (±150mV) power supply for core ◆ LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV) power supply for I/Os and control signals on each port ◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆ Available in a 128-pin Thin Quad Plastic Flatpack (TQFP), 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array IDT70V3389SHIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE ◆ Green parts available, see ordering information

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3389 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE 0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3389 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (V DD) remains at 3.3V. Pin Configuration(1,2,3,4) NOTES: 1. All V DD pins must be connected to 3.3V power supply. 2. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V IH (3.3V), and 2.5V if OPT pin for that port is set to V IL (0V). 3. All V SS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 1716151412 1310987654321 11 A B C D E F G H J K L M N P R T U I/O9L NC V SS NC A2L A4LCLKLA8LA12LNCNC OPTL NC VSS NC VSS A1LA5LA9LA13LNC VDDQL I/O9R VDDQR VDD A3L A6L NC A10LA14LNC NC NC V SS I/O10L NC NC I/O11L NC VDDQR I/O10R NC I/O11R NC VSS VDD NC I/O 12L VDD VSS VSS NC VSS I/O12R CNTRSTR NC I/O 14L VDDQR VDDQL I/O15RNC VSS NCNC A15L A11L A7L A0L NC I/O7L NC I/O6L I/O8RUBL NC I/O8L VDDQL CE0L CE1L LBL CNTRST LOEL I/O0L I/O2LI/O1R ADSR R/WR NC I/O16R I/O15L NC A13R A12R NC VDD CLKR I/O0R NC NC NC NC NCNC VSS A5RA9R CE0R CE1R VDD VSS NC NC NC NC NC NC A14R A10R UBR VSS VDDQL I/O1L I/O2R NC NC NC A 15R A11R A7R LBR OER VSS NC VDDQL OPTR NC 70V3389BF BF-208(5) 208-Pin fpBGA Top View(6) 4832 tbl 02 I/O14R VDDQL VSS VDDQR NC NC NC NC I/O7R NC R/WL NC ADSL VDDQL I/O13R CNTENL VSS I/O13L VSS I/O16L VDDQR VSS I/O17R I/O17L VDDQL VSS VDD A8R CNTENR A6R A3R A1R A2R A0R I/O3L I/O4L A4R VDD VSS VSS VSS VDDQR VDDQL VSS VDDQR VSS I/O3R I/O4R VSS VDDQRVSSVDDVSS VDD VSS I/O5R I/O5L VDDQRI/O6RVSS VSS VDDQL VDD VSS VDDQRVSS VSS VDD VDD VSS VDD VSS 12/12/01

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4) (con't.) NOTES: 1. All V DD pins must be connected to 3.3V power supply. 2. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V IH (3.3V), and 2.5V if OPT pin for that port is set to V IL (0V). 3. All V SS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 70V3389BC BC-256(5) 256-Pin BGA Top View(6) E16 I/O7R D16 I/O8R C16 I/O8L B16 NC A16 NC A15 NC B15 NC C15 NC D15 NC E15 I/O7L E14 NC D14 NC D13 VDD C12 A6L C14 OPTL B14 VDD A14 A0L A12 A5L B12 A4L C11 ADSL D12 VDDQR D11 VDDQR C10 CLKL B11 CNTRSTL A11 CNTENL VDDQR NC CE1L VDDQL LBL CE0L D10 VDDQL A7L UBL NC B13 A1L A13 A2L A10 OEL VDDQR A9L A8L A12L A10L VDDQL A14L A15L A13L VDDQL NC NC NC VDD NC NC VSS NC I/O9R I/O9L NC NC NC NC NC NC I/O10R I/O10L NC VDDQL I/O11L NC VDDQL NC NC I/O12L VDDQR NC I/O12R NC VDDQR I/O13L I/O14R I/O13R VDDQL NC NC I/O14L VDDQL I/O15L NC I/O15R VDDQR I/O16R I/O16L NC VDDQR NC I/O17R NC VDD NC I/O17L NC NC NC NC NC NC NC NC NC NC A13R A15R P12 A6R NC LBR UBR NC P10 CLKR T11 CNTENR P11 ADSR R12 A4R T12 A5R P13 A3R A7R R13 A1R T13 A2R A12R A14R T14 A0R R14 OPTR P14 NC P15 NC R15 NC T15 NC T16 NC R16 NC P16 I/O0L N16 NC N15 I/O0R N14 NC M16 NC M15 I/O1L M14 I/O1R L16 I/O2R L15 NC L14 I/O2L K16 I/O3L K15 NC K14 NC J16 I/O4L J15 I/O3R J14 I/O4R H16 I/O5R H15 NC H14 NC G16 NC G15 NC G14 I/O5L F16 I/O6L F14 I/O6R F15 NC CE0R R11 CNTRST R A11R CE1R A11L B10 R/WL C13 A3L A10R R10 R/WR A9R T10 OER A8R VDD VDD VSS VSS VSS E10 VSS E11 VDD E12 VDD E13 VDDQR VDD VSS VSS VSS F10 VSS F12 VDD F13 VDDQR VSS VSS VSS VSS VSS G10 VSS G11 VSS G12 VSS G13 VDDQL VSS VSS VSS VSS VSS H10 VSS H11 VSS H12 VSS H13 VDDQL VSS VSS VSS VSS VSS J10 VSS J11 VSS J12 VSS J13 VDDQR VSS VSS VSS VSS VDD VSS VSS VSS VDD VDD VSS VSS VDDQR VDDQR VDDQL VDDQL VSS K10 VSS K11 VSS K12 VSS VSS L10 VSS L11 VSS L12 VDD VSS M10 VSS M11 VDD M12 VDD VDDQR N10 VDDQR N11 VDDQL N12 VDDQL K13 VDDQR L13 VDDQL M13 VDDQL N13 VDD VSS F11 VSS 4832 drw 02c I/O11R 12/12/01

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 102 101 100 A14L A15L VSS NC IO9L IO9R VDDQL VSS IO10L IO10R VDDQR VSS IO11L IO11R IO12L IO12R VDD VDD VSS VSS IO13R IO13L IO14R IO14L IO15R IO15L VDDQL VSS IO16R IO16L VDDQR VSS IO17R IO17L NC NC A15R A14R A1R A0R OPTR IO0L IO0R VDDQR VSS IO1L IO1R VDDQL VSS IO2L IO2R IO3L IO3R IO4L IO4R VSS VSS VDD VDD IO5L IO5R VDDQR VSS IO7R IO7L VDDQL VSS NC (VSS)(7) IO8R IO8L NC (VSS)(7) OPTL A0L A1L IO6R IO6L 70V3389PRF PK-128(5) 128-Pin TQFP Top View(6) 4832 drw 02a A 13L A 12L A 11L A 10L A A A UB L LB L CE CE V DD V DD V SS V SS CLK L OE L R/W L ADS L CNTEN L CNTRSTL A A A A A A 13R A 12R A 11R A 10R A A A UB R LB R CE CE V DD V DD V SS V SS CLK R OE R R/W R ADS R CNTEN R CNTRSTR A A A A A 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 12/12/01 Pin Configuration(1,2,3,4) (con't.) NOTES: 1. All V DD pins must be connected to 3.3V power supply. 2. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V IH (3.3V), and 2.5V if OPT pin for that port is set to V IL (0V). 3. All V SS pins must be connected to ground supply. 4. Package body is approximately 14mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign these pins as V SS. Customers who plan to take advantage of the upgrade path should treat these pins as V SS on the 70V3379 and 70V3389. If no upgrade is needed, the pins can be treated as NC.

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table I—Read/Write and Enable Control(1,2,3) Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 15L A0R - A 15R Address I/O0L - I/O17 L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock AD SL AD SR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRS TL CNTRSTR Counter Reset UBL - LB L UBR - LB R Byte Enables (9-bit bytes) VDDQ L VDDQR Power (I/O Bus) (3.3V or 2.5V) (1) OPTL OPTR Option for selecting V DDQX(1,2) VDD Power (3.3V)(1 ) VSS Ground (0V) 4832 tbl 01 OE CLK CE0 CE1 UB LB R/W Upper Byte I/O9-18 Lower Byte I/O0-8 MODE X ↑ L H H H X High-Z High-Z All Bytes Deselected X ↑ LHHLLH i g h - Z D IN Write to Lower Byte Only X ↑ LHLHL D IN High-Z Writ e t o Upper Byte Only X ↑ LHLLL D IN DIN Write to Both Bytes L ↑ LHHLHH i g h - Z D OUT Read Lower Byte Only L ↑ LHLHH D OUT High-Z Read Upper Byte Only L ↑ LHLLH D OUT DOUT Read Both Bytes H ↑ L H L L X High-Z High-Z Outputs Disabled 4832 tbl 02 NOTES: 1. V DD, OPT X, and V DDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPT X selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPT X is set to VIL (0V), then that port's I/Os and controls will operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Absolute Maximum Ratings(1) Truth Table II—Address Counter Control(1,2) NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/ W, CE0, CE 1, BEn and OE. 3. Outputs are in Pipelined mode: the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other memory control signals including CE0, CE 1 and BEn 5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE 1, BEn. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed V DD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of V TERM > VDD + 150mV. NOTES: 1. Industrial temperature: for specific speeds, packages and powers contact your sales office. Address Previous Address Addr Used CLK ADS CNTEN CNTRST I/O(3) MODE XX 0 ↑ XX L (4) DI/ O(0) Counter Reset to Address 0 An X An ↑ L (4 ) XH D I/O (n) External Address Used An Ap Ap ↑ HH H D I/O(p) External Address Blocked—Counter disabled (Ap reused) XA p A p + 1 ↑ H L (5) HD I/O(p+1) Counter Enabled—Internal Address generation 4832 tb l 03 Grade Ambient Temperature GND V DD Commercial 0 OC to +70OC0 V 3 . 3 V + 150mV Industrial -40 OC to +85OC0 V 3 . 3 V + 150mV 483 2 tbl 0 4 Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.15 3.3 3.45 V VDDQ I/O Supply Voltage (3) 2.375 2.5 2.625 V VSS Ground 0 0 0 V VIH Inp ut High Voltage(3) (Address & Control Inputs) 1.7 ____ VDDQ + 125mV(2) V VIH Inp ut High Voltage - I/O(3) 1.7 ____ VDDQ + 125mV(2) V VIL Input Low Voltage -0.3 (1) ____ 0.7 V 4832 tb l 05a Symbol Rating Commercial & Industrial Unit VTE RM(2 ) Terminal Voltage with Respect to GND -0.5 to +4.6 V TBIAS T emperature Under Bias -55 to +125 oC TST G Storage T emperature -65 to +150 oC IOUT DC Output Current 50 mA 4 832 tbl 06 Recommended DC Operating Conditions with VDDQ at 2.5V NOTES: 1. V IL > -1.5V for pulse width less than 10 ns. 2. V TERM must not exceed V DDQ + 125mV. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V IL (0V), and V DDQX for that port must be supplied as indicated above. Recommended DC Operating Conditions with VDDQ at 3.3V NOTES: 1. V IL > -1.5V for pulse width less than 10 ns. 2. V TERM must not exceed V DDQ + 150mV. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V IH (3.3V), and VDDQX for that port must be supplied as indicated above. Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.15 3.3 3.45 V VDDQ I/O Sup ply Voltage(3) 3.15 3.3 3.45 V VSS Ground 0 0 0 V VIH Input High Voltage (Address & Control Inputs) (3) 2.0 ____ VDDQ + 150mV(2) V VIH Input High Voltage - I/O (3) 2.0 ____ VDDQ + 150mV(2) V VIL Input Lo w Voltage -0.3 (1) ____ 0.8 V 4832 tbl 05b

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) NOTES: 1. At V DD < - 2.0V input leakages are undefined. Symbol Parameter Test Conditions 70V3389S UnitMin. Max. |ILI| Input Leakage Current (1 ) VDD Q = Max., V IN = 0V to V DDQ ___ 10 µA |ILO| Output Leakage Current CE0 = V IH or CE 1 = V IL, VOUT = 0V to V DD Q ___ 10 µA VOL (3.3V) Output Low Voltage (2) IOL = +4mA, V DDQ = Min. ___ 0.4 V VOH (3.3V) Output High Voltage (2) IOH = -4mA, V DD Q = Min. 2.4 ___ V VOL (2.5V) Output Low Voltage (2) IOL = +2mA, V DDQ = Min. ___ 0.4 V VOH (2.5V) Output High Voltage (2) IOH = -2mA, V DD Q = Min. 2.0 ___ V 4832 tb l 0 8 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. C OUT also references C I/O. Capacitance(1) (TA = +25°C, F = 1.0MHZ) TQFP ONLY Symbol Parameter Conditions (2) Max. Unit CIN I nput Capacit ance V IN = 3dV 8 pF COUT(3 ) Output Capacitance V OUT = 3dV 10.5 pF 4832 tbl 07

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV) NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. V DD = 3.3V, T A = 25°C for Typ, and are not production tested. I DD DC (f=0) = 120mA (Typ). 5. CEX = V IL means CE0X = V IL and CE 1X = V IH CEX = V IH means CE0X = V IH or CE 1X = V IL CEX < 0.2V means CE0X < 0.2V and CE 1X > VDDQ - 0.2V CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE 1X - 0.2V "X" represents "L" for left port or "R" for right port. 70V3389S4 Com'l Only 70V3389S5 Com'l & Ind 70V3389S6 Com'l Only IDD Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L S 375 460 285 360 245 310 mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL = CER = V IH f = fMAX(1) COM'L S 145 190 105 145 95 125 mA ISB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) COM'L S 265 325 190 260 175 225 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CE L and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or V IN < 0.2V, f = 0 (2) C O M ' L S 61 561 561 5 mA ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VDDQ - 0.2V (5) VIN > VDDQ - 0.2V or V IN < 0.2V, Active Port, Outputs Disabled, f = f MAX(1) COM'L S 265 325 180 260 170 225 mA 4832 tbl 09

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Temperature Range (Read and Write Cycle Timing)(1,2) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) NOTES: 1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE). 70V3389S4 Com'l Only 70V3389S5 Com'l & Ind 70V3389S6 Com'l Only tCYC2 Clock Cycle Time (Pipelined) 7.5 ____ 10 ____ 12 ____ ns tOHZ Output Enable to Output High-Z 1 4 1 4.5 1 5 ns tCD2 Clock t o Dat a Valid (Pipelined) ____ 4.2 ____ 5 ____ 6n s tDC Data Output Hold After Clock High 1 ____ 1 ____ 1 ____ ns tCKHZ Clock High to Output High-Z 1 3 1 4.5 1.5 6 ns Port-to-Port Delay 4830 tbl 11

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges tSC tHC CE0(B1) ADDRESS(B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 4832 drw 07 Q0 Q1 Q3DATAOUT(B1) tCH2 tCL2 tCYC2 ADDRESS(B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATAOUT(B2) Q2 Q4 tCD2 tCD2 tCKHZ tCD2 tCKLZtDC tCKHZ tCD2 tCKLZ tSC tHC tCKHZ tCKLZ tCD2 tDC tSC tHC tSC tHC An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE1 UB, LB(0-3) (3) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 4832 drw 06 (1) (1) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (4) (1 Latency) (5) (5) Timing Waveform of a Multi-Device Pipelined Read(1,2) Timing Waveform of Read Cycle for Pipelined Operation(2) NOTES: 1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ADS = V IL, CNTEN and CNTRST = V IH. 3. The output is disabled (High-Impedance state) by CE0 = V IH, CE 1 = V IL, UB, LB = V IH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If UB or LB was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state). NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3389 for this waveform, and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = V IL; CE 1(B1), CE 1(B2), R/ W, CNTEN, and CNTRST = V IH.

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges CLKL R/WL ADDRESSL DATAINL CLKR R/WR ADDRESSR DATAOUTR tSW tHW tSA tHA tSD tHD tSW tHW tSA tHA tCO(3) tCD2 NO MATCH VALID NO MATCHMATCH MATCH VALID 4832 drw 08tDC R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 CE0 CLK 4832 drw 09 Qn Qn + 3DATAOUT CE1 UB, LB tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (3) (1) tSW tHW WRITE (4) Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2) NOTES: 1. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. 2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to. 3. If t CO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will be tCO + 2 t CYC2 + t CD2). If t CO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on o pposite port will be t CO + t CYC + t CD2). Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges ADDRESS An CLK DATAOUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3 ADS CNTEN tCYC2 tCH2 tCL2 4832 drw 11 tSA tHA tSAD tHAD tCD2 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tSAD tHAD tSCN tHCN READ WITH COUNTER Qn + 1 R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATAIN Dn + 3Dn + 2 CE0 CLK 4832 drw 10 DATAOUT Qn Qn + 4 CE1 UB, LB OE tCH2 tCL2 tCYC2 tCKLZ tCD2 tOHZ tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (3) (1) tSW tHW (4) Timing Waveform of Pipelined Read with Address Counter Advance(1) NOTES: 1. CE0, OE, UB, LB = V IL; CE 1, R/ W, and CNTRST = V IH. 2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH, then the data output remains constant for subsequent clocks. Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE 0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if tim ing so allows.

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges ADDRESS An tCH2 tCL2 tCYC2 Q0 Q1 CLK DATAIN R/W CNTRST 4832 drw 13 INTERNAL(3) ADDRESS ADS CNTEN tSRST tHRST tSD tHD tSW tHW COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Qn An + 1 An + 2 READ ADDRESS n+1 DATAOUT tSA tHA

1 An An + 1

(4) (5) (6) Ax tSAD tHAD tSCN tHCN Timing Waveform of Write with Address Counter Advance(1) Timing Waveform of Counter Reset(2) NOTES: 1. CE0, UB, LB, and R/ W = V IL; CE 1 and CNTRST = V IH. 2. CE0, UB, LB = V IL; CE 1 = V IH. 3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: A DDR 0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. T he ‘An +1’Address is written to during this cycle. ADDRESS An CLK DATAIN Dn Dn + 1 Dn + 1 Dn + 2 ADS CNTEN tCH2 tCL2 tCYC2 4832 drw 12 INTERNAL(3) ADDRESS An(7) An + 1 An + 2 An + 3 An + 4 Dn + 3 Dn + 4 tSA tHA tSAD tHAD WRITE COUNTER HOLD WRITE WITH COUNTERWRITE EXTERNAL ADDRESS WRITE WITH COUNTER tSD tHD tSCN tHCN

transition of the clock signal.

0 LOW and CE1

HIGH to re-activate the outputs. various chip enables in order to expand two devices in depth. Figure 4. Depth and Width Expansion with IDT70V3389

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Datasheet Document History 01/18/99: Initial Public Release 03/15/99: Page 9 Additional notes 04/28/99: Added fpBGA package 06/08/99: Page 2 Changed package body height from 1.5mm to 1.4mm 06/15/99: Page 5 Deleted note 6 for Table II 0714//99: Page 2 Corrected pin T3 to V DDQL 08/04/99: Page 6 Improved power numbers 10/01/99: Upgraded speed to 133MHz, added 2.5V I/O capability 11/12/99: Replaced IDT logo 02/28/00: Added new BGA package, added full 2.5V interface capability 05/01/00: Page 2 Added ball pitch Page 3 Renamed pins Page 6 Made corrections to Truth Table Page 9 Changed Ω numbers in figure 2 01/10/01: Page 4 Added information to pin and pin notes Page 6 Increased storage temperature parameter Clarified T A Parameter Page 8 DC Electrical parameters–changed wording from "open" to "disabled" Removed note 7 on DC Characteristics table Removed Preliminary status 04/10/01: Added Industrial Temperature Ranges and removed related notes NOTES: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2 Green parts available. For specific speeds, packages and powers contact your local sales office.

6.42 IDT70V3389S High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges The IDT logo is a registered trademark of Integrated Device Technology, Inc. CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 Dua lPortHelp@idt.com www.idt.com Datasheet Document History (cont'd) 02/12/01: Page 2, Added date revision to pin configurations 3 & 4 Page 6 Removed industrial temp footnote from table 04 Page 8 Removed industrial temp for 6ns from DC & AC Electrical Characteristic & 10 Page 16 Removed industrial temp from 6ns in ordering information Added industrial temp footnote Page 1 Replaced TM logo with ® logo & 17 01/05/06: Page 1 Added green availability to features Page 16 Added green indicator to ordering information 02/08/06: Page 5 Changed footnote 2 for Truth Table I from ADS, CNTEN, CNTRST = VIH to ADS, CNTEN, CNTRST = X 07/25/08: Page 8 Corrected a typo in the DC Chars table 01/19/09: Page 16 Removed "IDT" from orderable part number 10/03/14: Page 16 Added Tape & Reel to Ordering Information