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©2014 Integrated Device Technology, Inc. OCTOBER 2014 DSC 5623/10 Functional Block Diagram Features: ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed data access – Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) – Industrial: 4.2ns (133MHz) (max.) ◆ Selectable Pipelined or Flow-Through output mode – Due to limited pin count PL/ FT option is not supported on the 128-pin TQFP package. Device is pipelined outputs only on each port. ◆ Counter enable and repeat features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 6ns cycle time, 166MHz operation (6Gbps bandwidth) – Fast 3.6ns clock to data out – 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ Dual Cycle Deselect (DCD) for Pipelined Output mode ◆ LVTTL- compatible, single 3.3V (±150mV) power supply for core ◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port ◆ Industrial temperature range (-40°C to +85°C) is available at 133MHz. ◆ Available in a 128-pin Thin Quad Flatpack, 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array ◆ Supports JTAG features compliant to IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package ◆ Green parts available, see ordering information HIGH-SPEED 3.3V 256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3319/99S Dout0-8_L B W L B W L Din_L OEL UBL LBL R/WL CE0L CE1L ab FT/PIPEL 0/1 1b 0b 1a 0a 0b 1b0a 1a ab FT/PIPEL REPEATR A17R(1) A0R CNTENR ADSR Dout0-8_R Dout9-17_R I/O0R -I / O17RDin_R ADDR_R OER UBR LBR R/WR CE0R CE1R FT/PIPER CLKR Counter/ Address Reg. B W R B W R FT/PIPER Counter/ Address Reg. CNTENL ADSL REPEATL Dout9-17_L I/O0L -I / O17L A17L(1) A0L ADDR_L 5623 tbl 01 256K x 18 MEMORY ARRAY CLKL JTAG TCK TRST TMS TDO TDI ba 0b 1b0a 1a 1b 0b 1a 0a ab NOTE: 1. A 17 is a NC for IDT70V3399.
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3319/99 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE 0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3319/99 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (V DD) remains at 3.3V. Pin Configuration(1,2,3,4,5) NOTES: 1. A 17 is a NC for IDT70V3399. 2. All V DD pins must be connected to 3.3V power supply. 3. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V IH (3.3V), and 2.5V if OPT pin for that port is set to V IL (0V). 4. All V SS pins must be connected to ground supply. 5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 1716151412 1310987654321 11 A B C D E F G H J K L M N P R T U I/O9L NC V SS TDO A2L A4LCLKLA8LA12LA16LNC OPTL NC VSS NC TDI A1LA5LA9LA13LA17L(1) VDDQL I/O9R VDDQR PIPE/FTL A3L A6L NC A10LA14LNC NC NC V SS I/O10L NC NC I/O11L NC VDDQR I/O10R NC I/O11R NC VSS VDD NC I/O 12L VDD VSS VSS NC VSS I/O12R REPEATR NC I/O 14L VDDQR VDDQL I/O15RNC VSS NCNC A15L A11L A7L A0L NC I/O7L NC I/O6L I/O8RUBL NC I/O8L VDDQL CE0L CE1L LBL REPEATLOEL I/O0L I/O2LI/O1R ADSR R/WR NC I/O16R I/O15L TRST A13R A12R NC VDD CLKR I/O0R NC NC NC NC A17R(1)TCK TMS A5RA9R CE0R CE1R VDD VSS NC NC NC A16R NC NC A14R A10R UBR VSS VDDQL I/O1L I/O2R NC NC NC A 15R A11R A7R LBR OER VSS NC VDDQL OPTR NC 70V3319/99BF BF-208(6) 208-Pin fpBGA Top View(7) 5623 drw 02c I/O14R VDDQL VSS VDDQR NC NC NC NC I/O7R NC R/WL NC ADSL VDDQL I/O13R CNTENL VSS I/O13L VSS I/O16L VDDQR VSS I/O17R I/O17L VDDQL VSS PIPE/FTR A8R CNTENR A6R A3R A1R A2R A0R I/O3L I/O4L A4R VDD VSS VSS VSS VDDQR VDDQL VSS VDDQR VSS I/O3R I/O4R VSS VDDQRVSSVDDVSS VDD VSS I/O5R I/O5L VDDQRI/O6RVSS VSS VDDQL VDD VSS VDDQRVSS VSS VDD VDD VSS VDD VSS 08/01/02
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4,5) (con't.) NOTES: 1. A 17 is a NC for IDT70V3399. 2. All V DD pins must be connected to 3.3V power supply. 3. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V IH (3.3V), and 2.5V if OPT pin for that port is set to V IL (0V). 4. All V SS pins must be connected to ground supply. 5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 70V3319/99BC BC-256(6) 256-Pin BGA Top View(7) E16 I/O7R D16 I/O8R C16 I/O8L B16 NC A16 NC A15 NC B15 NC C15 NC D15 NC E15 I/O7L E14 NC D14 NC D13 VDD C12 A6L C14 OPTL B14 VDD A14 A0L A12 A5L B12 A4L C11 ADSL D12 VDDQR D11 VDDQR C10 CLKL B11 REPEATL A11 CNTENL VDDQR NC CE1L VDDQL LBL CE0L D10 VDDQL A7L UBL NC B13 A1L A13 A2L A10 OEL VDDQR A9L A8L A12L A10L VDDQL A14L A15L A13L VDDQL NC A16L PIPE/FTL NC TDO VSS NC I/O9R I/O9L NC TDI NC NC NC NC I/O10R I/O10L NC VDDQL I/O11L NC VDDQL NC NC I/O12L VDDQR NC I/O12R NC VDDQR I/O13L I/O14R I/O13R VDDQL NC NC I/O14L VDDQL I/O15L NC I/O15R VDDQR I/O16R I/O16L NC VDDQR NC I/O17R NC PIPE/ FTR NC I/O17L TMS A16R NC NC TRST NC NC TCK NC A17R(1) A13R A15R P12 A6R NC LBR UBR NC P10 CLKR T11 CNTENR P11 ADSR R12 A4R T12 A5R P13 A3R A7R R13 A1R T13 A2R A12R A14R T14 A0R R14 OPTR P14 NC P15 NC R15 NC T15 NC T16 NC R16 NC P16 I/O0L N16 NC N15 I/O0R N14 NC M16 NC M15 I/O1L M14 I/O1R L16 I/O2R L15 NC L14 I/O2L K16 I/O3L K15 NC K14 NC J16 I/O4L J15 I/O3R J14 I/O4R H16 I/O5R H15 NC H14 NC G16 NC G15 NC G14 I/O5L F16 I/O6L F14 I/O6R F15 NC CE0R R11 REPEAT R A11R CE1R A11L B10 R/WL C13 A3L A10R R10 R/WR A9R T10 OER A8R VDD VDD VSS VSS VSS E10 VSS E11 VDD E12 VDD E13 VDDQR VDD VSS VSS VSS F10 VSS F12 VDD F13 VDDQR VSS VSS VSS VSS VSS G10 VSS G11 VSS G12 VSS G13 VDDQL VSS VSS VSS VSS VSS H10 VSS H11 VSS H12 VSS H13 VDDQL VSS VSS VSS VSS VSS J10 VSS J11 VSS J12 VSS J13 VDDQR VSS VSS VSS VSS VDD VSS VSS VSS VDD VDD VSS VSS VDDQR VDDQR VDDQL VDDQL VSS K10 VSS K11 VSS K12 VSS VSS L10 VSS L11 VSS L12 VDD VSS M10 VSS M11 VDD M12 VDD VDDQR N10 VDDQR N11 VDDQL N12 VDDQL K13 VDDQR L13 VDDQL M13 VDDQL N13 VDD VSS F11 VSS 5623 drw 02d I/O11R 08/01/02 A17L(1)
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4,5,8,9) (con't.) NOTES: 1. A 17 is a NC for IDT70V3399. 2. All V DD pins must be connected to 3.3V power supply. 4. All V SS pins must be connected to ground supply. 5. Package body is approximately 14mm x 20mm x 1.4mm. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 8. PIPE/ FT option in PK-128 is not supported due to limitation in pin count. Device is pipelined outputs only on each port. 9. Due to the limited pin count, JTAG is not supported in the PK-128 package. 102 101 100 A14L A15L A16L A17L(1) IO9L IO9R VDDQL VSS IO10L IO10R VDDQR VSS IO11L IO11R IO12L IO12R VDD VDD VSS VSS IO13R IO13L IO14R IO14L IO15R IO15L VDDQL VSS IO16R IO16L VDDQR VSS IO17R IO17L A17R(1) A16R A15R A14R A1R A0R OPTR IO0L IO0R VDDQR VSS IO1L IO1R VDDQL VSS IO2L IO2R IO3L IO3R IO4L IO4R VSS VSS VDD VDD IO5L IO5R VDDQR VSS IO7R IO7L VDDQL VSS VSS IO8R IO8L VSS OPTL A0L A1L IO6R IO6L 70V3319/99PRF PK-128(6) 128-Pin TQFP Top View(7) 5623 drw 02a A 13L A 12L A 11L A 10L A A A UB L LB L CE CE V DD V DD V SS V SS CLK L OE L R/W L ADS L CNTEN L REPEATL A A A A A A 13R A 12R A 11R A 10R A A A UB R LB R CE CE V DD V DD V SS V SS CLK R OE R R/W R ADS R CNTEN R REPEATR A A A A A 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 08/06/02
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (6 ) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 17L(1 ) A0R - A 17R(1 ) Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock PIPE/FTL(5) PIPE/FTR(5 ) Pipeline/Flow-Through ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable REPEATL REPEATR Counter Repeat(4 ) UBL UBR Upper Byte Enable (I/O 9-I/O17)(6 ) LBL LBR Lower Byte Enable (I/O 0-I/O8)(6 ) VDDQ L VDDQR Power (I/O Bus) (3.3V or 2.5V) (2 ) OPTL OPTR Option for selecting V DDQX(2,3) VDD Power (3.3V)(2) VSS Ground (0V) TDI Test Data Input TDO Test Data Output TCK T est Logic Clock (10MHz) TMS T est Mode Select TRST Reset (Initialize TAP Controller) 562 3 tbl 01 1. A 17 is a NC for IDT70V3399. 2. V DD, OPT X, and V DDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 3. OPT X selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPT X is set to VIL (0V), then that port's I/Os and address controls will operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 4. When REPEAT X is asserted, the counter will reset to the last valid address loaded via ADSX. 5. PIPE/ FT option in PK-128 package is not supported due to limitation in pin count. Device is pipelined output mode only on each port. 6. Chip Enables and Byte Enables are double buffered when PL/ FT = VIH, i.e., the signals take two cycles to deselect. NOTES:
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE is an asynchronous input signal. Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O9-17 Lower Byte I/O0-8 MODE X ↑ HXXXX H i g h - Z H i g h - Z D e s e l e c t e d – P o w e r D o w n X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ LHHLL H i g h - Z D IN Write to Lower Byte Only X ↑ LHLHL D IN High-Z Write to Upper Byte Only X ↑ LHLLL D IN DIN Write to Both Bytes L ↑ LHHLH H i g h - Z D OUT Read Lower Byte Only L ↑ LHLHH D OUT High-Z Read Upper Byte Only L ↑ LHLLH D OUT DOUT Read Both Bytes H ↑ L H L L X High-Z High-Z Outputs Disabled 5623 tb l 0 2 Truth Table II—Address Counter Control(1,2) NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/ W, CE0, CE 1, UB, LB and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE 0, CE 1 and UB, LB. 5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE 1, UB, LB. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. Ex ternal Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT (6 ) I/O(3) MODE XX A n ↑ XX L (4 ) DI/O(0) Counter Reset to last valid ADS load An X An ↑ L (4) XH D I/O (n) External Address Used An Ap Ap ↑ HH H D I/O(p) External Address Blocked—Counter disabled (Ap reused) XA p A p + 1 ↑ H L (5) HD I/O(p+1) Counter Enabled—Internal Address generation 5623 tb l 0 3
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Recommended DC Operating Conditions with V DDQ at 2.5V Absolute Maximum Ratings(1) NOTES: 1. Undershoot of V IL > -1.5V for pulse width less than 10ns is allowed. 2. V TERM must not exceed V DDQ + 100mV. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied as indicated above. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed V DD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of V TERM > VDD + 150mV. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected. NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Grade Ambient Temperature GND V DD Commercial 0 OC to +70 OC0 V 3 . 3 V + 150mV Industrial -40 OC to +85 OC0 V 3 . 3 V + 150mV 562 3 tbl 04 Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.15 3.3 3.45 V VDDQ I/O Supp ly Voltage(3 ) 2.4 2.5 2.6 V VSS Ground 0 0 0 V VIH Input High Voltage (Address & Control Inputs) 1.7 ____ VDDQ + 100mV(2 ) V VIH Input High Voltage - I/O (3) 1.7 ____ VDDQ + 100mV(2 ) V VIL Input Low Voltage -0.3 (1) ____ 0.7 V 5623 tbl 05a Symbol Rating Commercial & Industrial Unit VTERM(2 ) T erminal Voltage with Respect to GND -0.5 to +4.6 V TBIAS(3) Temperature Under Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC TJN Junction Temperature +150 oC IOUT DC Output Current 50 mA 562 3 tbl 06 Recommended DC Operating Conditions with VDDQ at 3.3V NOTES: 1. Undershoot of V IL > -1.5V for pulse width less than 10ns is allowed. 2. V TERM must not exceed V DDQ + 150mV. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V IH (3.3V), and VDDQX for that port must be supplied as indicated above. Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.15 3.3 3.45 V VDDQ I/O Supply Voltage (3) 3.15 3.3 3.45 V VSS Ground 0 0 0 V VIH Input High Voltage (Address & Control Inputs) (3) 2.0 ____ VDDQ + 150mV(2) V VIH Inp ut Hig h Vo ltage - I/O(3) 2.0 ____ VDDQ + 150mV(2) V VIL Input Low Voltage -0.3 (1) ____ 0.8 V 5623 tbl 05b
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) NOTE: 1. At V DD < 2.0V leakages are undefined. Symbol Parameter Test Conditions 70V3319/99S UnitMin. Max. |ILI| Input Leakage Current (1 ) VDDQ = Max., V IN = 0V to V DDQ ___ 10 µA |ILO| Output Leakage Currentt (1 ) CE0 = V IH or CE 1 = V IL, VOUT = 0V to V DDQ ___ 10 µA VOL (3.3V) Output Low Voltage (2) IOL = +4mA, V DDQ = Min. ___ 0.4 V VOH (3 .3 V) O ut pu t H igh V olt age(2 ) IOH = -4mA, V DDQ = Min. 2.4 ___ V VOL (2.5V) Output Low Voltage (2) IOL = +2mA, V DDQ = Min. ___ 0.4 V VOH (2 .5 V) O ut pu t H igh V olt age(2 ) IOH = -2mA, V DDQ = Min. 2.0 ___ V 5623 tbl 08 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. C OUT also references C I/O. Capacitance(1)(TA = +25°C, F = 1.0MHZ) Symbol Parameter Conditions (2) Max. Unit CIN Input Capacit ance V IN = 3dV 8 pF COUT(3) Output Capacitance V OUT = 3dV 10.5 pF 5623 tbl 07
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV) NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. V DD = 3.3V, T A = 25°C for Typ, and are not production tested. I DD DC (f=0) = 120mA (Typ). 5. CEX = V IL means CE0X = V IL and CE 1X = V IH CEX = V IH means CE0X = V IH or CE 1X = V IL CEX < 0.2V means CE0X < 0.2V and CE 1X > VDDQ - 0.2V CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE 1X - 0.2V "X" represents "L" for left port or "R" for right port. 70V3319/99S166 Com'l Only 70V3319/99S133 Com'l & Ind Symbol Parameter Test Condition Version Typ. (4) Max. Typ. (4) Max . Unit IDD Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L S 370 500 320 400 mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL = CER = V IH, Outputs Disabled, f = fMAX(1) COM'L S 125 200 115 160 mA ISB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) COM'L S 250 350 220 290 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports Outputs Disabled CEL and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or V IN < 0.2V, f = 0 (2) COM'L S 15 30 15 30 mA ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDDQ - 0.2V (5) VIN > VDDQ - 0.2V or V IN < 0.2V Active Port, Out puts Disabled, f = f MAX(1) COM'L S 250 350 220 290 mA 5623 tbl 09
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges (Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) NOTES: 1. The Pipelined output parameters (t CYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = V IH. Flow-through parameters (t CYC1, t CD1) apply when FT/PIPE = V IL for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 70V3319/99S166 Com'l Only 70V3319/99S133 Com'l & Ind Symbol Parameter Min. Max. Min. Max. Unit tCYC1 Clock Cycle T ime (Flow-T hrough)(1) 20 ____ 25 ____ ns tCYC2 Clock Cycle T ime (Pipelined) (1) 6 ____ 7.5 ____ ns tCH1 Clock High Time (Flow-Through) (1) 6 ____ 7 ____ ns tCL1 Clock Low Time (Flow-Through) (1) 6 ____ 7 ____ ns tCH2 Clock High Time (Pipelined) (2) 2.1 ____ 2.6 ____ ns tCL2 Clock Low Time (Pipelined) (1) 2.1 ____ 2.6 ____ ns tSA Address Setup T ime 1.7 ____ 1.8 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ ns tSC Chip Enable Setup Time 1.7 ____ 1.8 ____ ns tHC Chip Enable Hold Time 0.5 ____ 0.5 ____ ns tSB Byte Enable Setup Time 1.7 ____ 1.8 ____ ns tHB Byte Enable Hold Time 0.5 ____ 0.5 ____ ns tSD Input Data Setup Time 1.7 ____ 1.8 ____ ns tHD Input Data Hold Time 0.5 ____ 0.5 ____ ns tSAD ADS Setup Time 1.7 ____ 1.8 ____ ns tSCN CNTEN Setup Time 1.7 ____ 1.8 ____ ns tHCN CNTEN Hold Time 0.5 ____ 0.5 ____ ns tSRPT REPEAT Setup Time 1.7 ____ 1.8 ____ ns tHRPT REPEAT Hold Time 0.5 ____ 0.5 ____ ns tOE Output Enable to Data Valid ____ 4.0 ____ 4.2 ns tOLZ Output Enable to Output Low-Z 1 ____ 1 ____ ns tOHZ Output Enable to Output High-Z 1 3.6 1 4.2 ns tCD1 Clock to Data Valid (Flow-Through) (1) ____ 12 ____ 15 ns tCD2 Clock to Data Valid (Pipelined) (1) ____ 3.6 ____ 4.2 ns tDC Data Output Hold After Clock High 1 ____ 1 ____ ns tCKHZ Clock High to Output High-Z 1 3 1 3 ns tCKLZ Clock High to Output Low-Z 1 ____ 1 ____ ns Port-to-Port Delay tCO Clock-to-Clock Offset 5 ____ 6 ____ ns 5623 tbl 11
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE1 UB, LB (3) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 5623 drw 06 (1) (1) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (4) (1 Latency) (5) (5) Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(2) NOTES: 1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ADS = V IL, CNTEN and REPEAT = V IH. 3. The output is disabled (High-Impedance state) by CE0 = V IH, CE 1 = V IL, UB, LB = V IH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If UB, LB was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(2,6) An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/W ADDRESS DATAOUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 5623 drw 07 (5) (1) CE1 UB, LB (3) tSB tHB tSW tHW tSA tHA tDC tDC (4) tSC tHC tSB tHB
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges tSC tHC CE0(B1) ADDRESS(B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK Q0 Q1 Q3DATAOUT(B1) tCH2 tCL2 tCYC2 ADDRESS(B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATAOUT(B2) Q2 Q4 tCD2 tCD2 tCKHZ tCD2 tCKLZtDC tCKHZ tCD2 tCKLZ tSC tHC tCKHZ tCKLZ tCD2 tDC tSC tHC tSC tHC 5623 drw 08 Timing Waveform of a Multi-Device Pipelined Read(1,2) NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3319/99 for this waveform, and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = V IL; CE 1(B1), CE 1(B2), R/ W, CNTEN, and REPEAT = V IH. Timing Waveform of a Multi-Device Flow-Through Read(1,2) tSC tHC CE0(B1) ADDRESS(B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 5623 drw 09 D0 D3 tCD1 tCKLZ tCKHZ (1) (1) D1DATAOUT(B1) tCH1 tCL1 tCYC1 (1) ADDRESS(B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATAOUT(B2) D2 D4 tCD1 tCD1 tCKHZ tDC tCD1 tCKLZ tSC tHC (1) tCKHZ (1) tCKLZ (1) tCD1 tDC tSC tHC tSC tHC tCD1 tCKLZ (1) tCKHZ (1)
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges CLK"A" R/W"A" ADDRESS"A" DATAIN"A" CLK"B" R/W"B" ADDRESS"B" DATAOUT"B" tSW tHW tSA tHA tSD tHD tSW tHW tSA tHA tCO(3) tCD2 NO MATCH VALID NO MATCHMATCH MATCH VALID 5623 drw 10tDC Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4) NOTES: 1. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 2. OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to. 3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to val id read on opposite port will be tCO + 2 t CYC2 + t CD2). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on oppos ite port will be t CO + t CYC2 + t CD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A" Timing Waveform with Port-to-Port Flow-Through Read(1,2,4) DATAIN "A" CLK "B" R/W "B" ADDRESS"A" R/W "A" CLK "A" ADDRESS"B" NO MATCHMATCH NO MATCHMATCH VALID tCD1 tDC DATAOUT "B" 5623 drw 11 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCO tDC tSA tSW tHA (3) NOTES: 1. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to. 3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to v alid read on opposite port will be tCO + t CYC + t CD1). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on oppo site port will be tCO + t CD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 CE0 CLK 5623 drw 12 Qn Qn + 3DATAOUT CE1 UB, LB tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (3) (1) tSW tHW WRITE (4) Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATAIN Dn + 3Dn + 2 CE0 CLK 5623 drw 13 DATAOUT Qn Qn + 4 CE1 UB, LB OE tCH2 tCL2 tCYC2 tCKLZ tCD2 tOHZ tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (3) (1) tSW tHW (4) Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if tim ing so allows.
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2) Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE 0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATAIN Dn + 2 CE0 CLK 6523 drw 14 QnDATAOUT CE1 UB, LB tCD1 Qn + 1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tCD1 tDC tCKHZ Qn + 3 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ NOP READ tCKLZ (3) (1) tSW tHW WRITE(5) R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5(3) DATAIN Dn + 2 CE0 CLK 5623 drw 15 QnDATAOUT CE1 UB, LB tCD1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tDC Qn + 4 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ WRITE READ tCKLZ (1) Dn + 3 tOHZ tSW tHW OE tOE
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges ADDRESS An CLK DATAOUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3 ADS CNTEN tCYC2 tCH2 tCL2 5623 drw 16 tSA tHA tSAD tHAD tCD2 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tSAD tHAD tSCN tHCN READ WITH COUNTER Qn + 1 Timing Waveform of Pipelined Read with Address Counter Advance(1) NOTES: 1. CE0, OE, UB, LB = V IL; CE 1, R/ W, and REPEAT = V IH. 2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH, then the data output remains constant for subsequent clocks. Timing Waveform of Flow-Through Read with Address Counter Advance(1) ADDRESS An CLK DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 ADS CNTEN tCYC1 tCH1 tCL1 5623 drw 17 tSA tHA tSAD tHAD READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tCD1 tDC tSAD tHAD tSCN tHCN READ WITH COUNTER
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges ADDRESS An tCH2 tCL2 tCYC2 QLAST QLAST+1 LAST ADS LOAD CLK DATAIN R/W REPEAT 5623 drw 19 INTERNAL(3) ADDRESS ADS CNTEN tSRPT tHRPT tSD tHD tSW tHW EXECUTE REPEAT WRITE LAST ADS ADDRESS READ LAST ADS ADDRESS READ LAST ADS ADDRESS + 1 READ ADDRESS n Qn An + 1 An + 2 READ ADDRESS n+1 DATAOUT tSA tHA LAST ADS +1 An An + 1 (4) (5) (6) Ax tSAD tHAD tSCN tHCN Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs)(1) Timing Waveform of Counter Repeat(2) NOTES: 1. CE0, UB, LB, and R/ W = V IL; CE 1 and REPEAT = V IH. 2. CE0, UB, LB = V IL; CE 1 = V IH. 3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II. 7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. T he ‘An +1’Address is written to during this cycle. ADDRESS An CLK DATAIN Dn Dn + 1 Dn + 1 Dn + 2 ADS CNTEN tCH2 tCL2 tCYC2 5623 drw 18 INTERNAL(3) ADDRESS An(7) An + 1 An + 2 An + 3 An + 4 Dn + 3 Dn + 4 tSA tHA tSAD tHAD WRITE COUNTER HOLD WRITE WITH COUNTERWRITE EXTERNAL ADDRESS WRITE WITH COUNTER tSD tHD tSCN tHCN
0 LOW and
CE1 HIGH to re-activate the outputs. various chip enables in order to expand two devices in depth. applications needing 36-bits or wider. Figure 4. Depth and Width Expansion with IDT70V3319/99
- 30pF loading on external output signals.
- Refer to AC Electrical Test Conditions stated earlier in this document.
- JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet. Figure 5. Standard JTAG Timing
- Device inputs = All device inputs except TDI, TMS, and TRST.
- Device outputs = All device outputs except TDO.
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 0x0 Reserved f or version number IDT Device ID (27:12) 0x0314(1) Defines IDT part number IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT ID Register Indicator Bit (Bit 0) 1 I ndicates t he presence of an I D register 562 3 tbl 1 3 Scan Register Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Id entificatio n (IDR) 32 Boundary Scan (BSR) Note (3) 562 3 tbl 14 System Interface Parameters Instruction Code Description EXT EST 0000 Forces cont ents of t he boundary scan cells onto the device out puts (1). Places t he boundary scan regist er (BSR) bet ween TDI and TDO. BYPASS 1 11 1 Places the bypass register (BYR) between TDI and TDO. IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. HIGHZ 001 1 Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2 ) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the b oundary scan cells via the TDI. RESERVED All other codes Several combinations are reserved. Do not use codes other than those identified above. 562 3 tbl 1 5 NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by conta cting your local IDT sales representative. NOTE: 1. Device ID for IDT70V3399 is 0x0315.
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
Ordering Information
Dual-Port I/O Specitications Clock Specifications IDT PLL Clock DeviceVoltage I/O Input Capacitance Input Duty Cycle Requirement Maximum Frequency Jitter Tolera nce 70V3319/99 3.3/2.5 LVTTL 8pF 40% 166 75ps IDT5V2528 5623 tbl 16a IDT Clock Solution for IDT70V3319/99 Dual-Port NOTE: 1. Green parts available. For specific speeds, packages and powers contact your local sales office.
6.42 IDT70V3319/99S High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History: 06/02/00: Initial Public Offering 07/12/00: Page 1 Added mux to functional block diagram 06/20/01: Page 1 Added JTAG information for TQFP package Page 4 Corrected TQFP package size 07/30/01: Page 1 Added PL/ FToption Page 20 Changed maximum value for JTAG AC Electrical Characteristics for t JCD from 20ns to 25ns Page 9 Added Industrial Temperature DC Parameters 11/20/01: Page 2, 3 & 4 Added date revision for pin configurations Page 11 Changed t OE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05 Page 1 & 22 Replaced TM logo with ® logo Page 10 Changed AC Test Conditions Input Rise/Fall Times 08/06/02: Consolidated multiple devices into one datasheet Page 1 & 5 Added DCD capability for Pipelined Outputs Page 7 Clarified T BIAS and added TJN Page 9 Changed DC Electrical Parameters Page 11 Removed Clock Rise & Fall Time from AC Electrical Characteristics Table Removed Preliminary status 05/19/03: Page 11 Added Byte Enable SetupTime & Byte Enable Hold Time to AC Elecctrical Characteristics Table Page 22 Added IDT Clock Solution Table 02/08/06: Page 1 Added green availability to features Page 6 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = V IH to ADS, CNTEN, REPEAT = X Page 22 Added green indicator to ordering information 07/25/08: Page 9 Corrected a typo in the DC Chars table 01/19/09: Page 22 Removed "IDT" from orderable part number 10/03/14: Page 22 Added Tape & Reel to the Ordering Information The IDT logo is a registered trademark of Integrated Device Technology, Inc. CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@ idt.com www.idt.com