IDT70V05S_12 IDT | Alldatasheet

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  • Manufacturer or author: lruddell
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Technical content

Features

◆◆◆◆◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20ns (max.) ◆◆◆◆◆ Low-power operation – IDT70V05S Active: 400mW (typ.) Standby: 3.3mW (typ.) – IDT70V05L Active: 380mW (typ.) Standby: 660 µW (typ.) ◆◆◆◆◆ IDT70V05 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆◆◆◆◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆◆◆◆◆ On-chip port arbitration logic ◆◆◆◆◆ Full on-chip hardware support of semaphore signaling between ports ◆◆◆◆◆ Fully asynchronous operation from either port ◆◆◆◆◆ TTL-compatible, single 3.3V (±0.3V) power supply ◆◆◆◆◆ Available in 68-pin PGA and PLCC, and a 64-pin TQFP ◆◆◆◆◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆◆◆◆◆ Green parts available, see ordering information Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/WL CEL OEL BUSYL A12L A0L 2942 drw 01 I/O0L-I / O7L CEL OEL R/WL SEML INTL M/S BUSYR I/O0R-I/O7R A12R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/WR CER OER 1313 R/WR

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit- or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 400mW of power. The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC and a 64-pin thin quad flatpack (TQFP). Pin Configurations(1,2,3) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. PN64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking 2941 drw 02 INDEX 987 6543 216 8 6 7 6 6 6 5 27 28 29 30 31 32 33 34 35 36 37 38 39 V DD VDD I/O1R I/O2R I/O3R I/O4R INTL VSS A4L A3L A2L A1L A0L A3R A0R A1R A2R I/O2L A5L R/W L M/S 40 41 42 43 64 63 62 61 I/O3L VSS I/O0R VDD A4R BUSYL VSS BUSYR INTR A 12R I/O N/C V SS OE R R/W R SEM R CE R OE L SEM L CE L N/C I/O I/O IDT70V05J J68-1(4) 68-Pin PLCC Top View(5) I/O4L I/O5L I/O6L I/O7L I/O5R I/O6R N/C A 12L A 11R N/C A 10R A A A A A A 11L A 10L A A A A N/C N/C 12/03/01 INDEX 70V05PF PN-64(4) 64-Pin TQFP Top View(5) 17 18 19 20 323130292827262524232221 4950515263 62 61 60 59 58 57 56 55 54 5364 I/O2L VDD VSS VSS A4R BUSYL BUSYR INTR INTL VSS M/S OEL A5L I/O R/W L CEL SEM L V DD N/C N/C OER CER R/W R SEM R A12R GND I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O I/O A11R A10R A9R A8R A7R A6R A5R A3R A2R A1R A0R A0L A1L A2L A3L A4L A6L A7L A8L A9L A10L A11L A12L I/O 2941 drw 03 12/03/01

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 4. This package code is used to reference the package diagram. 5. This text does not indicate oriention of the actual part-marking. Pin Configurations(1,2,3) (con't.) 2941 drw 04 51 50 48 46 44 42 40 38 36 13579 11 13 15 IDT70V05G G68-1(4) 68-Pin PGA Top View(5) ABCDEFGH JKL 47 45 43 41 34 24681 0 1 2 1 4 1 6 18 19 49 39 37 A5L INTL N/C SEML CEL VDD OEL R/WL I/O0L N/C VSS VSS I/O0R VDD N/C OER R/WR SEMR CER VSS BUSYR BUSYL M/S INTR N/C VSS A1R N/C N/C INDEX A4L A2L A0L A3R A2R A4R A5R A7R A6R A9R A8R A11R A10R A12R A0RA7L A6L A3L A1L A9L A8L A11L A10L A12L VDD I/O2R I/O3R I/O5R I/O6R I/O1R I/O4R I/O7RI/O1L I/O2L I/O4L I/O7L I/O3L I/O5L I/O6L 12/03/01 Pin Names troPtfeLt roPthgiRs emaN EC L EC R elbanEpihC /R WL /R WR elbanEetirW/daeR EO L EO R elbanEtuptuO A0L A- 21 L A0R A- 21 R sserddA O/I 0L O/I- 7L O/I 0R O/I- 7R tuptuO/tupnIataD MES L MES R elbanEerohpameS TNI L TNI R galFtpurretnI YSUB L YSUB R galFysuB /M S tceleSevalSroretsaM VDD )v3.3(rewoP VSS )v0(dnuorG 00lbt1492

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I: Non-Contention Read/Write Control Truth Table II: Semaphore Read/Write Control(1) NOTE: 1. A 0L — A 12L≠ A0R — A 12R NOTE: 1. There are eight semaphore flags written to via I/O 0 and read from I/O0 -I/O7. These eight semaphores are addressed by A0-A2. stupnI )1( stuptuO edoMEC /R W EOM ES O/I 7-0 HXXH Z -hgiHn woD-rewoP:detceleseD LLXH A TAD NI yromeMotetirW LHLH A TAD TUO yromeMdaeR XXHX Z -hgiHd elbasiDstuptuO 20lbt1492 stupnI )1( stuptuO edoMEC /R W EOM ES O/I 7-0 HHL L A TAD TUO galFerohpameSniataDdaeR H ↑ XL A TAD NI tirW e O/I 0 galFerohpameSotni LXXL ____ dewollAtoN 30lbt1492

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) Recommended DC Operating Conditions Maximum Operating Temperature and Supply Voltage (1) Absolute Maximum Ratings(1) Capacitance (TA = +25°C, f = 1.0MHz) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed V DD + 0.3V. NOTE: 1. This is the parameter T A. This is the "instant on" case temperature. NOTES: 1. V IL> -1.5V for pulse width less than 10ns. 2. V TERM must not exceed V DD +0.3V. lobmySg nitaRl aicremmoC lairtsudnI& tinU V MRET )2( egatloVlanimreT tcepseRhtiw DNGot 6.4+ot5.0-V T SAIB erutarepmeT saiBrednU 521+ot55- oC T GTS egarotS erutarepmeT 051+ot56- oC I TUO tuptuOCD tnerruC 05A m 40lbt1492 edarGe rutarepmeTtneibmAD NGV DD laicremmoC0 O 07+otC OCV 0V 3.3 + V3.0 lairtsudnI0 4- O 58+otC OCV 0V 3.3 + V3.0 50lbt1492 lobmySr etemaraP. niM. pyT. xaMt inU VDD egatloVylppuS0 .33 .36 .3V VSS dnuorG0 0 0 V V HI egatloVhgiHtupnI0 .2 ____ VDD 3.0+ )2( V V LI egatloVwoLtupnI5 .0- )1( ____ 8.0V 60lbt1492 lobmySr etemaraP )1( snoitidnoC. xaMt inU CNI ecnaticapaCtupnIV NI Vd3=9 F p C TUO ecnaticapaCtuptuOV TUO Vd3=0 1F p 70lbt1492 lobmySr etemaraPs noitidnoCtseT S50V07L 50V07 tinU.niM. xaM. niM. xaM I| LI|t nerruCegakaeLtupnI )1( V DD V,V6.3= NI VotV0= DD ___ 01 ___ 5A µ I| OL |t nerruCegakaeLtuptuOV TUO VotV0= DD ___ 01 ___ 5A µ V LO egatloVwoLtuptuOI LO Am4+= ___ 4.0 ___ 4.0V V HO egatloVhgiHtuptuOI HO Am4-=4 .2 ___ 4.2 ___ V 80lbt1492 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitznce when the input and output signals switch from 0V to 3V or from 3V to 0V. NOTE: 1. At V DD < 2.0V input leakages are undefined.

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V) NOTES: 1. “X” in part number indicates power rating (S or L) 2. V DD = 3.3V, T A = +25°C, and are not production tested. I DD DC = 115mA (Typ.) 3. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 51X50V07 ylnOl'moC 02X50V07 l'moC dnI& 52X50V07 ylnOl'moC IDD gnitarepOcimanyD tnerruC )evitcAstroPhtoB( EC V= LI delbasiDstuptuO, MES V= HI f=f XAM )3( L'MOCS L 051 041 512 581 041 031 002 571 031 521 091 561 Am DNIS L ____ ____ ____ ____ 041 031 522 591 ____ ____ ____ ____ Am I 1BS tnerruCybdnatS LTT-stroPhtoB( )stupnIleveL EC R = EC L V= HI MES R = MES L V= HI f=f XAM )3( L'MOCS L Am DNIS L ____ ____ ____ ____ ____ ____ ____ ____ Am I 2BS tnerruCybdnatS LTT-troPenO( )stupnIleveL EC L ro EC R V= HI ,delbasiDstuptuOtroPevitcA f=f XAM )3( L'MOCS L 021 011 011 001 011 Am DNIS L ____ ____ ____ ____ 031 511 ____ ____ ____ ____ Am I 3BS tnerruCybdnatSlluF -stroPhtoB( )stupnIleveLSOMC stroPhtoB EC L dna EC R > VDD ,V2.0- V NI > VDD roV2.0- V NI < 0=f,V2.0 )4( MES R = MES L > VDD V2.0- L'MOCS L 0.1 2.0 5.2 0.1 2.0 5.2 0.1 2.0 5.2 Am DNIS L ____ ____ ____ ____ 0.1 2.0 ____ ____ ____ ____ Am I 4BS tnerruCybdnatSlluF -troPenO( )stupnIleveLSOMC troPenO EC L ro EC R > VDD V2.0- MES R = MES L > VDD V2.0- V NI > VDD VroV2.0- NI < V2.0 ,delbasiDstuptuOtroPevitcA f=f XAM )3( L'MOCS L 521 501 511 001 501 Am DNIS L ____ ____ ____ ____ 031 511 ____ ____ ____ ____ Am a90lbt1492 53X50V07 ylnOl'moC 55X50V07 ylnOl'moC lobmySr etemaraPn oitidnoCtseTn oisreV. pyT )2( .xaM. pyT )2( .xaMt inU IDD gnitarepOcimanyD tnerruC )evitcAstroPhtoB( EC V= LI delbasiDstuptuO, MES V= HI f=f XAM )3( L'MOCS L 021 511 081 551 021 511 081 551 Am DNIS L 021 511 002 071 021 511 002 071 Am I 1BS tnerruCybdnatS LTT-stroPhtoB( )stupnIleveL EC R = EC L V= HI MES R = MES L V= HI f=f XAM )3( L'MOCS L Am DNIS L Am I 2BS tnerruCybdnatS LTT-troPenO( )stupnIleveL EC L ro EC R V= HI ,delbasiDstuptuOtroPevitcA f=f XAM )3( L'MOCS L 001 001 Am DNIS L 021 501 021 501 Am I 3BS tnerruCybdnatSlluF -stroPhtoB( )stupnIleveLSOMC stroPhtoB EC L dna EC R > VDD ,V2.0- V NI > VDD roV2.0- V NI < 0=f,V2.0 )4( MES R = MES L > VDD V2.0- L'MOCS L 0.1 2.0 5.2 0.1 2.0 5.2 Am DNIS L 0.1 2.0 0.1 2.0 Am I 4BS tnerruCybdnatSlluF -troPenO( )stupnIleveLSOMC troPenO EC L ro EC R > VDD V2.0- MES R = MES L > VDD V2.0- V NI > VDD VroV2.0- NI < V2.0 ,delbasiDstuptuOtroPevitcA f=f XAM )3( L'MOCS L 001 001 Am DNIS L 511 001 511 001 Am b90lbt1492

Figure 1. AC Output Test Load Figure 2. Output Test Load

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is determined by device characterization but is not production tested. 3. To access SRAM, CE = V IL, SEM = V IH. 4. 'X' in part number indicates power rating (S or L). Operating Temperature and Supply Voltage Range(4) 51X50V07 ylnOl'moC 02X50V07 l'moC dnI& 52X50V07 ylnOl'moC ELCYCDAER t DP emiTnwoDrewoPotelbasiDpihC )2,1( ____ 51 ____ 02 ____ 52s n t POS (esluPetadpUgalFerohpameS EO ro MES )0 1 ____ 01 ____ 01 ____ sn a11lbt1492 53X50V07 ylnOl'moC 55X50V07 ylnOl'moC tinUlobmySr etemaraP. niM. xaM. niM. xaM ELCYCDAER t AA emiTsseccAsserddA ____ 53 ____ 55s n t ECA emiTsseccAelbanEpihC )3( ____ 53 ____ 55s n t EOA emiTsseccAelbanEtuptuO )3( ____ 02 ____ 03s n t HO egnahCsserddAmorfdloHtuptuO 3 ____ 3 ____ sn t ZL emiTZ-woLtuptuO )2,1( 3 ____ 3 ____ sn t ZH emiTZ-hgiHtuptuO )2,1( ____ 51 ____ 52s n t UP emiTpUrewoPotelbanEpihC )2,1( 0 ____ 0 ____ sn t DP emiTnwoDrewoPotelbasiDpihC )2,1( ____ 53 ____ 05s n t POS (esluPetadpUgalFerohpameS EO ro MES )5 1 ____ 51 ____ sn t AAS sseccAsserddAerohpameS )3( ____ 53 ____ 55s n b11lbt1492

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simul taneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last t AOE, tACE, tAA or tBDD. 5. SEM = VIH. tRC R/W CE ADDR tAA OE 2941 drw 07 (4) tACE (4) tAOE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4)

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is determined by device characterization but is not production tested. 3. To access SRAM, CE = V IL, SEM = V IH. To access semaphore, CE = V IH and SEM = V IL. Either condition must be valid for the entire t EW time. 4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. “X” in part number indicates power rating (S or L). Operating Temperature and Supply Voltage(5) lobmySr etemaraP 51X50V07 ylnOl'moC 02X50V07 l'moC dnI& 52X50V07 ylnOl'moC ELCYCETIRW t WE etirW-fo-dnEotelbanEpihC )3( 21 ____ 51 ____ 02 ____ sn t ZW Z-hgiHnituptuOotelbanEetirW )2,1( ____ 01 ____ 21 ____ 51s n t WO etirW-fo-dnEmorfevitcAtuptuO )4,2,1( 0 ____ 0 ____ 0 ____ sn a21lbt1492 lobmySr etemaraP 53X50V07 ylnOl'moC 55X50V07 ylnOl'moC tinU.niM. xaM. niM. xaM ELCYCETIRW t WE etirW-fo-dnEotelbanEpihC )3( 03 ____ 54 ____ sn t WA etirW-fo-dnEotdilaVsserddA 03 ____ 54 ____ sn t SA emiTpu-teSsserddA )3( 0 ____ 0 ____ sn t WD etirW-fo-dnEotdilaVataD 51 ____ 03 ____ sn t ZH emiTZ-hgiHtuptuO )2,1( ____ 51 ____ 52s n t ZW Z-hgiHnituptuOotelbanEetirW )2,1( ____ 51 ____ 52s n t WO etirW-fo-dnEmorfevitcAtuptuO )4,2,1( 0 ____ 0 ____ sn t DRWS MES emiTdaeRotetirWgalF 5 ____ 5 ____ sn t SPS MES wodniWnoitnetnoCgalF 5 ____ 5 ____ sn b21lbt1492

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8) NOTES: 1. R/ W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE, or R/W. 7. Timing depends on which enable signal is de-asserted first, CE, or R/W. 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. 9. To access RAM, CE = V IL and SEM = V IH. To access Semaphore, CE = V IH and SEM = V IL. tEW must be met for either condition. Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8) 2941 drw 09 tWC tAS tWR tDW tDH ADDRESS DATAIN CE or SEM R/W tAW tEW (3) (2) (6) (9) R/W tWC tHZ tAW tWRtAS tWP DATAOUT (2) tWZ tDW tDH tOW OE ADDRESS DATAIN CE (6) (4) (4) (3) 2941 drw 08 (7) (7) or SEM (9)

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTE: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. “DATA OUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) SEM"A" 2941 drw 11 tSPS MATCH R/W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/W"B" A0"B"-A2"B" SIDE "B" (2) NOTES: 1. D OR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/ W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If t SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtai n the flag. SEM 2941 drw 10 tAW tEW tSOP DATA0 VALID ADDRESS tSAA R/W tWR tOH t tACE VALID ADDRESS DATAIN VALID DATA OUT tDW tWP tDHtAS tSWRD tAOE tSOP Read CycleWrite Cycle A0-A2 OE VALID(2)

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With Port- To-Port Delay (M/S = VIL)”. 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. 'X' is part number indicates power rating (S or L). Operating Temperature and Supply Voltage Range(6) 51X50V07 ynOl'moC 02X50V07 l'moC dnI& 52X50V07 ylnOl'moC YSUB /M(GNIMIT S V= HI ) t AAB YSUB hctaMsserddAmorfemiTsseccA ____ 51 ____ 02 ____ 02s n t ADB YSUB dehctaMtoNsserddAmorfemiTelbasiD ____ 51 ____ 02 ____ 02s n t CAB YSUB WOLelbanEpihCmorfemiTsseccA ____ 51 ____ 02 ____ 02s n t CDB YSUB HGIHelbanEpihCmorfemiTelbasiD ____ 51 ____ 71 ____ 71s n t SPA emiTpu-teSytiroirPnoitartibrA )2( 5 ____ 5 ____ 5 ____ sn t DDB YSUB ataDdilaVotelbasiD )3( ____ 81 ____ 03 ____ 03s n YSUB /M(GNIMIT S V= LI ) GNIMITYALEDTROP-OT-TROP t DDD yaleDataDdaeRotdilaVataDetirW )1( ____ 52 ____ 53 ____ 53s n a31lbt1492 53X50V07 ylnOl'moC 55X50V07 ylnOl'moC lobmySr etemaraP. niM. xaM. niM. xaMt inU YSUB /M(GNIMIT S V= HI ) t AAB YSUB hctaMsserddAmorfemiTsseccA ____ 02 ____ 54s n t ADB YSUB dehctaMtoNsserddAmorfemiTelbasiD ____ 02 ____ 04s n t CAB YSUB WOLelbanEpihCmorfemiTsseccA ____ 02 ____ 04s n t CDB YSUB HGIHelbanEpihCmorfemiTelbasiD ____ 02 ____ 53s n t SPA emiTpu-teSytiroirPnoitartibrA )2( 5 ____ 5 ____ sn t DDB YSUB ataDdilaVotelbasiD )3( ____ 53 ____ 04s n t HW retfAdloHetirW YSUB )5( 52 ____ 52 ____ sn YSUB /M(GNIMIT S V= LI ) t BW YSUB etirWottupnI )4( 0 ____ 0 ____ sn t HW retfAdloHetirW YSUB )5( 52 ____ 52 ____ sn GNIMITYALEDTROP-OT-TROP t DDW yaleDataDotesluPetirW )1( ____ 06 ____ 08s n t DDD yaleDataDdaeRotdilaVataDetirW )1( ____ 54 ____ 56s n b31lbt1492

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 2941 drw 12 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD tBAA Timing Waveform of Write with Port-to-Port Read with BUSY(2,4,5) (M/S=VIH) NOTES: 1. To ensure that the earlier of the two ports wins. t APS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/ S = VIL (SLAVE) then BUSY is input. For this example, BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) NOTES: 1. t WH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY“B” goes HIGH. 3. t WB is only for the slave version. 2941 drw 13 R/W"A" BUSY"B" tWP tWB R/W"B" tWH (1) (2) (3) 2941 drw 14 ADDR"A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 2941 drw 15 ADDR"A" ADDRESS "N" ADDR"B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N"

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range(1) NOTES: 1. 'X' in part number indicates power rating (S or L). 51X50V07 ylnOl'moC 02X50V07 l'moC dnI& 52X50V07 ylnOl'moC GNIMITTPURRETNI a41lbt1492 53X50V07 ylnOl'moC 55X50V07 ylnOl'moC lobmySr etemaraP. niM. xaM. niM. xaMt inU GNIMITTPURRETNI t SNI emiTteStpurretnI ____ 52 ____ 04s n t RNI emiTteseRtpurretnI ____ 52 ____ 04s n b41lbt1492

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 2941 drw 17 ADDR"B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR (3) INT"B" (2) Waveform of Interrupt Timing(1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal ( CE or R/W) is asserted last. 4. Timing depends on which enable signal ( CE or R/W) is de-asserted first. 2941 drw 16 ADDR"A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR (3) (4) tINS (3) INT"B" (2)

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. V IL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence (1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05. 2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Truth Table III — Interrupt Flag (1) NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. troPtfeLt roPthgiR noitcnuFR/WL EC L EO L A L21 A- L0 TNI L /R WR EC R EO R A R21 A- R0 TNI R LLX F FF1 XXXX X L )2( thgiRteS TNI R galF X X XXX X L L F FF1H )3( thgiRteseR TNI R galF XXX X L )3( LLX E FF1X t feLteS TNI L galF XLL E FF1H )2( X X XXX t feLteseR TNI L galF 51lbt1492 stupnIs tuptuO noitcnuFEC L EC R A L21 A- L0 A R21 A- R0 YSUB L )1( YSUB R )1( XX H CTAMONH H l amroN HX H CTAMH H l amroN XH H CTAMH H l amroN LL H CTAM) 2() 2(t ibihnIetirW )3( 61lbt1492 snoitcnuFD 0 D- 7 tfeLD 0 D- 7 thgiRs utatS noitcAoN1 1 e erferohpameS erohpameSot"0"setirWtroPtfeL0 1 n ekoterohpamessahtroptfeL erohpameSot"0"setirWtroPthgiR0 1 e rohpamesotsseccaetirwonsahedisthgiR.egnahcoN erohpameSot"1"setirWtroPtfeL1 0 n ekoterohpamessniatbotropthgiR erohpameSot"0"setirWtroPtfeL1 0 e rohpamesotsseccaetirwonsahtroptfeL.egnahcoN erohpameSot"1"setirWtroPthgiR0 1 n ekoterohpamessniatbotroptfeL erohpameSot"1"setirWtroPtfeL1 1 e erferohpameS erohpameSot"0"setirWtroPthgiR1 0 n ekoterohpamessahtropthgiR erohpameSot"1"setirWtroPthgiR1 1 e erferohpameS erohpameSot"0"setirWtroPtfeL0 1 n ekoterohpamessahtroptfeL erohpameSot"1"setirWtroPtfeL1 1 e erferohpameS 71lbt1492

Truth Table III for the interrupt operation. as a slave (M/S pin = VIL) as shown in Figure 3. address signals only. It ignores whether an access is a read or write. and corrupted data in the slave. an additional 8 address locations dedicated to binary semaphore flags. Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or accessed, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non- semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table II where CE and SEM are both HIGH. Systems which can best use the IDT70V05 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V05's hardware sema- phores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V05 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are indepen- dent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V05 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A 0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two sema- phore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch.

made to one port or the other. are misused or misinterpreted, a software error can easily happen. dedicated at any one time to servicing either the left or right port. indicator for the upper section of memory. 4K blocks of Dual-Port SRAM with each other. being given a common meaning as was shown in the example above. during a transfer and the I/O device cannot tolerate any wait states. ously without any wait states. assigned SRAM segments at full speed. teeing a consistent data structure. Figure 4. IDT70V05 Semaphore Logic

6.42 IDT70V05S/L High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) A G(2) Green PF G J 64-pin TQFP (PN64-1) 68-pin PGA (G68-1) 68-pin PLCC (J68-1) S L Standard Power Low Power XXXXX Device Type 64K (8K x 8) 3.3V Dual-Port RAM70V05 Speed in nanoseconds Commercial Only Commercial & Industrial Commercial Only Commercial Only Commercial Only A Tube or Tray Tape and Reel Blank Datasheet Document History 3/11/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 and 3 Added additional notes to pin configurations 6/9/99: Changed drawing format 11/10/99: Replace d IDT logo 3/10/00: Added 15 & 20ns speed grades Upgraded DC parameters Added Industrial Temperature information Changed ±200mV to 0mV in notes 5/26/00: Page 5 Increased storage temperature parameter Clarified T A parameter Page 6 DC Electrical parameters2–changed wording from open to disabled 12/04/01: Page 2 & 3 Added date revision to pin configurations Page 2, 3, 5 & 6 Changed naming conventions from VCC to VDD and from GND to VSS Page 6, 8, 10, 13 & 16 Removed industrial temp for 25ns, 35ns and 55ns from DC & AC Electrical Characteristics Page 22 Removed industrial temp from 25ns, 35ns and 55ns from ordering information Page 1 & 22 Replaced TM logo with ® logo 07/27/06: Page 1 Added green availability to features Page 22 Added green indicator to ordering information 10/23/08: Page 22 Removed "IDT" from orderable part number 06/14/12: Page 11 Corrected footnote 9 from VIN to VIH, to read "To access RAM, CE = VIL and SEM = VIH". Page 22 Added T& R indicator to ordering information CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPo rtHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. NOTE: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office.