IDT70T3339_18 IDT | Alldatasheet

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©2018 Integrated Device Technology, Inc. FEBRUARY 2018 DSC-5652/9 HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70T3339/19/99S Functional Block Diagram – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz – Self-timed write allows fast cycle time ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ Dual Cycle Deselect (DCD) for Pipelined Output Mode ◆ 2.5V (±100mV) power supply for core ◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port ◆ Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz ◆ Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine pitch Ball Grid Array (fpBGA) ◆ Supports JTAG features compliant with IEEE 1149.1 ◆ Green parts available, see ordering information Features: ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed data access – Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) ◆ Selectable Pipelined or Flow-Through output mode ◆ Counter enable and repeat features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Interrupt and Collision Detection Flags ◆ Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out – Data input, address, byte enable and control registers 1. Address A 18 is a NC for the IDT70T3319. Also, Addresses A 18 and A 17 are NC's for the IDT70T3399. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. NOTES: Dout0-8_L B W L B W L Din_L OEL UBL LBL R/WL CE0L CE 1L ab FT/PIPEL 0/1 1b 0b 1a 0a 0b 1b0a 1a ab FT/PIPEL REPEATR A 0R CNTENR ADSR Dout0-8_R Dout9-17_R I/O0R - I/O17RDin_R ADDR_R OER UBR LBR R/WR CE0R CE 1R FT/PIPER CLK R Counter/ Address Reg. B W R B W R FT/PIPER Counter/ Address Reg. CNTENL ADSL REPEATL Dout9-17_L I/O0L - I/O17L A18L(1) A0L ADDR_L 5652 drw 01 512/256/128K x 18 MEMORY ARRAY CLK L ba 0a 1a 1b 0b 1a 0a ab INTERRUPT COLLISION DETECTION LOGIC INTL COLL INTR COLR R/WL R/WR CE 0 L CE1 L CE0 R CE1 R ZZ CONTROL LOGIC ZZL(2) ZZR (2) JTAG TCK TRST TMS TDO TDI A18R (1) LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3339/19/99 has been optimized for applications having unidirec- tional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70T3339/19/99 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 70T3339/19/99BC BC-256(8) 256-Pin BGA Top View(9) Pin Configuration (3,4,5,6,9) NOTES: 1. Pin is a NC for IDT70T3319 and IDT70T3399. 2. Pin is a NC for IDT70T3399. 3. All V DD pins must be connected to 2.5V power supply. 4. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is set to V SS (0V). 5. All V SS pins must be connected to ground supply. 6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 7. This package code is used to reference the package diagram. 8. This text does not indicate orientation of the actual part-marking. 9. Pins A15 and T15 will be V REFL and V REFR respectively for future HSTL device. E16 I/O7R D16 I/O8R C16 I/O8L B16 NC A16 NC A15 NC B15 NC C15 NC D15 NC E15 I/O7L E14 NC D14 NC D13 VDD C12 A6L C14 OPT L B14 VDD A14 A0L A12 A5L B12 A4L C11 ADSL D12 VDDQR D11 VDDQR C10 CLK L B11 REPEATL A11 CNTENL VDDQR NC CE 1L VDDQL LBL CE0L D10 VDDQL A7L UBL NC B13 A1L A13 A2L A10 OEL VDDQR A9L A8L A12L A10L VDDQL A14L A15L A13L VDDQL A17L(2) A18L(1) A16L PIPE/FTL NC TDO V SS NC I/O9R I/O9L NC TDI NC INTL COLL NC I/O10R I/O10L NC VDDQL I/O11L NC VDDQL NC NC I/O12L VDDQR NC I/O12R NC VDDQR I/O13L I/O14R I/O13R VDDQL NC NC I/O14L VDDQL I/O15L NC I/O15R VDDQR I/O16R I/O16L NC VDDQR NC I/O17R NC PIPE/FTR COLR I/O17L TMS A16R INTR NC TRST A18R (1) NC TCK NC A17R (2) A13R A15R P12 A6R NC LBR UBR NC P10 CLK R T11 CNTENR P11 ADSR R12 A4R T12 A5R P13 A3R A7R R13 A1R T13 A2R A 12R A14R T14 A0R R14 OPT R P14 NC P15 NC R15 NC T15 NC T16 NC R16 NC P16 I/O0L N16 NC N15 I/O0R N14 NC M16 NC M15 I/O1L M14 I/O1R L16 I/O2R L15 NC L14 I/O2L K16 I/O3L K15 NC K14 NC J16 I/O4L J15 I/O3R J14 I/O4R H16 I/O5R H15 NC H14 NC G16 NC G15 NC G14 I/O5L F16 I/O6L F14 I/O6R F15 NC CE0R R11 REPEAT R A11R CE 1R A 11L B10 R/WL C13 A3L A10R R10 R/WR A9R T10 OER A8R VDD VDD NC VSS VSS E10 VSS E11 VDD E12 VDD E13 V DDQR VDD NC VSS VSS F10 VSS F12 VDD F13 V DDQR VSS VSS VSS VSS VSS G10 VSS G11 VSS G12 VSS G13 VDDQL VSS VSS VSS VSS H10 V SS H11 VSS H12 VSS H13 VDDQL ZZR VSS VSS VSS VSS J10 VSS J11 VSS J12 ZZL J13 V DDQR VSS VSS VSS VSS VDD NC NC VSS VDD VDD NC VSS VDDQR VDDQR VDDQL VDDQL VSS K10 VSS K11 VSS K12 VSS VSS L10 V SS L11 VSS L12 VDD VSS M10 VSS M11 VDD M12 VDD VDDQR N10 VDDQR N11 VDDQL N12 VDDQL K13 V DDQR L13 V DDQL M13 V DDQL N13 VDD NC F11 VSS 5652 drw 02d I/O11R VSS

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configurations(con't)(3,4,5,6,9) 1716151412 1310987654321 11 A B C D E F G H J K L M N P R T U I/O9L INTL VSS TDO A2L A4LCLK LA8LA12LA16LNC OPT L NC VSS COLL TDI A1LA5LA9LA13LA17L(2) VDDQL I/O9R VDDQR PIPE/FTL A3L A6L NC A10LA14LA18L(1) NC NC V SS I/O10L NC NC I/O11L NC VDDQR I/O10R NC I/O11R NC VSS VDD NC I/O 12L VDD VSS NC VSS I/O12R REPEATR NC I/O 14L VDDQR VDDQL I/O15RNC VSS NCNC A15L A11L A7L A0L NC I/O7L NC I/O6L I/O8RUBL NC I/O8L VDDQL CE0L CE 1L LBL REPEATLOEL I/O0L I/O2LI/O1R ADSR R/WR NC I/O16R I/O15L TRST A13R A12R NC VDD CLK R I/O0R NC NC NC NC A17R (2)TCK TMS A5RA9R CE0R CE 1R VDD VSS NC NC NC A16R NC A18R (1) A14R A10R UBR VSS VDDQL I/O1L I/O2R NC INTR NC A 15R A11R A7R LBR OER VSS NC VDDQL OPT R NC 70T3339/19/99BF BF-208(7) 208-Pin fpBGA Top View(8) 5652 drw 02c I/O14R VDDQL VSS VDDQR NC COLR NC NC I/O7R NC R/WL NC ADSL VDDQL I/O13R CNTENL ZZR I/O13L VSS I/O16L VDDQR VSS I/O17R I/O17L VDDQL VSS PIPE/FTR A8R CNTENR A6R A3R A1R A2R A0R I/O3L I/O4L A4R VDD VSS VSS VDDQR VDDQL VSS VDDQR VSS I/O3R I/O4R VSS VDDQRVSSVDD VDD VSS I/O5R I/O5L VDDQRI/O6RVSS VSS VDDQL VDD VSS VDDQR VSS VDD VDD VSS VDD VSS NC ZZL NC VSS NOTES: 3. All V DD pins must be connected to 2.5V power supply. 4. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is set to V SS (0V). 5. All V SS pins must be connected to ground supply. 6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 7. This package code is used to reference the package diagram. 8. This text does not indicate orientation of the actual part-marking. 9. Pins B14 and R14 will be V REFL and V REFR respectively for future HSTL device. 1. Pin is a NC for IDT70T3319 and IDT70T3399. 2. Pin is a NC for IDT70T3399.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names NOTES: 1. V DD, OPT X, and V DDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPT X selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPT X is set to V SS (0V), then that port's I/Os and address controls will operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode. 5. Address A 18x is a NC for the IDT70T3319. Also, Addresses A 18x and A 17x are NC's for the IDT70T3399. 6. Chip Enables and Byte Enables are double buffered when PL/ FT = VIH, i.e., the signals take two cycles to deselect. Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input) (6) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A 18L(5) A0R - A 18R(5) Address (Input) I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock (Input) PL/FTL PL/FTR Pipeline/Flow-Through (Input) ADSL ADSR Address Strobe Enable (Input) CNTENL CNTENR Counter Enable (Input) REPEATL REPEATR Counter Repeat(3) UBL UBR Upper Byte Enable (I/O 9 - I/O17)(6) LBL LBR Lower Byte Enable (I/O 0 - I/O8)(6) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V) (1) (Input) OPTL OPTR Option for selecting V DDQX(1,2) (Input) ZZL ZZR Sleep Mode pin (4) (Input) VDD Power (2.5V)(1) (Input) VSS Ground (0V) (Input) TDI Test Data Input TDI Test Data Output TCK Test Logic Clock (10MHz) (Input) TMS T est Mode Select (Input) TRST Reset (Initialize TAP Controller) (Input) INT L INTR Interrupt Flag (Output) COLL COLR Collision Alert (Output) 5652 tbl 01

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE and ZZ are asynchronous input signals. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table I—Read/Write and Enable Control (1,2,3,4) Truth Table II—Address Counter Control (1,2) NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/ W, CE0, CE 1, UB , LB and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE 1, UB and LB. 5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE 1, UB and LB. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. OE CLK CE0 CE1 UB LB R/W ZZ Upper Byte I/O9-17 Lower Byte I/O0-8 MODE X ↑ HXXXXL H igh-Z H igh-Z D eselected– Power Down X ↑ X L X X X L High-Z High-Z Deselected–Power Down X ↑ L H H H X L High-Z High-Z Both Bytes Deselected X ↑ LH HLLL H igh-Z D IN Write to Lower Byte Only X ↑ LHLHLL D IN High-Z Write to Upper Byte Only X ↑ LHLLLL D IN DIN Write to Both Bytes L ↑ LHHLHL H igh-Z D OUT Read Lower Byte Only L ↑ LHLHHL D OUT High-Z Read Upper Byte Only L ↑ LHLLHL D OUT DOUT Read Both Bytes H ↑ L H L L X L High-Z High-Z Outputs Disabled XXXXXXXH H igh-Z H igh-Z S leep Mode 5652 tbl 02 Address Previous Internal Address Internal Address Used CLK ADS CNTEN REPEAT (6) I/O(3) MODE An X An ↑ L (4) XH D I/O (n) External Address Used XA n A n + 1 ↑ H L (5) HD I/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ HH H D I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX A n ↑ XX L (4) DI/O(n) Counter Set to last valid ADS load 5652 tbl 03

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Recommended DC Operating Conditions w ith VDDQ at 3.3V Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.4 2.5 2.6 V VDDQ I/O Supply Voltage (3) 3.15 3.3 3.45 V VSS Ground 0 0 0 V VIH Input High Voltage (Address, Control &Data I/O Inputs) (3) 2.0 ____ VDDQ + 150mV(2) V VIH Input High Voltage _ JT AG 1.7 ____ VDD + 100mV(2) V VIH Input High Voltage - ZZ, OPT , PIPE/FT VDD - 0.2V ____ VDD + 100mV(2) V VIL Input Low Voltage -0.3 (1) ____ 0.8 V VIL Input Low Voltage - ZZ, OPT , PIPE/FT -0.3(1) ____ 0.2 V 5652 tbl 05bNOTES: 1. V IL (min.) = -1.0V for pulse width less than t CYC/2, or 5ns, whichever is less. 2. V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC/2 or 5ns, whichever is less. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V DD (2.5V), and V DDQX for that port must be supplied as indicated above. Recommended DC Operating Conditions w ith VDDQ at 2.5V Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.4 2.5 2.6 V VDDQ I/O Supply Voltage (3) 2.4 2.5 2.6 V VSS Ground 0 0 0 V VIH Input High Volltage (Address, Control & Data I/O Inputs) (3) 1.7 ____ VDDQ + 100mV(2) V VIH Input High Voltage _ JT AG 1.7 ____ VDD + 100mV(2) V VIH Input High Voltage - ZZ, OPT, PIPE/FT VDD - 0.2V ____ VDD + 100mV(2) V VIL Input Low Voltage -0.3 (1) ____ 0.7 V VIL Input Low Voltage - ZZ, OPT, PIPE/FT -0.3(1) ____ 0.2 V 5652 tbl 05a NOTES: 1. V IL (min.) = -1.0V for pulse width less than t CYC/2 or 5ns, whichever is less. 2. V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC/2 or 5ns, whichever is less. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V ss(0V), and V DDQX for that port must be supplied as indicated above. Maximum Operating Temperature and Supply Voltage (1) Grade Ambient Temperature GND V DD Commercial 0 OC to +70OC0 V 2 .5V + 100mV Industrial -40 OC to +85OC0 V 2 .5V + 100mV 5652 tbl 04 NOTE: 1. This is the parameter TA. This is the "instant on" case temperature.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Absolute Maximum Ratings (1) Symbol Rating Commercial & Industrial Unit VTERM (VDD) VDD T erminal Voltage with Respect to GND -0.5 to 3.6 V VTERM(2) (VDDQ) VDDQ T erminal Voltage with Respect to GND -0.3 t o VDDQ + 0.3 V VTERM(2) (INPUTS and I/O's) Input and I/O Terminal Voltage with Respect to GND -0.3 t o VDDQ + 0.3 V TBIAS(3) T emperature Under Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC TJN Junction Temperature +150 oC IOUT(For VDDQ = 3.3V) DC Output Current 50 mA IOUT(For VDDQ = 2.5V) DC Output Current 40 mA 5652 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed V DDQ during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV) Symbol Parameter Test Conditions 70T3339/19/99S UnitMin. Max. |ILI| Input Leakage Current (1) VDDQ = Max., V IN = 0V t o VDDQ ___ 10 µA |ILI| JTAG & ZZ Input Leakage Current (1,2) VDD = Max., VIN = 0V to V DD ___ ±30 µA |ILO| Output Leakage Current (1,3) CE0 = V IH or CE 1 = V IL, VOUT = 0V to V DDQ ___ 10 µA VOL (3.3V) Output Low Voltage (1) IOL = +4mA, V DDQ = Min. ___ 0.4 V VOH (3.3V) Output High Voltage (1) IOH = -4mA, V DDQ = Min. 2.4 ___ V VOL (2.5V) Output Low Voltage (1) IOL = +2mA, V DDQ = Min. ___ 0.4 V VOH (2.5V) Output High Voltage (1) IOH = -2mA, V DDQ = Min. 2.0 ___ V 5652 tbl 08 NOTES: 2. Applicable only for TMS, TDI and TRST inputs. 3. Outputs tested in tri-state mode. Capacitance (1) (TA = +25°C, f = 1.0MHz) PQFP ONLY Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance V IN = 3dV 8 pF COUT(3) Output Capacitance V OUT = 3dV 10.5 pF 5652 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. C OUT also references C I/O.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range (3)(VDD = 2.5V ± 100mV) 70T3339/19/99 S200 Com'l Only(8) 70T3339/19/99 S166 Com'l & Ind(7) 70T3339/19/99 S133 Com'l & Ind IDD Dynamic Operating Current (Both Ports Active) CE L and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L S 375 525 320 450 260 370 mA ISB1(6) Standby Current (Both Ports - TTL Level Inputs) CE L = CER = V IH f = fMAX(1) COM'L S 205 270 175 230 140 190 mA ISB2(6) Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = V IH(5) Active Port Outputs Disabled, f=f MAX(1) COM'L S 300 375 250 325 200 250 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CE L and CER > VDDQ - 0.2V, V IN > VDDQ - 0.2V or VIN < 0.2V, f = 0 (2) COM'L S 5 15 5 15 5 15 mA ISB4(6) Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VDDQ - 0.2V (5) VIN > VDDQ - 0.2V or V IN < 0.2V Active Port, Outputs Disabled, f = f MAX(1) COM'L S 300 375 250 325 200 250 mA Izz Sleep Mode Current (Both Ports - TTL Level Inputs) ZZ L = ZZR = VIH f=fMAX(1) COM'L S 5 15 5 15 5 15 mA 5652 tbl 09NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS". 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. V DD = 2.5V, T A = 25°C for Typ, and are not production tested. I DD DC (f=0) = 15mA (Typ). 5. CEX = V IL means CE0X = V IL and CE 1X = V IH CEX = V IH means CE0X = V IH or CE 1X = V IL CEX < 0.2V means CE0X < 0.2V and CE 1X > VDDQ - 0.2V CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE 1X - 0.2V "X" represents "L" for left port or "R" for right port. 6. I SB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZ L and/or ZZ R = V IH. 7. 166MHz I-Temp is not available in the BF-208 package. 8. 200Mhz is not available in the BF-208 package.

Figure 1. AC Output Test load.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges (Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C) NOTES: 1. The Pipelined output parameters (t CYC2, t CD2) apply to either or both left and right ports when FT/PIPEX = V DD (2.5V). Flow-through parameters (t CYC1, t CD1) apply when FT/PIPE = V ss (0V) for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE), FT/PIPE and OPT. FT/PIPE and OPT should be treated as DC signals, i.e. steady state during operation. 4. 166MHz I-Temp is not available in the BF-208 package. 5. 200Mhz is not available in the BF-208 package. 6. Guaranteed by design (not production tested). 70T3339/19/99 S200 Com'l Only(5) 70T3339/19/99 S166 Com'l & Ind(4) 70T3339/19/99 S133 Com'l & Ind tCYC1 Clock Cycle Time (Flow-Through) (1) 15 ____ 20 ____ 25 ____ ns tCYC2 Clock Cycle T ime (Pipelined) (1) 5 ____ 6 ____ 7.5 ____ ns tCH1 Clock High Time (Flow-Through) (1) 6 ____ 8 ____ 10 ____ ns tCL1 Clock Low Time (Flow-Through) (1) 6 ____ 8 ____ 10 ____ ns tCH2 Clock High T ime (Pipelined) (2) 2 ____ 2.4 ____ 3 ____ ns tCL2 Clock Low T ime (Pipelined) (1) 2 ____ 2.4 ____ 3 ____ ns tOE Output Enable to Data Valid ____ 4.4 ____ 4.4 ____ 4.6 ns tOLZ(6) Output Enable to Output Low-Z 1 ____ 1 ____ 1 ____ ns tOHZ(6) Output Enable to Output High-Z 1 3.4 1 3.6 1 4.2 ns tCD1 Clock to Data Valid (Flow-Through) (1) ____ 10 ____ 12 ____ 15 ns tCD2 Clock to Data Valid (Pipelined) (1) ____ 3.4 ____ 3.6 ____ 4.2 ns tDC Data Output Hold After Clock High 1 ____ 1 ____ 1 ____ ns tCKHZ(6) Clock High to Output High-Z 1 3.4 1 3.6 1 4.2 ns tCOLR Collision Flag Reset Time ____ 3.4 ____ 3.6 ____ 4.2 ns tZZRC Sleep Mode Recovery Cycles 3 ____ 3 ____ 3 ____ cycles Port-to-Port Delay tOFS Clock-to-Clock Offset for Collision Detection Please refer to Collision Detection Timing T able on Page 20 5652 tbl 11

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(2) Timing Waveform of Read Cycle for Flow -through Output (FT/PIPE"X" = VIL)(2,6) NOTES: 1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ADS = V IL, CNTEN and REPEAT = V IH. 3. The output is disabled (High-Impedance state) by CE0 = V IH, CE 1 = V IL, UB, LB = V IH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If UB, LB was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE 1 UB,LB (3) DATA OUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 5652 drw 05 (1) (1) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (4) (1 Latency) (5) (5) An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/W ADDRESS DATA OUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 5652 drw 06 (5) (1) CE 1 UB,LB (3) tSB tHB tSW tHW tSA tHA tDC tDC (4) tSC tHC tSB tHB

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Multi-Device Pipelined Read (1,2) NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3339/19/99 for this waveform, and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = V IL; CE 1(B1), CE 1(B2), R/ W, CNTEN, and REPEAT = V IH. Timing Waveform of a Multi-Device Flow -T hrough Read(1,2) tSC tHC CE0(B1) ADDRESS (B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK Q 0 Q 1 Q 3DATA OUT(B1) tCH2 tCL2 tCYC2 ADDRESS (B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATA OUT(B2) Q 2 Q 4 tCD2 tCD2 tCKHZ tCD2 tCKLZtDC tCKHZ tCD2 tCKLZ tSC tHC tCKHZ tCKLZ tCD2 tDC tSC tHC tSC tHC 5652 drw 07 tSC tHC CE0(B1) ADDRESS (B1) A0 A1 A2 A3 A4 A5 tSA tH A CLK 5652 drw 08 D 0 D 3 tCD1 tCKLZ tCKHZ (1) (1) D 1DATA OUT(B1) tCH1 tCL1 tCYC1 (1) ADDRESS (B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATA OUT(B2) D 2 D 4 tCD1 tCD1 tCKHZ tDC tCD1 tCKLZ tSC tHC (1) tCKHZ (1) tCKLZ (1) tCD1 tDC tSC tHC tSC tHC D 5 tCD1 tCKLZ (1) tCKHZ (1)

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4) Timing Waveform w ith Port-to-Port Flow -T hrough Read(1,2,4) NOTES: 1. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to. 3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + t CYC + t CD1). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + t CD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". CLK "A" R/W"A ADDRESS "A" DATA IN"A" CLK "B" R/W"B" ADDRESS "B" DATA OUT"B" tSW tHW tSA tHA tSD tHD tSW tHW tSA tHA tCO (3) tCD2 NO MATCH VALID NO MATC H MATC H MATC H VALID 5652 drw 09tDC DATA IN "A" CLK "B" R/W "B" ADDRESS "A" R/W "A" CLK "A" ADDRESS "B" NO MATCHMATCH NO MATCHMATCH VALID tCD1 tDC DATA OUT "B" 5652 drw 10 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCO tDC tSA tSW tHA (3) NOTES: 1. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 2. OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to. 3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to val id read on opposite port will be tCO + 2 t CYC2 + t CD2). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be t CO + t CYC2 + t CD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2) Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB, LB, and ADS = V IL; CE1, CNTEN, and REPEAT = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATA IN Dn + 2 CE0 CLK 5652 drw 11 Qn Qn + 3DATA OUT CE 1 UB,LB tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (3) (1) tSW tHW WRITE (4) R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATA IN Dn + 3Dn + 2 CE0 CLK 5652 drw 12 DATA OUT Qn Qn + 4 CE 1 UB,LB OE tCH2 tCL2 tCYC2 tCKLZ tCD2 tOHZ tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (3) (1) tSW tHW (4) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB, LB, and ADS = V IL; CE1, CNTEN, and REPEAT = V IH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow -T hrough Read-to-Write-to-Read (OE = VIL)(2) Timing Waveform of Flow -T hrough Read-to-Write-to-Read (OE Controlled)(2) NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and REPEAT = V IH. 3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATA IN Dn + 2 CE0 CLK 5652 drw 13 QnDATA OUT CE 1 UB,LB tCD1 Qn + 1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tCD1 tDC tCKHZ Qn + 3 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ NOP READ tCKLZ (3) (1) tSW tHW WRITE(4) , R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5(3) DATA IN Dn + 2 CE0 CLK 5652 drw 14 QnDATA OUT CE 1 UB,LB tCD1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tDC Qn + 4 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ WRITE READ tCKLZ (1) Dn + 3 tOHZ tSW tHW OE tOE

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read w ith Address Coun ter Advance (1) ADDRESS An CLK DATA OUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3 ADS CNTEN tCYC2 tCH2 tCL2 5652 drw 15 tSA tHA tSAD tHAD tCD2 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tSAD tHAD tSCN tHCN READ WITH COUNTER Qn + 1 NOTES: 1. CE0, OE, UB, LB = V IL; CE 1, R/ W, and REPEAT = V IH. 2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH, then the data output remains constant for subsequent clocks. Timing Waveform of Flow -T hrough Read w ith Address Counter Advance (1) ADDRESS An CLK DATA OUT Qx (2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 ADS CNTEN tCYC1 tCH1 tCL1 5652 drw 16 tSA tHA tSAD tHAD READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tCD1 tDC tSAD tHAD tSCN tHCN READ WITH COUNTER

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write w ith Address Counter Advan ce (Flow -through or Pipelined Inputs)(1) Timing Waveform of Counter Repeat (2) NOTES: 1. CE0, UB, LB, and R/ W = V IL; CE 1 and REPEAT = V IH. 2. CE0, UB, LB = V IL; CE 1 = V IH. 3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II. 7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. ADDRESS An CLK DATA IN Dn Dn + 1 Dn + 1 Dn + 2 ADS CNTEN tCH2 tCL2 tCYC2 5652 drw 17 INTERNAL (3) ADDRESS An(7) An + 1 An + 2 An + 3 An + 4 Dn + 3 Dn + 4 tSA tHA tSAD tHAD WRITE COUNTER HOLD WRITE WITH COUNTERWRITE EXTERNAL ADDRESS WRITE WITH COUNTER tSD tHD tSCN tHC N ADDRESS An D 0 tCH2 tCL2 tCYC2 Q LAST Q LAST+1 LAST ADS LOAD CLK DATA IN R/W REPEAT 5652 drw 18 INTERNAL (3) ADDRESS ADS CNTEN tSRPT tHRPT tSD tHD tSW tHW EXECUTE REPEAT WRITE LAST ADS ADDRESS READ LAST ADS ADDRESS READ LAST ADS ADDRESS + 1 READ ADDRESS n Qn An + 1 An + 2 READ ADDRESS n+1 DATA OUT tSA tHA LAST ADS +1 An An + 1 (4) (5) (6) Ax tSAD tHAD tSCN tHCN

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing (2) NOTES: 1. CE0 = VIL and CE1 = VIH 2. All timing is the same for Left and Right ports. 3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals. tSW tHW 7FFFF CLK R CE R (1) ADDRESS R (3) tSA tHA 7FFFF tSC tHC tINR CLK L R/WL ADDRESS L(3) CE L(1) tSA tHA tSC tHC 5652 drw 19 INTR tINS R/WR tSW tHW Truth Table III — Interrupt Flag (1) Left Port Right Port FunctionCLKL R/WL(2) CEL(2) A18L-A0L(3,4,5) INTL CLKR R/WR(2) CER(2) A18R-A0R(3,4,5) INTR ↑ L L 7FFFF X ↑ X X X L Set Right INTR Flag ↑ XX X X ↑ H L 7FFFF H Reset Right INTR Flag ↑ XX X L ↑ L L 7FFFE X Set Left INTL Flag ↑ H L 7FFFE H ↑ X X X X Reset Left INTL Flag 5652 tbl 12 NOTES: 1. INTL and INTR must be initialized at power-up by Resetting the flags. 2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times. 3. A18 X is a NC for IDT70T3319, therefore Interrupt Addresses are 3FFFF and 3FFFE. 4. A18 X and A17 X are NC's for IDT70T3399, therefore Interrupt Addresses are 1FFFF and 1FFFE. 5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges tSA tHA (3) tCOLS tCOLR HAtSA t tCOLS tCOLR 5652 drw 20 COLR COLL (4) CLK R ADDRESS R A0 A1 A2 tOFS (4) CLK L ADDRESS L A0 A1 A2 A3 tOFS Waveform of Collision Timing (1,2) Both Ports Writing w ith Left Port Clock Leading Collision Detection Timing(3,4) Cycle Time tOFS (ns) Region 1 (ns) (1) Region 2 (ns) (2) 5ns 0 - 2.8 2.81 - 4.6 6ns 0 - 3.8 3.81 - 5.6 7.5ns 0 - 5.3 5.31 - 7.1 5652 tbl 13 NOTES: Region 1 Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc. Region 2 Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc. while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc. 3. All the production units are tested to midpoint of each region. 4. These ranges are based on characterization of a typical device. Left Port Right Port FunctionCLKL R/WL(1) CEL(1) A18L-A0L(2) COLL CLKR R/WR(1) CER(1) A18R-A0R(2) COLR ↑ HL M ATCH H ↑ HL M ATCH H Both ports reading. Not a valid collision. No flag output on either port. ↑ HL M ATCH L ↑ LL M ATCH H Left port reading, Right port writing. Valid collision, flag output on Left port. ↑ LL M ATCH H ↑ HL M ATCH L Right port reading, Left port writing. Valid collision, flag output on Right port. ↑ LL M ATCH L ↑ LL M ATCH L Both ports writing. Valid collision. Flag output on both ports. 5652 tbl 14 Truth Table IV — Collision Detection Flag NOTES: 1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times. 2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals. NOTES: 1. CE0 = VIL, CE1 = V IH. 2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases. 3. Leading Port Output flag might output 3t CYC2 + t COLS after Address match. 4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges (3) R/W DATA OUT R/W OE (4) Dn Dn+1 An+1An (5) (5) Timing Waveform - Entering Sleep Mode (1,2) Timing Waveform - Exiting Sleep Mode (1,2) NOTES: 1. CE 1 = VIH. 2. All timing is same for Left and Right ports. 3. CE0 has to be deactivated ( CE0 = V IH) three cycles prior to asserting ZZ (ZZx = V IH) and held for two cycles after asserting ZZ (ZZx = V IH). 4. CE0 has to be deactivated ( CE0 = V IH) one cycle prior to de-asserting ZZ (ZZx = V IL) and held for three cycles after de-asserting ZZ (ZZx = V IL). 5. The device must be in Read Mode (R/ W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT70T3339/19/99 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse width is independent of the cycle time. An asynchronous output enable is provided to ease asyn- chronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70T3339/19/99s for depth expansion configurations. Two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFFE when CEL = VIL and R/WL = VIH. Likewise, the right port interrupt flag ( INT R) is asserted when the left port writes to memory location 7FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFFF (3FFFF or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Collision Detection Sleep Mode The IDT70T3339/19/99 is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. Clocks must also meet cycle high and low times during these periods. Three cycles prior to asserting ZZ (ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device must be disabled via the chip enable pins. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read mode (R/Wx = VIH)when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected and will not perform any reads or writes. Collision is defined as an overlap in access between the two ports resulting in the potential for either reading or writing incorrect data to a specific address. For the specific cases: (a) Both ports reading - no data is corrupted, lost, or incorrectly output, so no collision flag is output on either port. (b) One port writing, the other port reading - the end result of the write will still be valid. However, the reading port might capture data that is in a state of transition and hence the reading port’s collision flag is output. (c) Both ports writing - there is a risk that the two ports will interfere with each other, and the data stored in memory will not be a valid write from either port (it may essentially be a random combination of the two). Therefore, the collision flag is output on both ports. Please refer to Truth Table IV for all of the above cases. The alert flag (COLX) is asserted on the 2nd or 3rd rising clock edge of the affected port following the collision, and remains low for one cycle. Please refer to Collision Detection Timing table on page 20. During that next cycle, the internal arbitration is engaged in resetting the alert flag (this avoids a specific requirement on the part of the user to reset the alert flag). If two collisions occur on subsequent clock cycles, the second collision may not generate the appropriate alert flag. A third collision will generate the alert flag as appropriate. In the event that a user initiates a burst access on both ports with the same starting address on both ports and one or both ports writing during each access (i.e., imposes a long string of collisions on contiguous clock cycles), the alert flag will be asserted and cleared every other cycle. Please refer to the Collision Detection Timing waveform on page 20. Collision detection on the IDT70T3339/19/99 represents a significant advance in functionality over current sync multi-ports, which have no such capability. In addition to this functionality the IDT70T3339/19/99 sustains the key features of bandwidth and flexibility. The collision detection function is very useful in the case of bursting data, or a string of accesses made to sequential addresses, in that it indicates a problem within the burst, giving the user the option of either repeating the burst or continuing to watch the alert flag to see whether the number of collisions increases above an acceptable threshold value. Offering this function on chip also allows users to reduce their need for arbitration circuits, typically done in CPLD’s or FPGA’s. This reduces board space and design complexity, and gives the user more flexibility in developing a solution.

various chip enables in order to expand two devices in depth. applications needing 36-bits or wider. Figure 4. Depth and Width Expansion with IDT70T3339/19/99

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Characteristics (1,2,3,4) JTAG Timing Specifications NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. TCK Device Inputs(1)/ TDI/TMS Device Outputs(2)/ TDO TRST tJCD tJDC tJRST tJS tJH tJCYC tJRSR tJF tJCL tJR tJCH 5652 drw 24 NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. 70T3339/19/99 Symbol Parameter Min. Max. Units tJCYC JT AG Clock Input Period 100 ____ ns tJCH JT AG Clock HIGH 40 ____ ns tJCL JT AG Clock Low 40 ____ ns tJR JTAG Clock Rise Time ____ 3(1) ns tJF JT AG Clock Fall Time ____ 3(1) ns tJRST JT AG Reset 50 ____ ns tJRSR JT AG Reset Recovery 50 ____ ns tJCD JTAG Data Output ____ 25 ns tJDC JTAG Data Output Hold 0 ____ ns tJS JT AG Setup 15 ____ ns tJH JT AG Hold 15 ____ ns 5652 tbl 15

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions System Interface Parameters NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. NOTE: 1. Device ID for IDT70T3319 is 0x334. Device ID for IDT70T3399 is 0x335. Instruction Field Value Description Revision Number (31:28) 0x0 Reserved for version number IDT Device ID (27:12) 0x333 (1) Defines IDT part number IDT JEDEC ID (11:1) 0x33 Allows unique identification of device v endor as IDT ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID regist er 5652 tbl 16 Scan Register Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) 32 Boundary Scan (BSR) Note (3) 5652 tbl 17 Instruction Code Description EXTEST 0000 Forces contents of the boundary scan cells onto the device outp uts(1). Places the boundary scan register (BSR) between TDI and T DO. BYPASS 1 1 1 1 Places the bypass register (BYR) between TDI and T DO. IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and T DO. HIGHZ 0100 Places the bypass register (BYR) between TDI and T DO. Forces all device output drivers to a High-Z state except COLx & INTx outputs. CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. RESERVED 0101, 0111, 1000, 1001, 1010, 1011, 1100 Several combinations are reserved. Do not use codes other t han those identified above. PRIVATE 0110,1110,1101 For internal use only. 5652 tbl 18

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTES: 1. 166MHz I-Temp is not available in the BF-208 package. 2. 200Mhz is not available in the BF-208 package. 3. Green parts available. For specific speeds, packages and powers contact your local sales office. 4. Contact your local sales office for industrial temp range for other speeds, packages and powers. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 A Power 999 Speed A Package XXXX Device Type BC BF 200 166 133 70T3339 70T3319 70T3399 S 256-pin BGA (BC-256) 208-pin fpBGA (BF-208) Standard Power Speed in Megahertz Commercial Only(2) Commercial & Industrial(1) Commercial & Industrial Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 9Mbit (512K x 18-bit) Synchronous Dual-Port RAM 4Mbit (256K x 18-bit) Synchronous Dual-Port RAM 2Mbit (128K x 18-bit) Synchronous Dual-Port RAM 5652 drw 25 A Process/ Temperature Range Tube or Tray Tape & Reel Blank Green A A Blank I(4) G (3) IDT Clock Solution for IDT70T3339/19/99 Dual-Port IDT Dual-Port Part Number Dual-Port I/O Specitications Clock Specifications IDT PLL Clock Device IDT Non-PLL Clock DeviceVoltage I/O Input Capacitance Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance 70T3339/19/99 2.5 LVTTL 8pF 40% 200 75ps 5T2010 5T9010 5T905, 5T9050 5T907, 5T9070 5652 tbl 19

6.42 IDT70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 01/20/03: Initial Datasheet 04/25/03: Page 11 Added Capacitance Derating drawing Page 12 Changed t INS and tINR specs in AC Electrical Characteristics table 11/11/03: Page 10 Updated power numbers in DC Electrical Characteristics table Page 12 Added t OFS symbol and parameter to AC Electrical Characteristics table Page 21 Updated Collision Timing waveform Page 22 Added Collision Detection Timing table and footnotes Page 26 Updated HIGHZ function in System Interface Parameters table Page 27 Added IDT Clock Solution table 04/08/04: Page 22 & 23 Clarified Sleep Mode Text and Waveforms Page 1 & 28 Removed Preliminary status Page 6 Added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode 02/07/06: Page 1 Added green availability to features Page 7 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X Page 27 Added green indicator to ordering information 07/28/08: Page 10 Corrected a typo in the DC Chars table footnotes 01/19/09: Page 28 Removed "IDT" from orderable part number 04/20/10: Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01 06/10/15: Page 3 & 4 Removed the date from all of the pin configurations BC256 & BF208 Page 26 Added T&R indicator and industrial temp footnote to Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 02/08/18: