70P5258L55BZGI

IDT70P5258ML IDT | Alldatasheet

Document overview

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Technical content

Features

– Industrial: 55ns (max.) ◆◆◆◆◆ Low-power operation – IDT70P5258ML and IDT70P525ML Active: 54mW (typ.) Standby: 7.2µW (typ.) – IDT70V525ML Active: 450mW (typ.) Standby: 250µW (typ.) Functional Block Diagram HIGH-SPEED 8K x 16 TriPort STATIC RAM R/WP1 BE0P1, BE1P1 OEP1 I/O0P1-I/O15P1 A0P1 -A 11P1 R/WP2 CEP2 OEP2 I/O0P2-I/O15P2 A0P2 -A 11P2 Memory Array PORT 1 I/O Control PORT 1 Address Decode R/WP1 OEP1 PORT 2 I/O Control PORT 3 I/O Control 5681 drw 01 R/WP3 CEP3 OEP3 I/O0P3-I/O15P3 A0P3 -A 11P3 PORT 2 Address Decode PORT 3 Address Decode Interrupt Control CEP2, CEP3 OEP2, OEP3 R/WP2, R/WP3 INTP1 - P2 INTP1 - P3 BE0P1, BE1P1 INTP3 - P1 INTP2 - P1 BE0P1, BE1P1 ◆◆◆◆◆ TriPort architecture allows simultaneous access to the memory from all three ports ◆◆◆◆◆ Fully asynchronous operation from each of the three ports: P1, P2, and P3 ◆◆◆◆◆ IDT70P5258 supports 3.0V and 1.8V I/O's ◆◆◆◆◆ Available in 144-ball 0.5mm-pitch fpBGA ◆◆◆◆◆ Industrial temperature range (–40°C to +85°C) ◆◆◆◆◆ Greeen parts available, see ordering information

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range NOTES: 1. V DDQ for 70P5258. Pin Configurations(1,2,3)

Description

The IDT70X525X is a high-speed 8K x 16 TriPort Static RAM designed to be used in systems where multiple access into a common RAM is required. This TriPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT70X525X is also designed to be used in systems where on- chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when more than one port simultaneously accesses the same TriPort RAM location. The IDT70X525X provides three independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from mutiple ports. An automatic power down feature, controlled by BE 0 and BE1 on Port 1 and CE on Port 2 and on Port 3, permits the on-chip circuitry of each port to enter a very low power standby power mode. The IDT70X525X is packaged in a 144-ball 0.5mm-pitch fpBGA. J9 J10 K9 K10 J1 J2 J3 J4 K1 K2 K3 K4 J5 J6 J7 J8 K5 K6 K7 K8 A2P1 A1P1 A0P1 A3P1A10P1I/O4P1I/O0P1I/O3P1 I/O2P1 I/O1P1 J11 J12 K11 K12 VDDVDD VssVssVss Vss VDD VssVss VDDVDDVDD C10 D10 A10 B10 E9 E10 F9 F10 G9 G10 H9 H10 C8C7 D3D2 A2A1 E1 E2 E3 E4 F1 F2 F3 F4 G1 G2 G3 G4 H1 H2 H3 H4 E5 E6 E7 E8 F5 F6 F8 G5 G6 G7 G8 H5 H6 H7 H8 5681 drw 02 12/19/03 Vss VssVss Vss Vss Vss R/WP2 OEP2VDD(1) NC VDD C12 A11 D11 C11 B11 D12 A12 B12 E11 E12 F11 F12 G11 G12 H11 H12 Vss Vss NC I/O15P2 I/O12P2 I/O11P2 I/O14P2 I/O13P2 I/O8P2 I/O4P2 I/O0P2 I/O3P2 I/O10P2 I/O7P2 I/O9P2 I/O6P2 I/O5P2 I/O2P2 I/O1P2 I/O15P3 I/O12P3 I/O11P3 I/O14P3 I/O13P3 I/O8P3 I/O4P3 I/O0P3 I/O3P3I/O10P3 I/O7P3 I/O9P3 I/O6P3 I/O5P3 I/O2P3 I/O1P3 R/WP3 OEP3 A5P2A8P2 A11P2 A6P2 A2P2 A1P2 A0P2 A3P2 A7P2A9P2 A4P2 A10P2 A5P3A8P3 A11P3 A6P3 A2P3 A1P3 A0P3 A3P3 A7P3A9P3 A4P3 A10P3CEP3 CEP2 VDD(1)VDD(1) VDD VDD Vss VssVss Vss VssVssVss VDD VDD(1)VDD VssVssVss VDDVDD A5P1A8P1A11P1 A6P1 A7P1A9P1 A4P1BE0P1 R/WP1 OEP1 I/O15P1 I/O12P1 I/O11P1 I/O14P1 I/O13P1 I/O8P1 I/O10P1 I/O7P1 I/O9P1 I/O6P1 I/O5P1 VDD L9 L10 M9 M10 L1 L2 L3 L4 M1 M2 M3 M4 L5 L6 L7 L8 M5 M6 M7 M8 L11 L12 M11 M12 BE1P1 NC INTP3P1 INTP2P1 INTP1P3 INTP1P2 VDD(1) 70(P/V)525XBZ BZ-144 Top View

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Pin Configurations(1,2) NOTES: 1. All V DD pins must be connected to the power supply. 2. All V SS pins must be connected to the ground supply. 3. IDT70P5258 only. 4. For Port 2 and Port 3. Symbol Pin Name A0P1 - A 11P1 Address Lines - Port 1 (Input) A0P2 - A 11P2 Address Lines - Port 2 (Input) A0P3 - A 11P3 Address Lines - Port 3 (Input) I/O0P1 - I/O15P1 Data I/O - Port 1 I/O0P2 - I/O15P2 Data I/O - Port 2 I/O0P3 - I/O15P3 Data I/O - Port 3 R/WP1 Read/Write - Port 1 (Input) R/WP2 Read/Write - Port 2 (Input) R/WP3 Read/Write - Port 3 (Input) CEP2 Chip Enable - Port 2 (Input) CEP3 Chip Enable - Port 3 (Input) OEP1 Output Enable - Port 1 (Input) OEP2 Output Enable - Port 2 (Input) OEP3 Output Enable - Port 3 (Input) BE0P1 Bank Enable 0 - Port 1 (Input) BE1P1 Bank Enable 1 - Port 1 (Input) INTP1 - P2 Inte rrupt P1 - P2 - Port 1 (Output) INTP1 - P3 Inte rrupt P1 - P3 - Port 1 (Output) INTP2 - P1 Inte rrupt P2 - P1 - Port 2 (Output) INTP3 - P1 Inte rrupt P3 - P1 - Port 3 (Output) VDD Power (Input) VDDQ Port Power Supply (Input) (3,4) VSS Ground (Input) 5681 tbl 01

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. Capacitance(1) (TA = +25°C, f = 1.0MHz) lobmySr etemaraPt roPs noitidnoC )2( xaMt inU CNI tupnI ecnaticapaC 1troPV NI Vd3=8 1F p 3&2troPV NI Vd3=9 F p C TUO tuptuO ecnaticapaC 1troPV TUO Vd3=0 2F p 3&2troPV TUO Vd3=1 1F p 30lbt1865 Maximum Operating Temperature and Supply Voltage(1) NOTE: 1. This is the parameter T A. This is the "instant on" case temperature. edarGe rutarepmeTtneibmAe civeDV SS VDD lairtsudnIC °58+otC°04- 525P07 8525P07 V0 V8.1 + Vm001 525V07V 0 V0.3 + Vm003 40lbt1865

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range NOTES: 1. The supply voltage for all ports on the IDT70P525 and IDT70V525 is supplied by V DD so there are no V DDQ pins on these devices. 2. V IL > -1.5V for pulse width less than 10ns. 3. V TERM must not exceed V DD + 10% for Port 1 or V DDQ + 10% for Port 2 and Port 3. Recommended DC Operating Conditions Symbol Device Port Parameter Min. Typ. Max. Unit VDD 70P5258 All Supply Voltage 1.7 1.8 1.9 V70P525 1.7 1.8 1.9 70V525 2.7 3 3.3 VDDQ 70P5258 Port 2 & 3 I/O Supp ly Vo ltag e(1) 2 . 733 . 3 VSS All All Ground 0 0 0 V VIH 70P5258 Port 1 Input Hig h Vo ltage 1.2 ____ VDD+0.2 V Port 2 & 3 2 ____ VDDQ+0.2 70P525 All 1.2 ____ VDD+0.2 70V525 All 2 ____ VDD+0.2 VIL 70P5258 Port 1 Input Lo w Voltag e -0.2 ____ 0.4 V 5681 tbl 02 Absolute Maximum Ratings(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed V DD + 10% for Port 1 or V DDQ + 10% for Port 2 and Port 3 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > VDD + 10% (Port 1) or V DDQ + 10% (Port 2 and Port 3). 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. 4. V DDQ + 0.3V for 70P5258. lobmySg nitaRl airtsudnIt inU V MRET VnoegatloVylppuS DD DNGottcepseRhtiw 9.2+ot5.0-V V MRET VnoegatloVylppuS DDQ DNGottcepseRhtiw 6.3+ot5.0-V V MRET )2( egatloVlanimreT DNGottcepseRhtiw Vot5.0- DD 3.0+ )4( V T SAIB )3( saiBrednUerutarepmeT5 21+ot55- oC T GTS erutarepmeTegarotS0 51+ot56- oC T NJ eutarepmeTnoitcnuJ0 51+ oC I TUO )525V07rof( tnerruCtuptuOCD0 5A m I TUO 525P07rof( )8525P07dna tnerruCtuptuOCD0 2A m 50lbt1865

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Temperature and Supply Voltage Range (1,4) 70P5258 70P525 Ind'l Only 70V525 Ind'l Only Symbol Parameter Test Condition Version Typ. (1) Max. Typ. (1) Max. Unit IDD Dynamic Operating Current (Both Ports Active - CMOS Level Inputs) CE = V IL, Outputs Open f = fMAX(2) IND'L L 30 50 150 180 mA ISB1 Standby Current (Both Ports - CMOS Level Inputs) CER and CEL = V IH f = fMAX(2) IND'L L .004 .016 5 10 mA ISB2 Standby Current (One Port - CMOS Level Inputs) CE"A" = V IL and CE"B" = V IH(3), Active Port Outputs Open f = fMAX(2) IND'L L 17 28 90 110 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or V IN < 0.2V f = fMAX(2) IND'L L 4 16 84 150 µA ISB4 Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDDQ - 0.2V (3) VIN > VDDQ - 0.2V or V IN < 0.2V, Active Port Outputs Open f = fMAX(2) IND'L L 17 28 90 110 mA 5681 tbl 06NOTES: 2. At f = f MAX, address and control lines are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions”. 3. For the 70P5258, if Port "A" is Port 1 then Port "B" may be either Port 2 or Port 3. If Port "A" is either Port 2 or Port 3, Port "B" must be Port 1. NOTE: 1. At V DD < 2.0V input leakages are undefined. Temperature and Supply Voltage Range(2) Symbol Device Port Parameter Test Conditions Min. Max. Unit ILI 70P5258 All Input Leakage Current VDD = 1.8V, V IN = 0V to V DD ____ 1 µA70P525 All V DD = 1.8V, V IN = 0V to V DD ____ 1 70V525 All V DD = 3.0V, V IN = 0V to V DD ____ 1 ILO 70P5258 All Output Leakage Current CEx = BEx = V IH, VOUT = 0V to V DD ____ 1 µA70P525 All CEx = BEx = V IH, VOUT = 0V to V DD ____ 1 70V525 All CEx = BEx = V IH, VOUT = 0V to V DD ____ 1 VOL 70P5258 Port 1 Output Low Voltage V Port 2 & 3 I OL = +2mA ____ 0.4 70P525 All I OL = +0.1mA ____ 0.2 70V525 All I OL = +2mA ____ 0.4 VOH 70P5258 Port 1 Output High Voltage V Port 2 & 3 I OH = -2mA 2.1 ____ 70P525 All I OH = -0.1mA 1.4 ____ 70V525 All I OH = -2mA 2.1 ____ 5681 tbl 07

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Timing Waveform of Read Cycle No. 2, Any Port(1, 2) NOTES: 1. R/ W = V IH for Read Cycles. 2. Addresses valid prior to or coincident with CE (or BEx) transition LOW. 3. CE for Port 2 or Port 3, BEx for Port 1. 4. Timing depends on which signal is asserted last, CE (or BEx) or OE. 5. Timing depends on which signal is deasserted first, CE (or BEx) or OE. Operating Temperature and Supply Voltage NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 70X525X Ind'l Only Symbol Parameter Min. Max. Unit READ CYCLE tRC Read Cycle Time 55 ____ ns tAA Address Access Time ____ 55 ns tACE Chip Enable Access Time ____ 55 ns tAOE Output Enable Access Time ____ 30 ns tOH Output Hold from Address Change 5 ____ ns tLZ Output Low-Z Time(1,2) 5 ____ ns tHZ Output High-Z Time(1,2) ____ 25 ns tPU Chip Enable to Power Up Time (2) 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 55 ns 5681 tb10 tLZ tAOE 5681 drw 08 tHZ DATAOUT CExo r BEx(3) tACE VALID DATA OE CURRENT ICC ISB tPU 50% tPD 50% (4) (5)

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Operating Temperature and Supply Voltage NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 70X525X Ind'l Only Symbol Parameter Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 55 ____ ns tEW Chip Enable to End-of-Write 45 ____ ns tAW Address Valid to End-of-Write 45 ____ ns tAS Address Set-up Time 0 ____ ns tWP Write Pulse Width (3) 40 ____ ns tWR Write Recovery Time 0 ____ ns tDW Data Valid to End-of-Write 30 ____ ns tHZ Output High-Z Time(1,2) ____ 25 ns tDH Data Hold Time 0 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 25 ns tOW Output Active from End-of-Write (1,2) 0 ____ ns 5681 tbl 11

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range 5681 drw 10 tAW tAS tWR tDW DATAIN ADDRESS tWC R/W tEW tDH (6) (2) (3) CE or BEx Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5) Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) NOTES: 1. R/ W or CE (or BEx) = V IH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a CE (or BEx) = V IL and a R/ W = V IL. 3. t WR is measured from the earlier of CE (or BEx) or R/ W = V IH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE (or BEx) LOW transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE (or BEx) or R/ W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 3). This parameter is guarant eed but is not production tested. CE or BEx 5681 drw 09 tAW tWR tDW DATAIN R/W tWP DATAOUT tWZ(7) (4) (4) (2) tOW (7)tHZtLZ (7) tHZ (3) tDH (6)tAS ADDRESS tWC

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Operating Temperature and Supply Voltage Range 70X525X Ind'l Only Symbol Parameter Min. Max. Unit INTERRUPT TIMING tAS Address Set-up T ime 0 ____ ns tWR Write Recovery Time 0 ____ ns tINS Interrupt Set Time ____ 45 ns tINR Interrupt Reset Time ____ 45 ns 5681 tbl 12 Waveform of Interrupt Timing(1) 5681 drw 12 ADDR"A" INTERRUPT SET ADDRESS CE"A" or BEx“A” R/W"A" tAS tWC tWR(3) (4) tINS (3) INT"B" (2) 5681 drw 13 ADDR"B" INTERRUPT CLEAR ADDRESS OE"B" tAS tRC (3) tINR(3) INT"B" (2) CE“B”or BEx“B” NOTES: 1. If Port A is Port 1, Port B may be either Port 2 or Port 3. If Port A is either Port 2 or Port 3, Port B must be Port 1. 2. See Interrupt Truth Table II. 3. Timing depends on which enable signal ( CE or R/ W) is asserted last. 4. Timing depends on which enable signal ( CE or R/ W) is de-asserted first.

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Functional Description The IDT70X525X provides three ports with separate control, address, and I/O pins that permit independent access for reads or writes to the two banks of memory. These devices have an automatic power down feature controlled by BE0 and BE1 on Port 1 and CE on Port 2 and Port 3. The CE (or BEX) controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE or BEX = VIH). When Port 1 is enabled, it has access to the full memory. When Port 2 is active it has access to Bank 1 of the memory. When Port 3 is active it has access to Bank 2 of the memory. See Truth Table I for a description of the Read/Write operation. Truth Table I – Read/Write Control NOTE: 1. Both BE0, and BE1 cannot be active ( BEx = V IL) simultaneously. 2. Memory Bank 0 for Port 2. Memory Bank 1 for Port 3. BE0 BE1 R/W CE OE D0-D15 Function PORT 1 HHXXXZ P o r t D e s e l e c t e d LHLXX D A T A IN Data on port written into Memory Bank 0 LHHXL D A T A OUT Data in Memory Bank 0 output on port HLLXX D A T A IN Data on port written into Memory Bank 1 HLHXL D A T A OUT Data in Memory Bank 1 output on port XXXXHZ O u t p u t s D i s a b l e d LLXXXX N o t A l l o w e d PORT 2 or PORT 3 X X X H X Z Port Deselect ed XXLLX D A T A IN Data on port written into Memory Bank (2) XXHLL D A T A OUT Data in Memory Bank (2) output on port XXXXHZ O u t p u t s D i s a b l e d HHXHXZ BE0 = BE1 = CEP3 = V IH, Sleep mode 5681 tbl 13

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range Port 1 Port 2 or 3 FunctionR/WB E 0 BE1 OE A11 - A0 INTP1 - P2 INTP1 - P3 R/WC E O E A11 - A0 INTPx - P1 L L H X FFF X X X X X X L Set P2 INT Flag XXXX X X X XLL F F F H R e s e t P 2 INT Flag L H L X FFF X X X X X X L Set P3 INT Flag XXXX X X X XLL F F F H R e s e t P 3 INT Flag XXXX X L X LLX F F E X Set P1 INTP1-P2 Flag (1) XLHL F F E H X XXX X X R e s e t P 1 INTP1-P2 Flag XXXX X X L LLX F F E X Set P1 INTP1-P3 Flag (2) XHLL F F E X H XXX X X R e s e t P 1 INTP1-P3 Flag 5681 tbl 14 Truth Table II - Interrupt Flag NOTE: 1. Port 2 sets the INTP1 - P2 flag on Port 1 so all signals refer to Port 2. 2. Port 3 sets the INTP1 - P3 flag on Port 1 so all signals refer to Port 3. Interrupts If the user chooses the interrupt function, a memory location (mailbox or message center) is assigned to each port. Interrupt P1 - P2 of Port 1 (INTP1 - P2) is asserted when Port 2 writes to memory location FFE(HEX), where a write is defined as CE = R/W = VIL per Truth Table II. Port 1 clears the interrupt by accessing address location FFE when BE0 = VIL, R/W is a "don't care". Interrupt P1 - P3 of Port 1 (INTP1 - P3) is asserted when Port 3 writes to memory location FFE (HEX), where a write is defined as CE= R/W = VIL. Port 1 clears the interrupt by accessing address location FFE when BE1 = VIL, R/W is a "don't care". Port 2's interrupt flag (INTP2 - P1) is asserted when Port 1 writes to memory location FFF (HEX), where a write is defined as BE0 = R/W = VIL. Port 2 clears the interrupt by accessing address location FFF when CE = VIL, R/W is a "don't care". Likewise, Port 3's interrupt flag (INTP3 - P1) is asserted when Port 1 writes to memory location FFF (HEX), where a write is defined as BE1= R/W = VIL. Port 3 clears the interrupt by accessing address location FFF when CE= VIL, R/ W is a "don't care".

6.42 IDT70X525XML Preliminary Low Power 4K x 8 TriPort Static RAM Industrial Temperature Range

Ordering Information

A Power 999 Speed A Package A Process/ Temperature Range BZ 144-Ball Ball Grid Array (BZ144-1) Speed in nanoseconds Low Power 128K (8K x 16) TriPort RAM Industrial Only55 XXXX Device Type 5681 drw 14 L 70P5258 70P525 70V525 A Industrial (-40°Ct o+ 8 5°C)I G(1) Green The IDT logo is a registered trademark of Integrated Device Technology, Inc. Datasheet Document History 10/14/03: Initial datasheet 03/23/04: Page 7 Corrected tOH spec min to 5ns in AC Electrical CharacteristicsTable 10 5/26/05: Page 1 Added green availability to features Page 13 Added green indicator to ordering information Page 1 & 13 Replaced old logo ® with new TM logo 05/08/06: Page 5 Updated VTERM in Absolute Maximum Ratings table and added footnote 3 & 4 07/25/08: Page 6 Corrected a typo in the DC Chars table 01/19/09: Page 14 Removed "IDT" from orderable part number CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com NOTE: 1. Green parts available. For specific speeds, packages and powers contact your sales office.