70P257L55BYGI

IDT70P257_09 IDT | Alldatasheet

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Technical content

Features

◆◆◆◆◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location – Industrial: 55ns (max.) ◆◆◆◆◆ Low-power operation IDT70P257/247L Active: 27mW (typ.) Standby: 3.6µW (typ.) ◆◆◆◆◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆◆◆◆◆ IDT70P257/247 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆◆◆◆◆ M/S = VDD for BUSY output flag on Master M/S = VSS for BUSY input on Slave ◆◆◆◆◆ Input Read Register ◆◆◆◆◆ Output Drive Register ◆◆◆◆◆ BUSY and Interrupt Flag ◆◆◆◆◆ On-chip port arbitration logic ◆◆◆◆◆ Full on-chip hardware support of semaphore signaling between ports ◆◆◆◆◆ Fully asynchronous operation from either port ◆◆◆◆◆ LVTTL-compatible, single 1.8V (±100mV) power supply ◆◆◆◆◆ Available in 100 Ball 0.5mm-pitch BGA ◆◆◆◆◆ Industrial temperature range (-40°C to +85°C) ◆◆◆◆◆ Green parts available, see ordering information Functional Block Diagram NOTES: 1. A 12X is a NC for IDT70P247. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull.

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range

Description

The IDT70P257/247 is a very low power 8K/4K x 16 Dual-Port Static RAM. The IDT70P257/247 is designed to be used as a stand-alone 128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual- Port SRAM for 32-bit-or-more word systems. Using the IDT MASTER/ SLAVE Dual-Port SRAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 27mW of power. The IDT70P257/247 is packaged in a 100 ball 0.5mm- pitch Ball Grid Array. The package is a 1mm thick and designed to fit in wireless handset applications. Pin Configurations(2,3,4) C10 D10 A8 A10 D3D2 A2A1 E1 E2 E3 E4 F1 F2 F3 F4 G1 G2 G3 G4 H1 H2 H3 H4 J1 J2 J3 J4 K1 K2 K3 K4 B10 E5 E6 E7 E8 E9 E10 F5 F6 F8 F9 F10 G5 G6 G7 G8 G9 G10 H5 H6 H7 H8 H9 H10 J5 J6 J7 J8 J9 J10 K5 K6 K7 K8 K9 K10 5684 drw 02b 02/04/04 A5R A8R A11R UBR Vss VssSEMR I/O15R I/O12R I/O10R Vss VssA6R I/O7RI/O11RI/O14RA2RA1RA0R LBR Vss Vss SFEN Vss Vss VDDA3R A7R A9R CER R/WR OER I/O9R I/O6RA4R VDD VDD A12R(1)A10RINTR I/O13R I/O5RBUSYR I/O2RODR2ODR4 I/O8R M/S ODR3 INTL IRR1 I/O4R I/O1R ODR1 BUSYL A1L NC NC OEL I/O0RI/O3R I/O15L VDD ODR0 A2L A5L A12L(1) VDD I/O3L I/O11L I/O12L I/O14L I/O13L A0L A4L A9L LBL CEL I/O1L VDD I/O10L A3L A7L A10L IRR0 I/O4L I/O6L I/O8L I/O9L A6L A8L A11L UBL SEML R/WL I/O0L I/O2L I/O5L I/O7L Vss 70P257/247BY BY-100 100-Ball 0.5mm Pitch BGA Top View(5) NOTES: 1. A 12X is a NC for IDT70P247. 2. All V DD pins must be connected to power supply. 3. All V SS pins must be connected to ground supply. 4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Pin Names Left Port Right Port Names CEL CER Chip Enable (Input) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A 12L(1) A0R - A 12R(1) Address (Input) I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable (Input) UBL UBR Upper Byte Select (Input) LBL LBR Lower Byte Select (Input) INTL INTR Interrupt Flag (Output) BUSYL BUSYR Busy Flag IRR0, IRR1 Input Read Register (Input) ODR0 - ODR4 Output Drive Register (Output) SFEN(2) Special Function Enable (Input) M/S Master or Slave Select (Input) VDD Power (1.8V) (Inp ut) VSS Ground (0V) (Input) 5684 tbl 01 NOTE: 1. A 12X is a NC for IDT70P247. 2. SFEN is active when either CEL = V IL or CER = V IL. SFEN is inactive when CEL = CER = V IH. NOTE: 1. A 0L — A 12L ≠ A 0R — A 12R for IDT70P257; A 0L — A 11L ≠ A 0R — A 11R for IDT70P247. Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs ModeCE R/W OE UB LB SEM I/O8-15 I/O0-7 H X X X X H High-Z High-Z Deselected: Power Down X X X H H H High-Z High-Z Both Bytes Deselected LLXLH H D A T A IN High-Z Writ e to Upper Byte Only LLXHLH H i g h - Z D A T A IN Write to Lower Byte Only LLXLLH D A T A IN DATAIN Write to Both Bytes LHLLH H D A T A OUT High-Z Read Upper Byte Only LHLHLH H i g h - Z D A T A OUT Read Lower Byte Only LHLLLH D A T A OUT DAT AOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 5684 tbl 02

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Truth Table II: Semaphore Read/Write Control(1) NOTE: 1. There are eight semaphore flags written to via I/O 0 and read from all of the I/O's (I/O 0-I/O15). These eight semaphores are addressed by A 0-A2. Inputs Outputs ModeCE R/W OE UB LB SEM I/O8-15 I/O0-7 HHLXXL D A T A OUT DATAOUT Read Data in Semaphore Flag XHLHHL D A T A OUT DATAOUT Read Data in Semaphore Flag H ↑ XXXL D A T A IN DATAIN Write DIN0 into Semaphore Flag X ↑ XHHL D A T A IN DATAIN Write DIN0 into Semaphore Flag 5684 tbl 03 Absolute Maximum Ratings(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed V DD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period over V TERM = V DD + 0.3V . 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. Symbol Rating Industrial Unit VTERM Supply Voltage on V DD with Respect to GND -0.5 to +2.9 V VTERM(2) Terminal Voltage with Respect to GND -0.5 to V DD +0.3 V TBIAS(3) Temperature Under Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC TJN Junction T emperature +150 oC IOUT DC Output Current 20 mA 5684 tbl 04

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Capacitance (TA = +25°C, f = 1.0MHz) NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance V IN = 3dV 9 pF COUT Output Capacitance V OUT = 3dV 1 1 pF 5684 tbl 07 Maximum Operating Temperature and Supply Voltage(1) NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. Grade Ambient Temperature GND V DD Industrial -40 OC to +85 OC0 V 1 . 8 V + 100mV 5684 tbl 05 Recommended DC Operating Conditions NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed V DD + 0.3V. 3. M/ S operates at the V DD and V SS voltage levels. Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage(3) 1.7 1.8 1.9 V VSS Ground 0 0 0 V VIH Input High Voltage 1.2 ___ VDD + 0.2 V VIL Input Low Voltage -0.2 ___ 0.4 V 5684 tbl 06

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VDD = 1.8V, V IN = 0V to VDD ___ 1 µA ILO Output Leakage Current CE = V IH, V OUT = 0V to VDD ___ 1 µA VOL Output Low Voltage IOL = +0.1mA ___ 0.2 V VOH Output High Voltage IOH = -0.1mA VDD - 0.2V ___ V 5684 tbl 08 Temperature and Supply Voltage Range(1) (VDD = 1.8V ±100mV) NOTES: 1. V DD = 1.8V, T A = +25°C, and are not production tested. I DD DC = 15mA ( typ.) 2. At f = f MAX, address and control lines are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions”. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. If M/ S = V SS, then f BUSYL = f BUSYR = 0 for full standby mode. 70P257/247 Ind'l Only Symbol Parameter Test Condition Version Typ. (1) Max. Unit IDD Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Open f = fMAX(2) IND'L L 15 25 mA ISB1 Standby Current (Both Ports - TTL Leve l Inp uts) CER and CEL = V IH, SEM = VIH f = fMAX(2) IND'L L 2 8 µA ISB2 Standby Current (One Port - TTL Leve l Inp uts) CE"A" = V IL and CE"B" = V IH(4), Active Port Outputs Open f = fMAX(2) IND'L L 8.5 14 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDD - 0.2V, SEML and SEMR > VDD - 0.2V, V IN > VDD - 0.2V or V IN < 0.2V f = fMAX(2), M/S = V DD or VSS(4) I N D ' LL 28 µA ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDD - 0.2V (4) VIN > VDD - 0.2V or V IN < 0.2V, Active Port Outputs Open f = fMAX(2) IND'L L 8.5 14 mA 5684 tbl 09

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Operating Temperature and Supply Voltage Range(4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = V IL, UB or LB = V IL, and SEM = V IH. To access semaphore, CE = V IH or UB and LB = V IH, and SEM = V IL. 4. The specification for t DH must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH and t OW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW. 5. At any given temperature and voltage condition, t HZ is less than t LZ for any given device. 70P257/247 Ind'l Only UnitSymbol Parameter Min. Max. READ CYCLE tRC Read Cycle Time 55 ____ ns tAA Address Access Time ____ 55 ns tACE Chip Enable Access Time (3) ____ 55 ns tABE Byte Enable Access Time (3) ____ 55 ns tAOE Output Enable Access Time (3) ____ 30 ns tOH Output Hold from Address Change 5 ____ ns tLZ Output Low-Z Time(1,2,5) 5 ____ ns tHZ Output High-Z Time(1,2,5) ____ 25 ns tPU Chip Enable to Power Up Time (1,2) 0 ____ ns tPD Chip Disable to Power Down Time (1,2) ____ 55 ns tSOP Semaphore Flag Updat e Pulse ( OE or SEM)1 5 ____ ns tSAA Semaphore Address Access (3) ____ 55 ns 5684 tbl 11

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range tRC R/W CE ADDR tAA OE UB, LB 5684 drw 05 (4) tACE (4) tAOE (4) tABE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. t BDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last t ABE, tAOE, tACE, tAA or tBDD. 5. SEM = V IH.

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access SRAM, CE = V IL, UB or LB = V IL, SEM = V IH. To access semaphore, CE = V IH or UB and LB = V IH and SEM = V IL. Either condition must be valid for the entire t EW time. 4. The specification for t DH must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH and t OW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW. Operating Temperature and Supply Voltage(4) Symbol Parameter 70P257/247 Ind'l Only UnitMin. Max. WRITE CYCLE t WC Write Cycle Time 55 ____ ns tEW Chip Enable to End-of-Write (3) 45 ____ ns tAW Address Valid to End-of-Write 45 ____ ns tAS Address Set-up Time (3) 0 ____ ns tWP Write Pulse Width 40 ____ ns tWR Write Recovery Time 0 ____ ns tDW Data Valid to End-of -Write 30 ____ ns tHZ Output High-Z Time(1,2) ____ 25 ns tDH Data Hold Time(4) 0 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 25 ns tOW Output Active from End-of-Write (1,2,4) 0 ____ ns tSWRD SEM Flag Writ e t o Read Time 10 ____ ns tSPS SEM Flag Contention Window 10 ____ ns 5684 tb l 12

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) NOTES: 1. R/ W or CE or UB & LB must be high during all address transitions. 2. A write occurs during the overlap (t EW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/ W going HIGH (or SEM going LOW) to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the high-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output Test Load. 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. 9. To access SRAM, CE = V IL, UB or LB = V IL, SEM = V IH. To access semaphore, CE = V IH or UB and LB = V IH and SEM = V IL. Either condition must be valid for the entire tEW time. R/W tWC tHZ tAW tWRtAS tWP DATAOUT (2) tWZ tDW tDH tOW OE ADDRESS DATAIN (6) (4) (4) (7) 5684 drw 06 CE or SEM (7) (3) CE or SEM (9) (9) (9) ADDRESS tAW CE or SEM tWC 5684 drw 07 tAS tWR tDW tDH DATAIN R/W tEW UB or LB (9) (3)(2)(6) Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Timing Waveform of Semaphore Read after Write Timing, Either Side(1) Timing Waveform of Semaphore Write Contention(1,3,4) NOTES: 1. D 0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH. 2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/ W "A" or SEM"A" going HIGH to R/ W"B" or SEM"B" going HIGH. 4. If t SPS is not satisfied there is no guarantee which side will be granted the semaphore flag. NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. “DATA OUT VALID” represents all I/O's (I/O0-I/O15)equal to the semaphore value. SEM"A" 5684 drw 09 tSPS MATCH R/W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/W"B" A0"B"-A2"B" SIDE (2) "B" SEM tEW 5684 drw 08 tAW I/O0 VALID ADDRESS tSAA R/W tWR tO H tACE VALID ADDRESS DATAIN VALID tDW tWP tDHtAS tSWRD tAOE Read CycleWrite Cycle A0-A2 OE DATAOUT VALID(2) tSOP

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Operating Temperature and Supply Voltage Range NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = V DD)" or "Timing Waveform of Write With Port-To-Port Delay (M/ S = V SS)". 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 70P257/247 Ind'l Only Symbol Parameter Min. Max. Unit BUSY TIMING (M/ S = V DD) tBAA BUSY Access Time from Address Match ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 45 ns tBAC BUSY Access T ime f rom C hip En a ble L OW ____ 45 ns tBDC BUSY Disable Time from Chip Enable HIGH ____ 45 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ ns tBDD BUSY Disable to Valid Dat a(3) ____ 40 ns tWH Write Hold After BUSY(5) 35 ____ ns BUSY TIMING (M/ S = V SS) tWB BUSY Input to Write (4) 0 ____ ns tWH Write Hold After BUSY(5) 35 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 80 ns tDDD Write Data Valid to Read Data Delay (1) ____ 65 ns 5684 tb l 13

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Timing Waveform of Slave Write (M/S = VIL) 5684 drw 11 R/W"A" BUSY"B" tWP tWB(3) R/W"B" tWH(1) (2) NOTES: 1. t WH must be met for both BUSY input (slave) and output (master). 2. Busy is asserted on port "B" blocking R/ W"B", until BUSY"B" goes HIGH. 3. t WB is only for the “slave” version. 5684 drw 10 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD(3) tWDD tBAA Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) NOTES: 1. To ensure that the earlier of the two ports wins. t APS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/ S = V SS (slave), BUSY is an input. Then for this example BUSY"A" = V IH and BUSY"B" input is shown above. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 5684 drw 12 ADDR"A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 5684 drw 13 ADDR"A" ADDRESS "N" ADDR"B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" Operating Temperature and Supply Voltage Range 70P257/247 Ind'l Only Symbol Parameter Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ ns tWR Write Recovery Time 0 ____ ns tINS Interrupt Set Time ____ 45 ns tINR Interrupt Reset Time ____ 45 ns 5684 tb l 14

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Waveform of Interrupt Timing(1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal ( CE or R/W) is asserted last. 4. Timing depends on which enable signal ( CE or R/W) is de-asserted first. 5684 drw 14 ADDR"A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR(3) (4) tINS(3) INT"B" (2) 5684 drw 15 ADDR"B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR(3) INT"B" (2)

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Truth Table III — Interrupt Flag (1) NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = V IL, then no change. 4. A 12X is a NC for IDT70P247, therefore Interrrupt Addresses are FFF and FFE. Left Port Right Port FunctionR/WL CEL OEL A12L-A0L(4) INTL R/WR CER OER A12R-A0R(4) INTR LLX 1 F F F XXXX X L (2) Se t Right INTR Flag X X XXX X L L 1 F F F H (3) Reset Right INTR Flag XXX X L (3) L L X 1FFE X Se t Left INTL Flag X L L 1FFE H (2) X X X X X Re set Le ft INTL Flag 5684 tbl 15 Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70P257/247 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V IH if the inputs to the opposite port became stable after the address and enable inputs of this port. If t APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A 0L — A 11L and A 0R — A 11R for IDT70P247. Inputs Outputs FunctionCEL CER A0L-A12L(4) A0R-A12R BUSYL(1) BUSYR(1) X X NO MATCH H H Normal HX M A T C H H H N o r m a l XH M A T C H H H N o r m a l L L MATCH (2) (2) Write Inhibit (3) 5684 tbl 16

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P257/247. 2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2. 3. CE = V IH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functions D 0 - D15 Left D 0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 5684 tbl 17 SFEN CE R/W OE UB LB ADDR I/O 0-I/O1 I/O2-I/O15 Mode HLHL L (1) L(1) x0000 - Max VALID (1) VALID(1) Standard Memory Access LLHL X L x 0 0 0 0 V A L I D (2) X IRR Read (3) 5684 tbl 18 Truth Table VI — Input Read Register Operation(3) NOTES: 1. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID. 2. LB must be active ( LB = V IL) for these bits to be valid. 3. SFEN = V IL to activate IRR reads. SFEN CE R/W OE UB LB ADDR I/O 0-I/O4 I/O5-I/O15 Mode HLH X (1) L(2) L(2) x0000 - Max VALID (2) VALID(2) Standard Memory Access L L L X X L x0001 VALID (3) X ODR Write (4,5) L L H L X L x0001 VALID (3) X ODR Read (5) 5684 tbl 19 Truth Table VII — Output Drive Register Operation(5) NOTES: 1. Output enable must be low (OE = Vil) during reads for valid data to be output. 2. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID. 3. LB must be active ( LB = V IL) for these bits to be valid. 4. During ODR writes data will also be written to the memory. 5. SFEN = V IL to activate ODR reads and writes.

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P257/247 SRAMs. the resulting array requires the use of an external AND gate. a slave (M/S pin = VSS) as shown in Figure 3. address signals only. It ignores whether an access is a read or write. write inhibit signal and corrupted data in the slave. and address x0000 is not available for standard memory operations. interrupt flag (INTR), the right port must read the memory location 1FFF. signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. prevented to a port by tying the BUSY pin for that port LOW.

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range The Output Drive Register (ODR) of the IDT70P257/247 determines the state of up to five external binary-state devices by providing a path to VSS for the external circuit. The five external devices supported by the ODR can operate at different voltages (1.5V < VSUPPLY < 3.5V), but the combined current of the devices must not exceed 40 mA (8mA IMAX for each external device). The status of the ODR bits is set using standard write accesses from either port to address x0001with a “1” corresponding to “on“ and a “0” corresponding to “off”. The status of the ODR bits can also be read (without changing the status of the bits) via a standard read to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for standard memory operations. When SFEN = VIH, the ODR is inactive and address x0001 can be used as part of the main memory. During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 - I/O15 are "Don't Care". Refer to Figure 4 and Truth Table VII for Output Drive Register operation. Semaphores The IDT70P257/247 is an extremely fast Dual-Port 8K/4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be accessed to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non- semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are LOW. Systems which can best use the IDT70P257/247 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70P257/247's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70P257/247 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active HIGH. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70P257/247 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A 0 – A 2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the Output Drive Register

fully to that location and will assume control over the resource in question. be read from that semaphore on the right side during subsequent read. made to one port or the other. are misused or misinterpreted, a software error can easily happen. to be dedicated at any one time to servicing either the left or right port. indicator for the upper section of memory.

1. If it succeeded in gaining control, it would lock out the left side.

4K/2K blocks of Dual-Port SRAM with each other. during a transfer and the I/O device cannot tolerate any wait states. ously without any wait states. assigned SRAM segments at full speed. teeing a consistent data structure.

0 D Q

Figure 4. IDT70P257/247 Semaphore Logic

6.42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range

Ordering Information

A Power 999 Speed A Package A Process/ Temperature Range I Industrial (-40°Ct o+ 8 5°C) BY 100 Ball 0.5mm-pitch BGA(BY100) L Low Power XXXXX Device Type 128K (8K x 16) 1.8V Dual-Port SRAM 64K (4K x 16) 1.8V Dual-Port SRAM 70P257 70P247 Speed in nanosecondsIndustrial Only A G(1) Green CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. Datasheet Document History 02/04/04: Initial Datasheet 03/22/05: Page 1 Added green availability to features Page 23 Added green indicator to ordering information Page 1 & 23 Replaced old IDT TM with new IDT TM logo Removed Preliminary status 05/08/06: Page 4 Updated VTERM in Absolute Maximum Ratings table 01/19/09: Page 23 Removed "IDT" from orderable part number NOTE: 1. Green parts available. For specific speeds, packages and powers contact your local sales office.