70P2352-IGT

78P2352 TERIDIAN | Alldatasheet

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Page: 1 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 SEPTEMBER 2006

DESCRIPTION

The 78P2352 is Teridian’s second generation Line Interface Unit (LIU) for 155 Mbps SDH/SONET (OC-3, STS-3, or STM-1) and 140 Mbps PDH (E4) telecom interfaces. The device is a dual channel, single chip solution that includes an integrated CDR in the transmit path for flexible NRZ to CMI conversion. The device can interface to 75Ω coaxial cable using CMI coding or directly to a fiber optics transceiver module using NRZ coding. The 78P2352 is compliant with all respective ANSI, ITU- T, and Telcordia standards for jitter tolerance, generation, and transfer.

APPLICATIONS

• Central Office Interconnects
• DSLAMs
• Add Drop Multiplexers (ADMs)
• Multi Service Switches
• Digital Microwave Radios

FEATURES

• ITU-T G.703 compliant cable driver for 139.264 Mbps or 155.52 Mbps CMI-coded coax transmission
• Integrated adaptive CMI equalizer and CDR in receive path handles over 12.7dB of cable loss
• Serial, LVPECL system interface with integrated CRU in transmit path for flexible NRZ to CMI conversion.
• 4-bit parallel CMOS system interface with master and slave Tx clock modes.
• Selectable LVPECL com patible NRZ media interface for 155.52 Mbps optical transmission.
• Configurable via HW control pins or 4-wire serial port interface
• Compliant with ANSI T1.105.03-1994; ITU-T Telcordia GR-253-CORE for jitter performance.
• Receiver Loss of Signal (LOS) detection compatible with ITU-T G.783
• Operates from a single 3.3V supply
• Standard and thermally enhanced 128-pin JEDEC LQFP package options BLOCK DIAGRAM Rx CDRCMI Decoder RXxP/N SOxDP/N SOxCKP/N POx[3:0]D POxCK PTOxCK PIx[3:0]D PIxCK SIxCKP/N SIxDP/N FIFOTx CDR Lock Detect EACH CHANNEL: Rx CMI Encoder ECLxP/N CMIxP/N TXxCKP/N Lock Detect EACH CHANNEL: Tx Adaptive Eq. LOS Detect PMOD, SMOD[1:0], PAR LLBK RLBK CMI

Page: 2 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4

Page: 3 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 TABLE OF CONTENTS (continued)

Page: 4 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 FUNCTIONAL DESCRIPTION The 78P2352 contains all the necessary transmit and receive circuitry for connection between 139.264Mbps and 155.52Mbps line interfaces and the digital universe. The chip is controllable through pins or serial port register settings. In hardware mode (pin control) the SPSL pin must be low. In software mode (SPSL pin high), control pins are disabled and the 78P2352 must be configured via the 4-wire serial port. MODE SELECTION The SDO_E4 pin or E4 register bit determines which rate the device (both channels) operates in according to the table below. This control, combined with CKSL, also selects the global reference clock frequency. Rate SDO_E4 pin E4 bit E4 High 1 STM-1, STS-3, OC-3 Low 0 The SEN_CMI pin or CMI register bit enables the CMI encoder/decoder and selects one of two media for reception and transmission: 75 Ω coaxial cable in CMI mode or optical fiber in Fiber (NRZ) mode. Independent channel operation for media type is available with register controls only. Media (coding) SEN_CMI pin CMI bit 75Ω Coax (CMI) High 1 Fiber (NRZ) Low 0 The SDI_PAR pin or PAR register bit selects the interface to the framer to be 4-bit parallel CMOS or serial LVPECL. For each interface there are different transmit timing modes available. See TRANSMITTER OPERATION section for more info. REFERENCE CLOCK The 78P2352 requires a reference clock supplied to the CKREFP/N pins. This reference clock is used for clock recovery in the Rx DLL and Tx DLL. It is also used for transmit re-timing in the synchronous transmit modes. Refer to the TRANSMITTER OPERATION section for timing requirements during synchronous (re-timing) transmit modes. For reference frequencies of 77.76MHz or lower, the device accepts a single ended CMOS input at CKREFP (with CKREFN grounded). For reference frequencies of 139.264 or 155.52MHz, the device accepts a differential LVPECL clock input at CKREFP/N. The frequency of this reference input is controlled by the rate selection and the CKSL control pin or register bit. Reference Frequency CKSL pin SDO_E4 low SDO_E4 high Low 19.44MHz 17.408MHz Float 77.76MHz N/A High 155.52MHz 139.264MHz CKSL[1:0] bits E4 bit = 0 E4 bit = 1 0 0 19.44MHz 17.408MHz 1 0 77.76MHz N/A 1 1 155.52MHz 139.264MHz RECEIVER OPERATION The receiver accepts seri al data, at 155.52Mbps or 139.264Mbps from the RXxP/N inputs. In CMI mode, the input is differentially terminated with 75 Ω and transformer-coupled to a coaxial connector. In Fiber (NRZ) mode, the input is differentially terminated with 100Ω and AC-coupled to an optical transceiver module. For board designs utilizing both coax and fiber media options, an analog switch or mechanical relay is required to switch between the different terminations and media paths. The CMI signal first enters an AGC and adaptive equalizer designed to overcome inter-symbol interference caused by long cable lengths. The variable gain differential amplifier automatically controls the gain to maintain a constant voltage level output regardless of the input voltage level. Note that in Fiber (NRZ) mode, the input signals bypass the adaptive equalizer. The outputs of the data comparators are connected to the clock recovery circuits. The clock recovery system employs a Delay Locked Loop (DLL), which uses a reference frequency derived from the clock applied to the CKREFP/N pins. In serial mode, the clock and data are decoded and transmitted through the LVPECL drivers. In parallel mode, the data is decoded and converted into four bit parallel segments before being transmitted through the CMOS drivers. Note that in Fiber (NRZ) mode, the CMI decoder is bypassed. Receiver Monitor Mode In CMI mode, the SCK_MON pin or MONx register bit enables the receiver’s monitor mode which adds approximately 20dB of flat gain to the receive signal before equalization. Rx Monitor Mode can handle 20dB of flat loss typical of monitoring points with up to 6dB of cable loss. Note that Loss of Signal detection is disabled during Rx Monitor Mode.

Page: 8 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 In SW mode only, a Full Remote (digital) Loopback bit FLBK is also available in the Advanced Tx Control register. This lo opback exercises the entire Rx and Tx paths of the 78P2352 including the Tx clock recovery unit. As such, the user must enable either Serial Plesiochronous or Serial Loop-timing transmit modes to utilize the Full Remote (digital) Loopback. Rx CDRCMI Decoder RXxP/N SOxDP/N SOxCKP/N POx[3:0]D POxCK PTOxCK PIx[3:0]D PIxCK SIxCKP/N SIxDP/N FIFOTx CDR Lock Detect EACH CHANNEL: Rx CMI Encoder ECLxP/N CMIxP/N TXxCKP/N Lock Detect EACH CHANNEL: Tx Adaptive Eq. LOS Detect PMOD, SMOD[1:0], PAR LLBK RLBK CMI Figure 8: Remote (Digital) Loopback INTERNAL POWER-ON RESET Power-On Reset (POR) function is provided on chip. Roughly 50µs after Vcc reaches 2.4V at power up, a reset pulse is internally generated. This resets all registers to their default values as well as all state machines within the tran sceiver to known initial values. The reset signal is also brought out to the PORB pin. The PORB pin is a special function analog pin that allows for the following:

• Override the internal POR signal by driving in an external active low reset signal;
• Use the internally generated POR signal to trigger other resets;
• Add external capacitor to slow down the release of power-on reset (approximately 8 µs per nF added). NOTE: Do not pull-up the PORB pin to Vcc or drive this pin high during power-up. This will prevent the internal reset generator from resetting the entire chip and may result in errors. SERIAL CONTROL INTERFACE The serial port controlled registers allows a generic controller to interface with the 78P2352. It is used for mode settings, diagnostics and test, retrieval of status and performance information, and for on-chip fuse trimming during prod uction test. The SPSL pin must be high in order to use the serial port. The serial interface consists of four pins: Serial Port Enable (SEN_CMI), Serial Clock (SCK_MON), Serial Data In (SDI_PAR), and Serial Data Out (SDO_E4). The SEN_CMI pin initiates the read and write operations. It can also be used to select a particular device allowing SCK_MON, SDI_PAR and SDO_E4 to be bussed together. SCK_MON is the clock input that times the data on SDI_PAR and SDO_E4. Data on SDI_PAR is latched in on the rising-edge of SCK_MON, and data on SDO_E4 is clocked out using the falling edge of SCK_MON. SDI_PAR is used to insert mode, address, and register data into the chip. Address and Data information are input leas t significant bit (LSB) first. The mode and address bit assignment and register table are shown in the following section. SDO_E4 is a tri-state capable output. It is used to output register data du ring a read operation. SDO_E4 output is normally high impedance, and is enabled only during the duration when register data is being clocked out. Read data is clocked out least significant bit (LSB) first. If SDI_PAR coming out of the micro-controller chip is also tri-state capable, SDI_PAR and SDO_E4 can be connected together to simplify connections. The maximum clock frequency for register access is 20MHz. PROGRAMMABLE INTERRUPTS In addition to the receiver LOS and LOL status pins, the 78P2352 provides a programmable interrupt for each transmitter. In HW control mode, the default events that trigger the Tx interrupt is a transmit Loss of Lock (TXLOL) or FIFO error (FERR).

Page: 9 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION REGISTER ADDRESSING Address Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Address Sub-Address Read/ Write Assignment PA[3] PA[2] PA[1] PA[ 0] SA[2] SA[1] SA[0] R/W* REGISTER TABLE a) PA[3:0] = 0 : Global Registers Sub Addr Reg. Name Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 MSCR

(R/W) Master Control E4 <0> <0> PAR <0> CKSL[1] <X> CKSL[0] <X> <X> <X> SRST <0>

1 INTC

(R/W) Interrupt Control INPOL <0> <0> <1> <0> <0> <X> MTLOL <1> MFERR <1> 2 -- (R/W) Reserved -- <X> <X> <X> <X> <X> <X> <X> <0> b) PA[3:0] = 1, 2 : Port-Specific Registers Sub Addr Reg. Name Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 MDCR

(R/W) Mode Control PDTX <0> PDRX <0> PMODE <X> SMOD[1] <X> SMOD[0] <X> MON <0> <0> <1>

1 SGCR

(R/W) Signal Control TCMIINV <0> RCMIINV <0> LOLOR <0> RLBK <0> LLBK <0> RCLKP <0> TCLKP <0> FRST <0>

2 ACR1

(R/W) Advanced Tx Control 1 <0> <0> <0> <0> <0> <0> TPK <0> TXEQ <0>

3 ACR0

(R/W) Advanced Tx Control 0 <1> <0> <1> <0> <1> BST[1] <0> BST[0] <0> FLBK <0>

4 MCR2

(R/W) Mode Control 2 CMI <1> <X> <X> <0> <0> <0> <0> <0>

5 STAT

(R/C) Status Monitor -- <X> <X> <X> RXLOS <X> RXLOL <X> <X> TXLOL <X> FERR <X>

Page: 10 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (CONTINUED) LEGEND TYPE DESCRIPTION TYPE DESCRIPTION R/O Read only R/W Read or Write R/C Read and Clear GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION

7 E4 R/W 0

Line Rate Selection: Selects the line rate of all channels as well as the input clock frequency at the CKREFP/N pins. 0: OC-3, STS-3, STM-1 (155.52MHz) 1: E4 (139.264MHz) 6 -- R/W 0 Unused

5 PAR R/W 0

Serial/Parallel Interface Selection: Selects the interface to the framer. 0: Serial LVPECL 1: 4-bit Parallel CMOS 4:3 CKSL [1:0] R/W XX Reference Clock Frequency Selection: Selects the reference clock frequency input at CKREFP/N pins. 11: 155.52MHz / 139.264MHz (differential LVPECL) 10: 77.76MHz / NA (single-ended CMOS) 00: 19.44MHz / 17.408MHz (single-ended CMOS) Secondary values correspond to E4 frequencies. Default values depend on the CKSL pin selection upon reset. 2:1 -- R/W X0 Reserved.

0 SRST R/W 0

Register Soft-Reset: When this bit is set, all registers are reset to their default values. This register bit is self-clearing.

Page: 11 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (CONTINUED) ADDRESS 0-1: INTERRUPT CONTROL REGISTER This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as required. BIT NAME TYPE DFLT VALUE DESCRIPTION

7 INPOL R/W 0

Interrupt Pin Polarity Selection: 0 : Interrupt output is active-low (default) 1 : Interrupt output is active-high 6:2 -- R/W 01000 Reserved for future use

1 MTLOL R/W 1

TXLOL Error Mask (active low): Gates the TXLOL register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass

0 MFERR R/W 1

FIERR Error Mask (active low): Gates the respective FIERR register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass ADDRESS 0-2: RESERVED BIT NAME TYPE DFLT VALUE DESCRIPTION 7:0 -- R/W XXXXXXX0 Reserved.

Page: 12 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (CONTINUED) PORT-SPECIFIC REGISTERS For PA[3:0] = 1-2 = N only. Accessing a register with port address greater than 2 constitutes an invalid command, and the read/write operation will be ignored. ADDRESS N-0: MODE CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION

7 PDTX R/W 0

Transmitter Power-Down: 0 : Normal Operation 1 : Power-Down. CMI Transmit output is tri-stated.

6 PDRX R/W 0

Receiver Power-Down: 0 : Normal Operation 1 : Power-Down

5 PMODE R/W X

Parallel Mode Interface Selection: When PAR=0, PMODE is invalid and defaults to logic ‘1’; When PAR=1 , (Master Control Register: bit 5), PMODE selects the source of the transmit parallel clock, either taken from the framer externally or generated internally. Default value is determined by CKMODE pin setting upon power up or reset. 0: Slave Timing. PIxCK clock input to the transmitter 1: Master Timing. PTOxCK clock output from the transmitter

4 SMOD[1] R/W X

3 SMOD[0] R/W X

Serial Mode Interface Selection: When PAR=0 (Master Control Register: bit 5), SMOD[1:0] configures the transmitter’s system interface. Default values determined by CKMODE pin setting upon power up or reset. SMOD[1] SMOD[0] 0 0 Synchronous clock and data are passed through a FIFO. The CDR is bypassed. 1 0 Synchronous data is passed through the CDR and then through the FIFO. 0 1 Plesiochronous data is passed through the CDR to recover a clock. FIFO is bypassed because the data is not synchronous with the reference clock. 1 1 Loop Timing Mode Enable: The recovered receive clock is used as the reference for the transmit DLL and FIFO. When PAR=1 (Master Control Regsiter: bit 5), setting SMOD[1:0] = 11 will enable Loop Timing Mode. Default values are determined by CKMODE pin setting upon power up or reset as follows: CKMODE Low Æ SMOD[1:0] default = 00 (no effect) CKMODE Float Æ SMOD[1:0] default = 11 (loop-timing enable) CKMODE High Æ SMOD[1:0] default = 01 (no effect)

2 MON R/W 0

Receive Monitor Mode Enable: 0: Normal Operation 1: Adds 20dB of flat gain to the receive signal before equalization NOTE : Monitor mode is only available in CMI mode. 1:0 -- R/W 00 Reserved

Page: 13 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (CONTINUED) ADDRESS N-1: SIGNAL CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION

7 TCMIINV R/W 0

Transmit CMI Inversion: This bit will flip the polarity of the transmit CMI data outputs at CMIxP/N. For debug use only. 0: Normal 1: Invert

6 RCMIINV R/W 0

Receive CMI Inversion: This bit will flip the polarity of the receive CMI data inputs at RXxP/N. For debug use only. 0: Normal 1: Invert

5 LOLOR R/W 0

Receive Loss of Lock/Signal Override: When high, the RXLOL and RXLOS signals will always remain low. 0: Normal 1: Forces LOS and LOL outputs to be low and resets counters NOTE : For reliable operation of the Rx LOL detection circuitry, one must manually reset the LOL counter by toggling this bit upon power-up or initialization.

4 RLBK R/W 0

3 LLBK R/W 0

Analog Loopback Selection: RLBK LLBK 0 0 Normal operation 1 0 Remote Loopback Enable: Recovered receive data is looped back to the transmit driver for retransmission. 0 1 Local Loopback Enable : The transmit data is looped back and used as the input to the receiver.

2 RCLKP R/W 0

Receive Clock Inversion Select: This bit will invert the receive output clock. 0: Normal. Data clocked out on falling edge of receive clock. 1: Invert. Data clocked out on the rising edge of receive clock.

1 TCLKP R/W 0

Transmit Clock Inversion Select: This bit will invert the transmit input system clock. 0: Normal. Data is clocked in on rising edge of the transmit clock. 1: Invert. Data is clocked in on the falling edge of the transmit clock.

0 FRST R/W 0

FIFO Reset: 0: Normal operation 1: Reset FIFO pointers to default locations. This reset should be initiated anytime the transmitter or IC powers up to ensure the FIFO is centered after internal VCO clocks and external transmit clocks are stable. *Not required for Plesiochronous Serial Mode

Page: 14 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (CONTINUED) ADDRESS N-2: ADVANCED TRANSMIT CONTROL REGISTER 1 BIT NAME TYPE DFLT VALUE DESCRIPTION 7:1 -- R/W 0000000 Reserved.

0 TXEQ R/W 0

Transmit Fixed Equalizer Enable: When enabled, compensates for between 0.75m and 1.5m of FR4 trace to the serial LVPECL data inputs SIxDP/N 0: Normal Operation 1: Enable equalizer ADDRESS N-3: ADVANCED TRANSMIT CONTROL REGISTER 0 BIT NAME TYPE DFLT VALUE DESCRIPTION 7:3 -- R/W 10101 Reserved. 2:1 BST[1:0] R/W 00 Transmit Driver Amplitude Boost: Adds roughly 5% or 10% of boost to the CMI output. Limits not tested during production test. 00 : Normal amplitude 01 : 5% boost 10 : Reserved 11 : 10% boost

0 FLBK R/W 0

Full Remote (digital) Loopback Enable: When enabled the recovered receive data is decoded and looped back to the transmit clock recovery unit exercising the entire receive and transmit paths. NOTE: Must be used in conjunction with Serial Plesiochronous Mode or Serial Loop-Timing Mode. ADDRESS N-4: MODE CONTROL REGISTER 2 BIT NAME TYPE DFLT VALUE DESCRIPTION

7 CMI R/W 1

Line Interface Mode Selection: 0: Optical fiber (LVPECL, NRZ). CMI ENDEC and line driver are disabled. Use RXxP/N and ECLxP/N pins for line interface. 1: Coaxial cable (CMI encoded). CMI ENDEC enabled. Optical (NRZ) interface disabled. Use RXxP/N and CMIxP/N pins for line interface. 6:0 -- R/W XX00000 Reserved.

Page: 15 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 REGISTER DESCRIPTION (continued) ADDRESS N-5: STATUS MONITOR REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION 7:5 -- R/C XXX Reserved.

4 RXLOS R/C X

Receive Loss of Signal Indication: 0: Normal operation 1: Loss of signal condition detected

3 RXLOL R/C X

Receive Loss of Lock Indication: This status bit is only defined during a valid input signal at RxP/N or when RXLOS=0 0: Normal operation 1: Recovered receive clock frequency differs from the reference by more than +/- 100ppm. 2 -- R/C X Unused

1 TXLOL R/C X

Transmit Loss of Lock Indication: This status bit is only defined and valid when using one of the serial transmit modes utilizing the Tx CDR. 0: Valid transmit input signal detected at SIxDP/N 1: No valid signal detected at SIxDP/N

0 FERR R/C X

Transmit FIFO Error Indication: This bit is set whenever the internal FERR signal is asserted, indicating that the FIFO is operating at its dept h limit. It is reset to 0 when the FRST pin is asserted. 0: Normal operation 1: Transmit FIFO phase error ADDRESS N-6, N-7: RESERVED BIT NAME TYPE DFLT VALUE DESCRIPTION 7:0 RSVD R/O 0 Reserved for test.

Page: 16 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 PIN DESCRIPTION LEGEND TYPE DESCRIPTION TYPE DESCRIPTION A Analog Pin (Tie unused pins to ground) PO LVPECL-Compatible Differential Output (Tie unused pins to supply or leave floating) CIT 3-State CMOS Digital Input CO CMOS Digital Output (Leave unused pins floating) CI CMOS Digital Input (Tie unused pins to ground) COZ CMOS Tristate Digital Output (Leave unused pins floating) CIU CMOS Digital Input w/ Pull-up OD Open-drain Digital Output (Leave unused pins floating) CID CMOS Digital Input w/ Pull-down S Supply CIS CMOS Schmitt Trigger Input (Tie unused pins to ground) G Ground PI LVPECL-Compatible Differential Input (Tie unused pins to ground) TRANSMITTER PINS NAME PIN TYPE DESCRIPTION PIx0D PIx1D PIx2D PIx3D 31, 66 32, 65 33, 64 34, 63 CI Transmit (Parallel Mode) Data Input: Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge (default) of the transmit parallel clock and serialized with the MSB (PIx3D) transmitted first. PIxCK 30, 67 CIS Transmit (Parallel Mode) Clock Input: A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be source synchronous with the reference clock supplied at the CKREFP/N pins. Used only in Slave Parallel Mode and Loop-timing Parallel Mode. PTOxCK 35, 62 CO Transmit (Parallel Mode) Clock Output: A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is intended to latch in synchronous parallel data. Active during reset. Used only in Master Parallel Mode (output disabled in all other transmit modes). SIxDP SIxDN 10, 87 11, 86 PI Transmit (Serial Mode) Data Input: Differential NRZ data input. See Transmitter Operation section for more info on different clocking/timing modes. SIxCKP SIxCKN 7, 90 8, 89 PI Transmit (Serial Mode) Clock Input: A 155.52MHz synchronous differential input clock used to clock in the serial NRZ data. By default, data is clocked in on the rising edge of SIxCKP. CMIxP CMIxN 121, 104 122, 103 A Transmit (Serial Mode) CMI Data Output: A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse templates when properly terminated and transformer coupled to 75Ω cable. Outputs are tri-stated when transmitter is disabled. Active, but undefined during reset. TXxCKP TXxCKN 124, 101 125, 100 PO Transmit (Serial Mode) Clock Output: A 2x line rate LVPECL clock output used to clock out the transmit CMI data. Used for diagnostics or far end re-timing. Active during reset. ECLxP ECLxN 127, 98 128, 97 PO Transmit (Serial Mode) LVPECL Data Output: Transmit NRZ data outputs used for interfacing with optical transceiver modules when in Fiber (NRZ) mode.

Page: 17 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 PIN DESCRIPTION (CONTINUED) RECEIVER PINS NAME PIN TYPE DESCRIPTION POx0D POx1D POx2D POx3D 46, 51 45, 52 42, 55 41, 56 CO Receive (Parallel Mode) Data Output: Recovered receive data deserialized into four-bit CMOS parallel (nibble) outputs. The MSB (POx3D) is received first. Active, but undefined during reset. Note: During Loss of Signal conditions, data outputs are held low. POxCK 38, 59 CO Receive (Parallel Mode) Clock Output: A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by dividing down the recovered receive clock. By default, receive data is clocked out on the falling edge. Active during reset. Note: During Loss of Signal conditions, the clock will remain on the last divided down phase selection of the Rx DLL and output a steady clock. SOxDP SOxDN 28, 69 29, 68 PO Receive (Serial Mode) Data Output: Recovered receive serial NRZ data at LVPECL levels. Active, but undefined during reset. Note: During Loss of Signal conditions, data outputs are held at logic 0. SOxCKP SOxCKN 25, 72 26, 71 PO Receive (Serial Mode) Clock Output: Recovered receive serial clock. By default, recovered serial NRZ data is clocked out the falling edge of SOxCKP. Active during reset. Note: During Loss of Signal conditions, the clock will remain on the last phase selection of the Rx DLL and output a steady clock. RXxP RXxN 118, 107 119, 106 PI Receiver CMI or LVPECL Input: The input is either transformer-coupled to coaxial cable for CMI data or AC- coupled at LVPECL levels to an optical transceiver module for NRZ data.

Page: 18 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 PIN DESCRIPTION (CONTINUED) REFERENCE AND STATUS PINS Note: The LOSx, LOLx, and INTxXxB pins are configurabl e at final test (default open-drain outputs). If CMOS level outputs are required, please refer to alternate 70Pxxxx ordering numbers at the end of the data sheet. NAME PIN TYPE DESCRIPTION CKREFP CKREFN 111 110 PI/ CI Reference Clock Input: A required reference clock input used for clock/data recovery and frequency synthesizer. Options include :

• 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock input at CKREFP/N
• 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) single- ended CMOS clock input at CKREFP. Tie CKREFN to ground when unused. LOS1 LOS2 OD/ CO Receive Loss of Signal (active-high): See Receiver Loss of Signal description for conditions. LOL1 LOL2 OD/ CO Receive Loss of Lock (active-high): This condition is met when the recovered clock frequency differs from the reference clock frequency by more than +/- 100ppm. INTTX1B INTTX2B OD/ CO Transmitter Fault Interrupt Flag (active low): When a transmitter error event occurs (as defined in the Interrupt Control Register Description), the INTTXxB pin will change state to indicate an interrupt. The interrupt is cleared by a read to the STAT Register, an issue of a FRSTx FIFO reset pulse (if the FIERRx signal caused the interrupt), or when the TXLOL register bit transitions from high to low. Note: The default interrupt condition is a loss of lock in the transmitter CDR. INTRX1B INTRX2B OD/ CO Receiver Fault Interrupt Flag (active low): Reserved for future use. PORB 83 A Power-On Reset (active low): See Power-On Reset description on use of this pin.

Page: 19 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 PIN DESCRIPTION (CONTINUED) CONTROL PINS NAME PIN TYPE DESCRIPTION FRST 78 CIT FIFO Phase-Initialization Control: When asserted, the transmit FIFO pointers are reset to the respective “centered” states. Also resets the FIERR interrupt bit. De-assertion edge of FRSTx will resume FIFO operation.

• Low: Channel 1 FRST assertion
• Float: Normal operation
• High: Channel 2 FRST assertion Because the internal VCO clock and off-chip transmit clocks may not be stable during transmit power-up, it is recommended to always reset the FIFOs after powering up the IC or the transmitter. Not valid during Plesiochronous Serial Mode. LPBKx 17, 18 CIT Analog Loopback Selection:
• Low: Normal operation
• Float: Remote Loopback Enable: Recovered receive data and clock are looped back to the transmitter for retransmission.
• High: Local Loopback Enable: The serial transmit data is looped back and used as the input to the receiver. CKMODE 15 CIT Clock Mode Selection: Selects the method of inputting transmit data into the chip. See TRANSMITTER OPERATION section for more information. In PARALLEL mode (SDI_PAR high):
• Low: Parallel transmit clock is input to the 78P2352.
• Float: Parallel transmit clock is input to the 78P2352. Loop-timing mode enabled.
• High: Parallel transmit clock is output from the 78P2352 In SERIAL mode (SDI_PAR low):
• Low: Reference clock is synchronous to transmit clock and data. Data is clocked in with SIxCKP/N and passed through a FIFO
• Float: Reference clock is synchronous to transmit data. Clock is recovered with a CDR and data is passed through a FIFO
• High: Reference clock is plesiochronous to transmit data. Clock is recovered with a CDR and the FIFO is bypassed

Page: 20 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 PIN DESCRIPTION (CONTINUED) CONTROL PINS (continued) NAME PIN TYPE DESCRIPTION TXOUT1 1 CIT Advanced Tx Control 1: Low: Enables fixed LVPECL equalizer at the transmit inputs SIDP/N for FR4 trace lengths up to 1.5m. Float: Normal operation High: Normal operation TXOUT0 2 CIT Advanced Tx Control 0: Low: Nominal amplitude Float: 5% amplitude boost High: 10% amplitude boost TXPD 14 CID Transmitter Power Down: When high, powers down and tr-states the transmitt driver on both channels. SPSL 77 CID Serial Port Selection: When high, chip is software controlled through the serial port. CKSL 81 CIT Reference Clock Frequency Selection: Selects the reference frequency that is supplied at the CKREFP/N pins. Its level is read in only at power-up or on the rising edge of a reset signal at the PORB pin.

• Low : 19.44MHz or 17.408MHz
• Float: 77.76MHz
• High: 155.52MHz or 139.264MHz

Page: 21 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 PIN DESCRIPTION (CONTINUED) SERIAL-PORT PINS NAME PIN TYPE DESCRIPTION SEN_CMI 95 CIU [SPSL=1] Serial-Port Enable: High during read and write operations. Low disables the serial port. While SEN is low, SDO remains in high impedance state, and SDI and SCK activities are ignored. [SPSL=0] Medium Select: Low: Fiber (NRZ pass-through) mode High: CMI mode SCK_MON 96 CIS [SPSL=1] Serial Clock: Controls the timing of SDI and SDO. [SPSL=0] Receive Monitor Mode Enable: When high, adds 20dB of flat gain to the incoming signal of both channels before equalization. NOTE: Channel specific monitor modes can be enabled through the serial port. Rx Monitor Mode is only available in CMI mode SDI_PAR 94 CI [SPSL=1] Serial Data Input: Inputs mode and address information. Also inputs register data during a Write operation. Both address and data are input least significant bit first. [SPSL=0] Data Width Select: Selects 4 bit parallel transmit modes (input high) or serial transmit modes (input low) SDO_E4 93 COZ/ CI [SPSL=1] Serial Data Output: Outputs register information during a Read operation. Data is output least significant bit first [SPSL=0] Rate Select: Selects E4 operation (input high) or STM1/STS3 operation (input low) POWER AND GROUND PINS It is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. See application note for decoupling guidelines. NAME PIN TYPE DESCRIPTION VCC 5, 12, 21, 74, 85, 92, 99, 105, 109, 116, 120, 126 S Power Supply VDD 23, 37, 40, 44, 48, 49, 53, 57, 60 S CMOS I/O Driver Supply GND 108, 112, 113, 114, 115, 117, 123 G Ground VSS 24, 36, 39, 43, 47, 50, 54, 58, 61 G CMOS I/O Driver Ground TGND 82 G Trim Ground Used during production test. Connect directly to ground. Do not decouple to supply or PORB.

Page: 22 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER RATING Supply Voltage (Vdd) -0.5 to 4.0 VDC Storage Temperature -65 to 150 °C Junction Temperature -40 to 150 °C Pin Voltage (CMIxP,CMIxN) Vdd + 1.5 VDC Pin Voltage (all other pins) -0.3 to (Vdd+0.6) VDC Pin Current ±100 mA RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. PARAMETER RATING DC Voltage Supply (Vdd) 3.15 to 3.45 VDC Ambient Operating Temperature -40 to 85 °C Junction Temperature -40 to 125 °C DC CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Total Supply Current (CMI) (including transmitter current through transformer) Idd STM-1 mode; CMI mode; Max. cable length 325 350 mA Total Supply Current (NRZ) Idde STM-1 mode; Fiber (NRZ) mode 290 310 mA Receive-only Supply Current Iddr Transmitter disabled; STM-1 mode; CMI mode; Max. cable length 190 205 mA Supply Current per Port (CMI) (including transmitter current through transformer) Iddx STM-1 mode; CMI mode; Max. cable length 160 180 mA Power down Current Iddq PDTX = 1, PDRX = 1 7 10 mA

Page: 23 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) ANALOG PINS CHARACTERISTICS: The following table is provided for informative purpose only. Not tested in production. PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT RXxP and RXxN Common-Mode Bias Voltage Vblin Ground Reference 1.9 2.1 2.6 V RXxP and RXxN Differential Input Impedance Rilin 20 kΩ Analog Input/Output Capacitance Cin 8 pF PORB Input Impedance -- 5 kΩ DIGITAL I/O CHARACTERISTICS: Pins of type CI, CIU, CID: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Type CI, CID only 0.8 Input Voltage Low Vil Type CIU only 0.4 V Input Voltage High Vih 2.0 V Input Current Iil, Iih -1 0 1 µA Pull-up Resistance Rpu Type CIU only 53 70 113 kΩ Pull-down Resistance Rpd Type CID only 40 58 120 kΩ Input Capacitance Cin 8 pF Pins of type CIT: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Input Voltage Low Vtil 0.4 V Input Voltage High Vtih Vcc-0.6 V Minimum impedance to be considered as “float” state Rtiz 30 kΩ Pins of type CIS: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Low-to-High Threshold Vt+ 1.3 1.7 V High-to-Low Threshold Vt- 0.8 1.2 V Input Current Iil, Iih -1 1 µA Input Capacitance Cin 8 pF

Page: 24 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) Pins of type CO and COZ: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Output Voltage Low Vol Iol = 8mA 0.4 V Output Voltage High Voh Ioh = -8mA 2.4 V Output Transition Time Tt C L = 20pF, 10-90% 2 ns Effective Source Impedance Rscr 30 Ω Tri-state Output Leakage Current Iz Type COZ only -1 1 µA Pins of type PO: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT 0.5 0.8 1.1 Signal Swing Vpk TXxCKP/N pins 0.35 0.95 V Common Mode Level Vcm Vdd referenced -1.55 -1.2 -1.1 V Effective Source Impedance Reff 20 Ω Rise Time Tr 10-90% 0.8 1.2 ns Fall Time Tf 10-90% 0.8 1.2 ns Pins of type PI: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Signal Swing Vpki 0.3 V Common Mode Level Vcm Vdd referenced -1.6 -1.2 -0.8 V Pins of type OD: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Output Voltage Low Vol Iol = 8mA 0.4 V Pull-down Leakage Current Ipd Logic high output 1 µA Pull-up Resistor Rpu 4.7 10 kΩ

Page: 25 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) SERIAL-PORT TIMING CHARACTERISTICS: PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT SDI to SCK setup time tsu 4 ns SDI to SCK hold time th 4 ns SCK to SDO propagation delay tprop 10 ns SCK Frequency SCK 20 MHz

1 SA0 SA1 SA2 PA0 PA1 PA2 PA3

Z CS SCK SDI SDO tsu th X X or Z tsu th D0 D1 D2 D3 D4 D5 D6 D7 Z tprop Figure 9: Read Operation Figure 10: Write Operation

0 SA0 SA1 SA2 PA0 PA1 PA2 PA3 D0 D1 D2 D3 D4 D5 D6 D7

Z CS SCK SDI SDO tsu th X X tsu th

Page: 26 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER TIMING CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Clock Duty Cycle TTCF/TTC PTOxCK 40 60 % Setup Time TPS Parallel mode 4 ns Hold Time TPH Parallel mode 4 ns Setup Time TSS Serial mode 2 ns Hold Time TSH Serial mode 2 ns TIMING DIAGRAM: Transmitter Waveforms TSHTSS SIxCKN SIxCKP SIxDP SIxDN PIxCK PIxD<0:3> TPHTPS PTOxCK PIxD<0:3> TPHTPS TTCTTRC = 25.72ns TRCF = 12.86ns

Page: 27 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) REFERENCE CLOCK CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT CKREF Duty Cycle -- 40 60 % Synchronous mode; E4 -15 +15 Synchronous mode; STM1 -20 +20 CKREF Frequency Stability -- Plesiochronous or Loop-timing mode. (see Note 1) -75 +75 ppm Note 1: In Plesiochronous mode, the transmit clock/data source (i.e. framer/system reference clock) must still be of +/-20ppm quality (+/-15ppm for E4) in order to meet the ITU-T (or Telcordia) bit rate requirements. RECEIVER TIMING CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT RCLK Duty Cycle TRCF/TRC 40 60 % RSCQ Serial mode 0 1 Clock to Q RPCQ Parallel mode -1 2 ns TIMING DIAGRAM: Receive Waveforms TRC = 6.43ns TRCF = 3.215ns RSCQ SOxCKN SOxCKP SOxDP SOxDN TRCT POxCK POxD<0:3> TRC = 25.72ns TRCF = 12.86ns RPCQ TRCT

Page: 28 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE Bit Rate: 139.264Mbps ± 15ppm or 155.52Mbps ± 20ppm Code: Coded Mark Inversion (CMI) Relevant Specification: ITU-T G.703, Telcordia GR-253, ANSI T1.102 With the coaxial output port driving a 75 Ω load, the output pulses conform to the templates in Figures 11, 12, 13, and 14. These specifications are tested during prod uction test. Consult application note for reference schematic, layout guidelines, and recommended transformers. PARAMETER CONDITION MIN NOM MAX UNIT Peak-to-peak Output Voltage (Fuse-trimmed to nominal target at final test) Template, steady state 0.9 1.05 1.1 V Rise/ Fall Time 10-90% 2 ns Negative Transitions -0.1 0.1 Positive Transitions at Interval Boundaries -0.5 0.5 Transition Timing Tolerance Positive Transitions at mid- interval -0.35 0.35 ns Transmit clock frequency stability (PIxCK or SIxCKP/N ) With respect to CKREF 0 0 ppm The following specifications are not tested during production test. They are included for information only. PARAMETER CONDITION MIN NOM MAX UNIT Output Impedance Driver is open drain 1 MΩ pF Return Loss 7MHz to 240MHz 15 dB

Page: 29 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) (Note 1) (Note 1) (Note 1) 0.60 0.55 0.50 0.45 0.40 0.05 -0.05 -0.50 -0.55 -0.60 -0.45 -0.40 (Note 1) 0.35ns Nominal Zero Level (Note 2) T = 7.18ns 0.1ns 0.1ns 1ns 1.795 ns 1.795 ns 1.795 ns 1.795 ns 1ns 1ns 1ns 0.1ns 0.1ns 1ns 1ns Nominal Pulse 0.35ns V Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. T he nominal zero level for both masks should be aligned with the oscilloscope trace wit h no input signal. With the signal then applied, the vert ical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limit s of the relevant mask, irrespective of the state of the pre ceding or succeeding pulses, with both pulse masks fixed in the same relati on to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersym bol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. W hen using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress t he effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the meas ured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Figure 11 – Mask of a Pulse corresponding to a binary Zero in E4 mode

Page: 30 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) (Note 1) (Note 1) 0.60 0.55 0.50 0.45 0.40 0.05 -0.05 -0.50 -0.55 -0.60 -0.45 -0.40 (Note 1) Nominal Zero Level (Note 2) T = 7.18ns 0.1ns 0.1ns 1ns 1.795 ns 1ns Nominal Pulse V 3.59ns 1.35ns 1.35ns 3.59ns 1.795 ns 1ns 1ns 0.5ns 0.5ns Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. T he nominal zero level for both masks should be aligned with the oscilloscope trace wit h no input signal. With the signal then applied, the vert ical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limit s of the relevant mask, irrespective of the state of the pre ceding or succeeding pulses, with both pulse masks fixed in the same relati on to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersym bol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. W hen using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress t he effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the meas ured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are ± 0.1ns and ±0.5ns respectively. Figure 12 – Mask of a Pulse corresponding to a binary One in E4 mode.

Page: 31 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) (Note 1) (Note 1) (Note 1) 0.60 0.55 0.50 0.45 0.40 0.05 -0.05 -0.50 -0.55 -0.60 -0.45 -0.40 (Note 1) 0.35ns Nominal Zero Level (Note 2) T = 6.43ns 0.1ns 0.1ns 1ns 1.608ns 1.608ns 1.608ns 1.608ns 1ns 1ns 1ns 0.1ns 0.1ns 1ns 1ns Nominal Pulse 0.35ns V Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. T he nominal zero level for both masks should be aligned with the oscilloscope trace wit h no input signal. With the signal then applied, the vert ical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limit s of the relevant mask, irrespective of the state of the pre ceding or succeeding pulses, with both pulse masks fixed in the same relati on to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersym bol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. W hen using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress t he effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the meas ured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Figure 13 – Mask of a Pulse corresponding to a binary Zero in STS-3/STM-1 mode.

Page: 32 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) (Note 1) (Note 1) 0.60 0.55 0.50 0.45 0.40 0.05 -0.05 -0.50 -0.55 -0.60 -0.45 -0.40 (Note 1) Nominal Zero Level (Note 2) 6.43ns 0.1ns 0.1ns 1ns 1.608ns 1ns Nominal Pulse V 3.215ns 1.2ns 1.2ns 3.215ns 1.608ns 1ns 1ns 0.5ns 0.5ns Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. T he nominal zero level for both masks should be aligned with the oscilloscope trace wit h no input signal. With the signal then applied, the vert ical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limit s of the relevant mask, irrespective of the state of the pre ceding or succeeding pulses, with both pulse masks fixed in the same relati on to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersym bol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. W hen using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress t he effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the meas ured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are ± 0.1ns and ±0.5ns respectively. Figure 14 – Mask of a Pulse corresponding to a binary One in STS-3/STM-1 mode

Page: 33 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER OUTPUT JITTER 1993 and T1.105.03-1994; and GR-253-CORE for all supported rates. Transmit output jitter is not tested during production test. PARAMETER CONDITION MIN NOM MAX UNIT CMI Mode; 200 Hz to 3.5 MHz, measured with respect to CKREF for 60s

0.075 UIpp

NRZ (optical) Mode; 12 kHz to 1.3 MHz, measured with respect to CKREF

0.01 UIrms

Page: 34 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled) Consult application note for reference schematic, layout guidelines, and recommended transformers. PARAMETER CONDITION MIN TYP MAX UNIT Peak Differential Input Amplitude, RXxP and RXxN CMI mode; MON=0; 12.7dB of cable loss 70 550 mVpk Peak Differential Input Amplitude, RXxP and RXxN CMI mode; MON=1; 20dB flat loss w/ 6dB of cable loss 25 80 mVpk Flat-loss Tolerance CMI mode; MON=0; All valid cable lengths. -2 6 dB Receive Clock Jitter STM-1 mode; CMI mode; 12.7 dB cable loss a) Normal receive mode b) Remote loopback mode 0.1 0.07 UIpp UIpp Latency 5 10 UI PLL Lock Time 1 10 µs Return Loss 7MHz to 240MHz 15 dB The input signal is assumed compliant with ITU-T G.703 and can be attenuated by th e dispersive loss of a cable. The minimum cable loss is 0dB and the maximum is –12.7dB at 78MHz. The “Worst Case” line corresponds to the ITU-T G.703 recommendation. The “Typical” line corresponds to a typical installation referred to in ANSI T1.102-1993. T he receiver is tested using the cable model. It is a lumped element approximation of the “Worst Case” line. Frequency (Hz) Attenuation (dB) Worst Case Typical Figure 15: Typical and worst-case Cable attenuation

Page: 35 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TOLERANCE The 78P2352 exceeds all relevant jitter tolerance specif ications shown in Figures 16, 17. STS-3/OC-3 jitter tolerance specifications are in ANSI T1.105.03-19 94 and Telcordia GR-253-CORE. STM-1 (optical) jitter tolerance specifications are in ITU-T G.813, G.825, and G.958. STM-1e (electrical) jitter tolerance specifications are in ITU-T G.825. E4 specifications are found in ITU-T G.8 23. Receive jitter tolerance is not tested during production test. 0.01 0.1 100 1.E+00 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Electrical (CMI) Interfaces G.825 - STM-1e Tolerance (for 2048 kbps networks) G.825 - STM-1e Tolerance (for 1544 kbps networks) Jitter Frequency Jitter Tolerance ( UIpp ) G.823 - E4 Tolerance Figure 16: Jitter Tolerance - electrical (CMI) interfaces PARAMETER CONDITION MIN NOM MAX UNIT 200Hz to 500Hz 1.5 UIpp 500Hz to 10kHz 750 f-1 µs E4 Jitter Tolerance 10kHz to 3.5MHz 0.075 UIpp 10Hz to 19.3Hz 38.9 UIpp 19.3Hz to 500Hz 750 f-1 µs 500Hz to 6.5kHz 1.5 UIpp 6.5kHz to 65kHz 9800 f-1 µs STM-1e Jitter Tolerance 65kHz to 1.3MHz 0.15 UIpp

Page: 36 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) 0.01 0.1 100 1.E+00 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Optical (NRZ) Interfaces STM-1 / STS-3 / OC-3 Tolerance G.825 - STM-1 Tolerance Jitter Frequency Jitter Tolerance ( UIpp ) Figure 17: Jitter Tolerance - optical (NRZ) interfaces PARAMETER CONDITION MIN NOM MAX UNIT 10Hz to 19.3Hz 38.9 UIpp 19.3Hz to 68.7Hz 750 f-1 µs 68.7Hz to 6.5kHz 1.5 UIpp 6.5kHz to 65kHz 9800 f-1 µs OC-3/STS-3/STM-1 (optical) Jitter Tolerance 65kHz to 1.3MHz 0.15 UIpp

Page: 37 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. The corner frequency of the Rx DLL is approximately 120 kHz. Receiver ji tter transfer function is not tested during production test. -10 Figure 18: Jitter Transfer PARAMETER CONDITION MIN NOM MAX UNIT Receiver Jitter transfer function below 120 kHz 0.1 dB Jitter transfer function roll-off 20 dB per decade

Page: 38 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 ELECTRICAL SPECIFICATIONS (continued) CMI MODE LOSS OF SIGNAL CONDITION PARAMETER CONDITION MIN TYP MAX UNIT LOS threshold Combination of cable loss at 78MHz and flat loss -35 -19 -15 dB LOS timing 10 110 255 UI Nominal value Maximum cable loss Loss of Signal must be cleared Loss of Signal must be declared Tolerance range LOS can be detected or cleared 3 dB 15dB 35dB

APPLICATION INFORMATION

EXTERNAL COMPONENTS: COMPONENT PIN(S) VALUE UNITS TOLERANCE Receiver Termination Resistor, CMI Mode RXxP RXxN 75 Ω 1% Transmitter Termination Resistor, CMI Mode CMIxP CMIxN 75 Ω 1% (CMI) TRANSFORMER SPECIFICATIONS: COMPONENT VALUE UNITS TOLERANCE Turns Ratio for the Receiver 1:1 Turns Ratio for the Transmitter (center-tapped) 1:1CT Suggested Manufacturers: Halo, Tamura, MiniCircuits, Belfuse THERMAL INFORMATION: PACKAGE CONDITIONS ΘJA ( ˚C/W) Standard 128-pin JEDEC LQFP (78P2352-IGT) No forced air; 4-layer JEDEC test board 46 (Recommended) Thernally enhanced Exposed Pad 128-pin JEDEC LQFP (78P2352-IEL) No forced air; 4-layer JEDEC test board; Die attach pad soldered to PCB 24.8 SCHEMATICS For reference schematics, layout guidelines, recommended transformer part numbers, etc. please check Teridian Semiconductor's website or contact your local sales repres entative for the latest application note(s) and/or demo board manuals.

Page: 39 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 MECHANICAL SPECIFICATIONS MAX. 1.600 0.400 13.950 +/- 0.100 0.180 +/- 0.050 0.600 +/- 0.150 1.400 +/- 0.050 0.100 +/- 0.050 16.000 +/- 0.200 5.00 REF. MAX. EXPOSED PAD AREA 128 16.000 +/- 0.200 5.00 REF. 12.400 REF. 14.000 +/- 0.100 14.000 +/- 0.100 78P2352-IEL 128-pin Exposed Pad JEDEC LQFP (Bottom View)

Page: 40 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 MECHANICAL SPECIFICATIONS 15.8 (0.622) 16.2 (0.637) 13.8 (0.543) 14.2 (0.559) 0.05 (0.002) 0.15 (0.006) 0.13 (0.005) 0.23 (0.009) 15.8 (0.622) 16.2 (0.637) 0.60 Typ. (0.024) 0.40 Typ. (0.015) . 1.60 Max (0.063) Top View Side View 78P2352-IGT 128-pin Standard JEDEC LQFP (Top View)

Page: 41 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4

PACKAGE INFORMATION

(Top View) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 TXOUT1 TXOUT0 N/C N/C VCC GND SI1CKP SI1CKN INTTX2B SI1DP SI1DN VCC GND TXPD CKMODE GND LPBK1 LPBK2 LOS2 LOL2 VCC GND VDD VSS SO1CKP SO1CKN INTRX2B SO1DP SO1DN PI1CK PI10D PI11D PI12D PI13D PTO1CK VSS VDD PO1CK VSS VDD PO13D PO12D VSS VDD PO11D PO10D VSS VDD VDD VSS PO20D PO21D VDD VSS PO22D PO23D VDD VSS PO2CK VDD VSS PTO2CK PI23D PI22D SCK_MON SEN_CMI SDI_PAR SDO_E4 VCC GND SI2CKP SI2CKN INTTX1B SI2DP SI2DN VCC GND PORB TGND CKSL LOS1 LOL1 FRST SPSL N/C N/C VCC GND SO2CKP SO2CKN INTRX1B SO2DP SO2DN PI2CK PI20D PI21D ECL1N ECL1P VCC TX1CKN TX1CKP GND CMI1N CMI1P VCC RX1N RX1P GND VCC GND GND GND GND CKREFP CKREFN VCC GND RX2P RX2N VCC CMI2P CMI2N GND TX2CKP TX2CKN VCC ECL2P ECL2N 78P2352

ORDERING INFORMATION

PART DESCRIPTION ORDER NUMBER PACKAGE MARK 128-pin LQFP, Open-drain outputs for LOSx, LOLx, INTTRx 78P2352-IGT 78P2352-IGT xxxxxxxxxxP6 128-pin LQFP, CMOS type outputs for LOSx, LOLx, INTTRx 70P2352-IGT 70P2352-IGT xxxxxxxxxxP6 128-pin LQFP w/ Exposed Solder Pad, Open-drain outputs for LOSx, LOLx, INTTRx 78P2352-IEL 78P2352-IEL xxxxxxxxxxP6 Tape & Reel option append ‘R’ n/a Lead-free option append ‘/F’ xxxxxxx-xxx xxxxxxxxxxP6F

Page: 42 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 Revison History -- Contact Teridian for revision history of earlier releases v2-0 March 14, 2005: Final Datasheet Release ƒ Updated Ordering Numbers to reflect production silicon revision A06 ƒ Improved/modified Functional Descriptions for: o Reference Clock, Rx LOS & LOL detectors, Synchronous (Re-Timing) Transmit Modes, Tx FIFO, Tx Driver, Tx LOL detector, and Power-on Reset description ƒ Improved/modified Register Descriptions for: o xCMIINV invert bits, FRST, RxLOL, and TxLOL ƒ Improved/modified Pin Descriptions for: o PTOCK, FRST, SEN_CMI, GND pin 63 ƒ Updated Electrical Specification min/max limits for: o DC Characteristics, o CID, CIU, CIT, and PO pin types o CMI Loss of Signal Conditions v2-2 August 12, 2005: ƒ Changed name and logo from TDK to Teridian ƒ Updated Rx and Tx Loss of Lock descriptions ƒ Added Full Remote (digital) Loopback and updated Remote (analog) Loopback descriptions v2-3 August 15, 2006 ƒ Updated Ordering Numbers to remove silicon revision A06 ƒ Updated Package Mark from C6 to P6 v2-4 September 20, 2006 ƒ Corrected several typos in the mechanical drawing of IGT package If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of ord er acknowledgment, including those pertaining to warranty, patent in fringement and limitation of li ability. Teridian Semiconduct or Corporation (TSC) reserves the right to make changes in specifications at any time without notic e. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridiansemiconductor.com