709289S12PFGI8

IDT709289L RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 7.5/9/12ns (max.) – Industrial: 9ns (max.) ◆ Low-power operation – IDT709289L Active: 1.2W (typ.) Standby: 2.5mW (typ.) ◆ Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic ◆ Full synchronous operation on both ports – 4ns setup to clock and 0ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode ◆ Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ◆ TTL- compatible, single 5V (±10%) power supply ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in a 100-pin Thin Quad Flatpack (TQFP) package ◆ Green parts available, see ordering information HIGH-SPEED 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT709289L 0a 1a 0b 1b 0/1ab I/O Control FT/PIPER R/WR UBR LBR CE0R OER CE 1R MEMORY ARRAY Counter/ Address Reg. 4842 drw 01 A15R A0R CLK R ADSR CNTENR CNTRSTR I/O8L-I/O15L I/O0L-I/O7L I/O8R -I/O15R I/O0R -I/O7R A0L CLK L ADSL A15L CNTENL CNTRSTL Counter/ Address Reg. R/WL UBL LBL CE0L OEL CE 1L 1 1b 0b 1a 0a0/1 ba I/O Control FT/PIPEL LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Index 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 IDT709289PF PN100 (4) 100-Pin TQFP Top View(5) 4842 drw 02a I/O15L OEL R/WL CNTRSTL CE 1L CE0L Vcc NC A14L A13L NC A12L A11L A10L A9L I/O10L I/O11L I/O12L I/O13L I/O14L UBL LBL GND I/O6R I/O5R FT/PIPER OER R/WR CNTRSTR CE 1R CE0R NC NC GND A12R A13R A11R A10R A9R A14R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND UBR LBR I/O4R I/O3R I/O2R I/O0R I/O0L I/OIL GND I/O2L I/O4L I/O5L I/O6L I/O7L I/O3L I/O1R I/O7R NC I/O8R I/O9R I/O8L I/O9L FT/PIPEL A8R A7R A8L A7L A6R A5R A4R A3R A2R A1R A0R CNTENR CLK R ADSR ADSL CLK L CNTENL A0L GND A2L A3L A5L A6L A1L A4L GND Vcc Vcc A15L A15R Pin Configurations(1,2,3) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.

Description

The IDT709289 is a high-speed 64K x 16 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT709289 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE 0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 1.2W of power.

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = V IH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table I—Read/Write and Enable Control (1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O8-15 Lower Byte I/O0-7 Mode X ↑ H X X X X High-Z High-Z Deselected—Power Down X ↑ X L X X X High-Z High-Z Deselected—Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ LHLHL D A T A IN High-Z Write to Upper Byte Only X ↑ LHHLL H i g h - Z D A T A IN Write to Lower Byte Only X ↑ LHLLL D A T A IN DATAIN Write to Both Bytes L ↑ LHLHH D A T A OUT High-Z Read Upper Byte Only L ↑ LHHLH H i g h - ZD A T A OUT Read Lower Byte Only L ↑ LHLLH D A T A OUT DATAOUT Read Both Bytes H X L H L L X High-Z High-Z Outputs Disabled 4842 tbl 02 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 15L A0R - A 15R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select LBL LBR Lower Byte Select ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VCC Power GND Ground 4842 tbl 01

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage Recommended DC Operating Conditions NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed V cc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Absolute Maximum Ratings(1) NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. C OUT also references CI/O. Capacitance(1) (TA = +25°C, f = 1.0MHz) NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. NOTES: 1. V TERM must not exceed V cc + 10%. 2. V IL > -1.5V for pulse width less than 10ns. Grade Ambient Temperature(2) GND Vcc Commercial 0 OC to +70 OC0 V 5 . 0 V + 10% Industrial -40 OC to +85OC0 V 5 . 0 V + 10% 4842 tbl 04 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(1) V VIL Input Low Voltage -0.5 (2 ) ____ 0.8 V 4842 tbl 0 5 Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance V IN = 3dV 9 pF COUT(3) Output Capacitance V OUT = 3dV 10 pF 4842 tbl 07 Symbol Rating Commercial & Industrial Unit VTE RM(2) T erminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS T emperature Under Bias -55 to +125 oC TST G Storage T emperature -65 to +150 oC IOUT DC Output Current 50 mA 4842 tbl 06 NOTES: 1. "H" = V IH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. 6. While an external address is being loaded ( ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily. Truth Table II—Address Counter Control (1,2,6) Address Previous Address Addr Used CLK ADS CNTEN CNTRST I/O(3) Mode XX 0 ↑ XX L D I/ O(0) Counter Reset to Address 0 An X An ↑ L (4 ) XH D I/ O(n) External Address Loaded into Counter An Ap Ap ↑ HH H D I/O(p ) External Address Blocked—Counter Disabled (Ap reused) XA p A p + 1 ↑ H L (5) HD I/O(p +1) Counter Enable—Internal Address Generation 4842 tbl 03

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I CC DC(f=0) = 150mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%) 709289L7 Com'l Only 709289L9 Com'l & Ind 709289L12 Com'l Only ICC Dynamic Operating Current (Both Ports Active) CE L and CER= VIL Outputs Disabled f = fMAX(1) COM'L L 275 465 250 400 230 355 mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CE L = CER = V IH f = fMAX(1) COM'L L 95 150 80 135 70 110 mA ISB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = VIH(3) Active Port Outputs Disabled, f=f MAX(1) COM'L L 200 295 175 275 150 240 mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CE R and CEL > VCC - 0.2V VIN > VCC - 0.2V or ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VCC - 0.2V (5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = f MAX(1) COM'L L 190 290 170 270 140 225 mA 4842 tbl 09 Temperature Supply Voltage Range (VCC = 5.0V ± 10%) NOTE: 1. At Vcc < 2.0V input leakages are undefined. Symbol Parameter Test Conditions 709289L UnitMin. Max. |ILI| Input Leakage Current (1) VCC = 5.5V, V IN = 0V to V CC ___ 5µ A |ILO| Output Leakage Current CE0 = V IH or CE 1 = V IL, VOUT = 0V to V CC ___ 5µ A VOL Output Low Voltage I OL = +4mA ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ V 4842 tbl 08

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guarant eed by device characteriza- tion, but is not production tested. 2. The Pipelined output parameters (t CYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE), FT/PIPER and FT/PIPEL. (Read and Write Cycle Timing)(3) (VCC = 5V ± 10%, TA = 0°C to +70°C) 709289L7 Com'l Only 709289L9 Com'l & Ind 709289L12 Com'l Only tCYC1 Clock Cycle Time (Flow-Through) (2) 22 ____ 25 ____ 30 ____ ns tCYC2 Clock Cycle Time (Pipelined) (2) 12 ____ 15 ____ 20 ____ ns tCH1 Clock High Time (Flow-Through) (2) 7.5 ____ 12 ____ 12 ____ ns tCL 1 Clock Low Time (Flow-Through) (2) 7.5 ____ 12 ____ 12 ____ ns tCH2 Clock High Time (Pipelined) (2) 5 ____ 6 ____ 8 ____ ns tCL 2 Clock Low Time (Pipelined) (2) 5 ____ 6 ____ 8 ____ ns tOL Z Output Enable to Output Low-Z(1) 2 ____ 2 ____ 2 ____ ns tOHZ Output Enable to Output High-Z (1) 17 17 17 n s tCD1 Clock to Data Valid (Flow-Through) (2) ____ 18 ____ 20 ____ 25 ns tCD2 Clock to Data Valid (Pipelined) (2) ____ 7.5 ____ 9 ____ 12 ns tDC Data Output Hold After Clock High 2 ____ 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z (1) 292929 n s tCKLZ Clock High to Output Low-Z (1) 2 ____ 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 28 ____ 35 ____ 40 ns 4842 tbl 11

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,7) Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,7) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X" here denotes Left or Right port. The diagram is with respect to that port. A n A n+1 A n+2 A n+3 tCYC1 tCH1 tCL1 R/W ADDRESS DATA OUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 4842 drw 07 (1) (1) (1) (1) (2) CE 1 UB,LB (4) tSB tHB tSW tHW tSA tHA tDC tDC (5) tSC tHC tSB tHB An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE 1 UB,LB (4) DATA OUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 4842 drw 08 (1) (1) (1) (2) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (5) (1 Latency) (6) (6)

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7) NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709289 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for t CWDD. If tCCS > maximum specified, then data from right port READ is not valid until t CCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". Timing Waveform of a Bank Select Pipelined Read(1,2) tSC tHC CE0(B1) ADDRESS (B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 4842 drw 09 Q 0 Q 1 Q 3DATA OUT(B1) tCH2 tCL2 tCYC2 (3) ADDRESS (B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATA OUT(B2) Q 2 Q 4 tCD2 tCD2 tCKHZ tCD2 tCKLZtDC tCKHZ tCD2 tCKLZ (3) (3) tSC tHC (3) tCKHZ (3) tCKLZ (3) tCD2 tDC tSC tHC tSC tHC DATA IN "A" CLK "B" R/W "B" ADDRESS "A" R/W "A" CLK "A" ADDRESS "B" NO MATCHMATCH NO MATCHMATCH VALID tCWDD tCD1 tDC DATA OUT "B" 4842 drw 10 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCCS tDC tSA tSW tHA (6) (6)

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATA IN Dn + 2 CE0 CLK 4842 drw 11 Qn Qn + 3DATA OUT CE 1 UB,LB tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (4) (2) (1) (1) tSW tHW WRITE(5) R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATA IN Dn + 3Dn + 2 CE0 CLK 4842 drw 12 DATA OUT Qn Qn + 4 CE 1 UB,LB OE tCH2 tCL2 tCYC2 tCKLZ (1) tCD2 tOHZ (1) tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (4) (2) tSW tHW

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATA IN Dn + 2 CE0 CLK 4842 drw 13 QnDATA OUT CE 1 UB,LB tCD1 Qn + 1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tCD1 tDC tCKHZ Qn + 3 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ NOP READ tCKLZ (4) (2) (1) (1) tSW tHW WRITE(5) R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5(4) DATA IN Dn + 2 CE0 CLK 4842 drw 14 QnDATA OUT CE 1 UB,LB tCD1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tDC Qn + 4 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ WRITE READ tCKLZ (2) Dn + 3 tOHZ (1) (1) tSW tHW OE tOE

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) Timing Waveform of Flow-Through Read with Address Counter Advance(1) NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. ADDRESS An CLK DATA OUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3 ADS CNTEN tCYC2 tCH2 tCL2 4842 drw 15 tSA tHA tSAD tHAD tCD2 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tSAD tHAD tSCN tHCN READ WITH COUNTER Qn + 1 ADDRESS An CLK DATA OUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 ADS CNTEN tCYC1 tCH1 tCL1 4842 drw 16 tSA tHA tSAD tHAD READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tCD1 tDC tSAD tHAD tSCN tHCN READ WITH COUNTER

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) Timing Waveform of Counter Reset (Pipelined Outputs)(2) NOTES: 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. 7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. ADDRESS An CLK DATA IN Dn Dn + 1 Dn + 1 Dn + 2 ADS CNTEN tCH2 tCL2 tCYC2 4842 drw 17 INTERNAL (3) ADDRESS An(7) An + 1 An + 2 An + 3 An + 4 Dn + 3 Dn + 4 tSA tHA tSAD tHAD WRITE COUNTER HOLD WRITE WITH COUNTERWRITE EXTERNAL ADDRESS WRITE WITH COUNTER tSD tHD ADDRESS An tCH2 tCL2 tCYC2 Q 0 Q 1 CLK DATA IN R/W CNTRST 4842 drw 18 INTERNAL (3) ADDRESS ADS CNTEN tSRST tHRST tSD tHD tSW tHW COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Qn An + 1 An + 2 READ ADDRESS n+1 DATA OUT tSA tHA

1 An An + 1

(5) (6)Ax (4) (6)

transition of the clock signal. various chip enables in order to expand two devices in depth. Figure 4. Depth and Width Expansion with IDT709289

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 A Power Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0 C to +70 C) Industrial (-40 C to +85 C) PF 100-pin TQFP (PN100 ) XXXXX Device Type Speed in nanoseconds Commercial Only Commercial & Industrial Commercial Only 4842 drw 20 L Low Power 709289 1024K (64K x 16-Bit) Synchronous Dual-Port RAM G (2) Green A Blank Tube or Tray Tape & Reel A Datasheet Document History 9/30/99: Initial Public Release 11/10/99: Replaced IDT logo 12/22/99: Page 1 Added missing diamond 1/5/01: Page 4 Changed information in Truth Table II Increased storage temperature parameter Clarified T A parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Removed Preliminary specification 10/18/01: Page 2 Added date revision for pin configuration Page 5 & 7 Added Industrial temp to column heading and values for 9ns speed to DC & AC Electrical Characteristics Page 15 Added Industrial temp offering to 9ns ordering information Page 4, 5 & 7 Removed Industrial temp footnote from all tables Page 1 & 15 Replace TM logo with ® logo Datasheet Document History (con't on next page)

6.42 IDT709289L High-Speed 64K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 05/05/06: Page 1 Added green availability to features Page 15 Added green indicator to ordering information 01/19/09: Page 15 Removed "IDT" from orderable part number 02/27/15: Page 2 Removed IDTin reference to fabrication Page 2 Removed date from PN100 pin configuration Page 2&15The package code PN100-1 changed to PN100 to match standard package codes, Page 6 Removed typo from typical output derating drawing Page 15 Added Tape & Reel to the Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 02/26/18:

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