709269S9PFG8

IDT709279_18 IDT | Alldatasheet

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Technical content

Features

◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 9/12/15ns (max.) – Industrial: 12ns (max.) ◆ Low-power operation – IDT709279/69S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709279/69L Active: 950mW (typ.) Standby: 1mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via the FT/PIPE pin ◆ Dual chip enables allow for depth expansion without additional logic ◆ Counter enable and reset features ◆ Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 67MHz operation in Pipelined output mode ◆ Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ◆ TTL- compatible, single 5V (±10%) power supply ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in a 100-pin Thin Quad Flatpack (TQFP) package ◆ Green parts available. See ordering information HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM IDT709279/69S/L FT/PIPER R/WR UBR LBR CE0R OER CE 1R I/O Control MEMORY ARRAY Counter/ Address Reg. I/O Control 3243 drw 01 A14R (1) A0R CLK R ADSR CNTENR CNTRSTR I/O8L- I/O15L I/O0L-I/O7L I/O8R -I/O15R I/O0R -I/O7R A0L CLK L ADSL A14L(1) CNTENL CNTRSTL Counter/ Address Reg. R/WL UBL LBL CE0L OEL CE 1L 0a 1a 0b 1b 0/1ab FT/PIPEL 1a 0a1b 0b0/1 ba NOTE: 1. A 14X is a NC for IDT709269. LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT709279/69 is a high-speed 32/16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Pin Configurations(2,3,4) With an input data register, the IDT709279/69 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 950mW of power. Index 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 0 0 9 9 9 8 9 79 6 9 59 49 3 9 29 1 9 08 9 8 88 7 8 68 5 8 48 3 8 28 18 0 7 97 8 7 77 6 IDT709279/69PF PN100 (5) 100-Pin TQFP Top View(6) 3243 drw 02 I/O15L OEL R/WL CNTRSTL CE 1L CE0L VCC NC A14L(1) A13L NC NC A12L A11L A10L A9L I/O10L I/O11L I/O12L I/O13L I/O14L UBL LBL GND I/O I/O FT/PIPER OER R/WR CNTRSTR CE 1R CE0R NC NC GND A12R A13R A11R A10R A9R A14R (1) NC I/O 10R I/O11R I/O12R I/O13R I/O14R I/O15R GND UBR LBR I/O I/O I/O I/O I/O I/O IL GND I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O FT/PIPEL A A A8L A7L A6R A A4R A A A1R A0R CNTEN R CLK R ADS R ADSL CLK L CNTEN L A0L GND A A A A A1L A4L GND V CC V CC NOTES: 1. A 14X is a NC for IDT709269. 2. All V CC pins must be connected to power supply. 3. All GND pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table I—Read/Write and Enable Control (1,2,3) OE CLK CE0 CE1 UB LB R/W Upper By te I/O8-15 Lower Byte I/O0-7 Mode X ↑ HXXXX H igh-Z H igh-Z D eselected— Power Down X ↑ X L X X X High-Z High-Z Deselected—Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ LHLHL D IN High-Z Write to Upper Byte Only X ↑ LH HLL H igh-Z D IN Write to Lower Byte Only X ↑ LH LLL D IN DIN Write to Both Bytes L ↑ LHLHH D OUT High-Z Read Upper Byte Only L ↑ LH HLH H igh-Z D OUT Read Lower Byte Only L ↑ LHLLH D OUT DOUT Read Both Bytes H X L H L L X High-Z High-Z Outputs Disabled 3243 tbl 02 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (3) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 14L(1) A0R - A 14R(1) Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select (2) LBL LBR Lower Byte Select (2) ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VSS Power GND Ground 3243 tbl 01 NOTES: 1. A14x is a NC for IDT709269. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE 1 are single buffered when FT/PIPE = V IL, CEo and CE 1 are double buffered when FT/PIPE = V IH, i.e. the signals take two cycles to deselect.

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don't Care. 2. CE0, LB, UB, and OE = V IL; CE 1 and R/ W = V IH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE 1, UB and LB. 5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other signals including CE0, CE 1, UB and LB. Recommended Operating Temperature and Supply Voltage (1) Recommended DC Operating Conditions NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > VCC + 10%. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselect. Absolute Maximum Ratings (1) NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. C OUT also references C I/O. Capacitance (1) (TA = +25°C, f = 1.0MHz) Truth Table II—Address Counter Control (1,2) NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. NOTES: 1. V TERM must not exceed V CC + 10%. 2. V IL > -1.5V for pulse width less than 10ns. External Address Previous Internal Address Internal Address Used CLK ADS CNTEN CNTRST I/O(3) MODE An X An ↑ L (4) XH D I/O (n) External Address Used XA n A n + 1 ↑ H L (5) HD I/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ HH H D I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX A 0 ↑ XX L (4) DI/O(0) Counter Reset to Address 0 3243 tbl 03 Grade Ambient Temperature GND V CC Commercial 0 OC to +70 OC0 V 5 .0V + 10% Industrial -40 OC to +85OC0 V 5 .0V + 10% 3243 tbl 04 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(1) V VIL Input Low Voltage -0.5 (2) ____ 0.8 V 3243 tbl 05 Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance V IN = 0V 9 pF COUT(2) Output Capacitance V OUT = 0V 10 pF 3243 tbl 07 Symbol Rating Commercial & Industrial Unit VTERM(2) T erminal Voltage with Respect to GND -0.5 to +7.0 V T BIAS T emperatureUnder Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC TJN Junction Temperature +150 oC IOUT DC Output Current 50 mA 3243 tbl 06

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. V CC = 5V, TA = 25°C for Typ, and are not production tested. I CC DC (f=0) = 150mA (Typ). 5. CEX = V IL means CE0X = V IL and CE 1X = V IH CEX = V IH means CE0X = V IH or CE 1X = V IL CEX < 0.2V means CE0X < 0.2V and CE 1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE 1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 'X' in part numbers indicate power rating (S or L). Temperature and Supply Voltage Range (6) (VCC = 5V ± 10%) 709279/69X9 Com'l Only 709279/69X12 Com'l & Ind 709279/69X15 Com'l Only ICC Dynamic Operating Current (Both Ports Active) CE L and CER= V IL Outputs Disabled f = f MAX(1) COM'L S L 210 210 390 350 200 200 345 305 190 190 325 285 mA IND S L ____ ____ ____ ____ 200 200 380 340 ____ ____ ____ ____ ISB1 Standby Current (Both Ports - TTL Level Inputs) CE L = CER = V IH f = f MAX(1) COM'L S L 135 115 110 110 mA IND S L ____ ____ ____ ____ 125 105 ____ ____ ____ ____ ISB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = V IH(3) Active Port Outputs Disabled, f=fMAX(1) COM'L S L 140 140 270 240 130 130 230 200 120 120 220 190 mA IND S L ____ ____ ____ ____ 130 130 245 215 ____ ____ ____ ____ ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CE R and CEL > VCC - 0.2V VIN > VCC - 0.2V or COM'L S L 1.0 0.2 1.0 0.2 1.0 0.2 mA IND S L ____ ____ ____ ____ 1.0 0.2 ____ ____ ____ ____ ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VCC - 0.2V (5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = f MAX(1) COM'L S L 130 130 245 225 120 120 205 185 110 110 195 175 mA IND S L ____ ____ ____ ____ 120 120 220 200 ____ ____ ____ ____ 3243 tbl 09 Temperature Supply Voltage Range (VCC = 5.0V ± 10%) NOTE: 1. At V CC < 2.0V input leakages are undefined. Symbol Parameter Test Conditions 709279/69S/L UnitMin. Max. |ILI| Input Leakage Current (1) VCC = 5.5V, V IN = 0V to V CC ___ 10 µA |ILO| Output Leakage Current CE 0 = V IH or CE 1 = V IL, VOUT = 0V t o V CC ___ 10 µA VOL Output Low Voltage I OL = +4mA ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ V 3243 tbl 08

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza- tion, but is not production tested. 2. The Pipelined output parameters (t CYC2, t CD2) apply to either or both left and right ports when FT/PIPE = V IH. Flow-through parameters (t CYC1, t CD1) apply when FT/PIPE = V IL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable ( OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 4. 'X' in part number indicates power rating (S or L). (Read and Write Cycle Timing) (3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C) 709279/69X9 Com'l Only 709279/69X12 Com'l & Ind 709279/69X15 Com'l Only tCYC1 Clock Cycle Time (Flow-Through) (2) 25 ____ 30 ____ 35 ____ ns tCYC2 Clock Cycle Time (Pipelined) (2) 15 ____ 20 ____ 25 ____ ns tCH1 Clock High Time (Flow-Through) (2) 12 ____ 12 ____ 12 ____ ns tCL1 Clock Low Time (Flow-Through) (2) 12 ____ 12 ____ 12 ____ ns tCH2 Clock High Time (Pipelined) (2) 6 ____ 8 ____ 10 ____ ns tCL2 Clock Low Time (Pipelined) (2) 6 ____ 8 ____ 10 ____ ns tOLZ Output Enable to Output Low-Z (1) 2 ____ 2 ____ 2 ____ ns tOHZ Output Enable to Output High-Z (1) 17 17 17 n s tCD1 Clock to Data Valid (Flow-Through) (2) ____ 20 ____ 25 ____ 30 ns tCD2 Clock to Data Valid (Pipelined) (2) ____ 9 ____ 12 ____ 15 ns tDC Data Output Hold After Clock High 2 ____ 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z (1) 292929 n s tCKLZ Clock High to Output Low-Z (1) 2 ____ 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 35 ____ 40 ____ 50 ns 3243 tbl 11

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow -T hrough Output (FT/PIPE"X" = VIL)(3,7) Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,7) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = V IL, CNTEN and CNTRST = V IH. 4. The output is disabled (High-Impedance state) by CE0 = V IH, CE 1 = V IL, UB = V IH, or LB = V IH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state). 7. "x" denotes Left or Right port. The diagram is with respect to that port. An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/W ADDRESS DATA OUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 3243 drw 07 (1) (1) (1) (1) (2) CE 1 UB,LB (4) tSB tHB tSW tHW tSA tHA tDC tDC (5) tSC tHC tSB tHB An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/W ADDRESS CE0 CLK CE 1 UB,LB (4) DATA OUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 3243 drw 08 (1) (1) (1) (2) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (5) (1 Latency) (6) (6)

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709279/69 for this waveform, and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = V IL; CE 1(B1), CE 1(B2), R/ W, CNTEN, and CNTRST = V IH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. 5. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to. 6. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for t CWDD. If tCCS > maximum specified, then data from right port READ is not valid until t CCS + t CD1. tCWDD does not apply in this case. Timing Waveform of a Bank Select Pipelined Read (1,2) tSC tHC CE0(B1) ADDRESS (B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 3243 drw 09 Q 0 Q 1 Q 3DATA OUT(B1) tCH2 tCL2 tCYC2 (3) ADDRESS (B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATA OUT(B2) Q 2 Q 4 tCD2 tCD2 tCKHZ tCD2 tCKLZtDC tCKHZ tCD2 tCKLZ (3) (3) tSC tHC (3) tCKHZ (3) tCKLZ (3) tCD2 tDC tSC tHC tSC tHC Timing Waveform of a Bank Select Flow -T hrough Read (6) tSC tHC CE0(B1) ADDRESS (B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 3243 drw 09a D0 D3 tCD1 tCKLZ tCKHZ (1) (1) D1DATA OUT(B1) tCH1 tCL1 tCYC1 (1) ADDRESS (B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATA OUT(B2) D2 D4 tCD1 tCD1 tCKHZ tDC tCD1 tCKLZ tSC tHC (1) tCKHZ (1) tCKLZ (1) tCD1 tDC tSC tHC tSC tHC D 5 tCD1 tCKLZ (1) tCKHZ (1)

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform w ith Port-to-Port Flow -T hrough Read(1,2,3,5) DATA IN "A" CLK "B" R/W "B" ADDRESS "A" R/W "A" CLK "A" ADDRESS "B" NO MATCHMATCH NO MATCHMATCH VALID tCWDD tCD1 tDC DATA OUT "B" 3243 drw 10 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCCS tDC tSA tSW tHA (4) (4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. 3. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to. 4. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for t CWDD. If tCCS > maximum specified, then data from right port READ is not valid until t CCS + t CD1. tCWDD does not apply in this case. 5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATA IN Dn + 2 CE0 CLK 3243 drw 11 Qn Qn + 3DATA OUT CE 1 UB,LB tCD2 tCKHZ tCKLZ tCD2 tSC tHC tSB tHB tSW tHW tSA tHA tCH2 tCL2 tCYC2 READ NOP READ tSD tHD (4) (2) (1) (1) tSW tHW WRITE(5) R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5 DATA IN Dn + 3Dn + 2 CE0 CLK 3243 drw 12 DATA OUT Qn Qn + 4 CE 1 UB,LB OE tCH2 tCL2 tCYC2 tCKLZ (1) tCD2 tOHZ (1) tCD2 tSD tHD READ WRITE READ tSC tHC tSB tHB tSW tHW tSA tHA (4) (2) tSW tHW

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow -T hrough Read-to-Write-to-Read (OE = VIL)(3) Timing Waveform of Flow -T hrough Read-to-Write-to-Read (OE Controlled)(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = V IL; CE 1, CNTEN, and CNTRST = V IH. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. R/W ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4 DATA IN Dn + 2 CE0 CLK 3243 drw 13 QnDATA OUT CE 1 UB,LB tCD1 Qn + 1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tCD1 tDC tCKHZ Qn + 3 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ NOP READ tCKLZ (4) (2) (1) (1) tSW tHW WRITE(5) R/W ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5(4) DATA IN Dn + 2 CE0 CLK 3243 drw 14 QnDATA OUT CE 1 UB,LB tCD1 tCH1 tCL1 tCYC1 tSD tHD tCD1 tDC Qn + 4 tCD1 tDC tSC tHC tSB tHB tSW tHW tSA tHA READ WRITE READ tCKLZ (2) Dn + 3 tOHZ (1) (1) tSW tHW OE tOE

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read w ith Address Coun ter Advance (1) Timing Waveform of Flow -T hrough Read w ith Address Counter Advance (1) NOTES: 1. CE0, OE, UB, and LB = V IL; CE 1, R/ W, and CNTRST = V IH. 2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH, then the data output remains constant for subsequent clocks. ADDRESS An CLK DATA OUT Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3 ADS CNTEN tCYC2 tCH2 tCL2 3243 drw 15 tSA tHA tSAD tHAD tCD2 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tSAD tHAD tSCN tHCN READ WITH COUNTER Qn + 1 ADDRESS An CLK DATA OUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 ADS CNTEN tCYC1 tCH1 tCL1 3243 drw 16 tSA tHA tSAD tHAD READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD tCD1 tDC tSAD tHAD tSCN tHCN READ WITH COUNTER

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write w ith Address Counter Advan ce (Flow -Through or Pipelined Outputs)(1) Timing Waveform of Counter Reset (Pipelined Outputs )(2) NOTES: 1. CE0, UB, LB, and R/ W = V IL; CE 1 and CNTRST = V IH. 2. CE0, UB, LB = V IL; CE 1 = V IH. 3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH. 4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR 0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. ADDRESS An CLK DATA IN Dn Dn + 1 Dn + 1 Dn + 2 ADS CNTEN tCH2 tCL2 tCYC2 3243 drw 17 INTERNAL (3) ADDRESS An(1) An + 1 An + 2 An + 3 An + 4 Dn + 3 Dn + 4 tSA tHA tSAD tHAD WRITE COUNTER HOLD WRITE WITH COUNTERWRITE EXTERNAL ADDRESS WRITE WITH COUNTER tSD tHD ADDRESS An tCH2 tCL2 tCYC2 Q 0 Q 1 CLK DATA IN R/W CNTRST 3243 drw 18 INTERNAL (3) ADDRESS ADS CNTEN tSRST tHRST tSD tHD tSW tHW COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Qn An + 1 An + 2 READ ADDRESS n+1 DATA OUT tSA tHA

1 An An + 1

(4) (5) (6)Ax

operation of the address counters for fast interleaved memory applications. enables in order to expand two devices in depth. Figure 4. Depth and Width Expansion with IDT709279/69

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

A Power Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF 100-pin TQFP (PN100) 3243 drw 20 S L Standard Power Low Power 709279 709269 512K (32K x 16-Bit) Synchronous Dual-Port RAM 256K (16K x 16-Bit) Sunchronous Dual-Port RAM Speed in nanoseconds Commercial Only Commercial & Industrial Commercial Only XXXXX Device Type G (2) Green Tube or Tray Tape and Reel A A Blank Ordering Information for Flow -through Devices Old Flow-through Part New Combined Part 70927S/L20 709279S/L9 70927S/L25 709279S/L12 70927S/L30 709279S/L15 3243 tbl 12 NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 IDT Dual-Port Part Number Dual-Port I/O Specitications Clock Specifications IDT Non-PLL Clock DeviceVoltage I/O Input Capacitance Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance 709279/69 5 TTL 9pF 40% 100 150ps 49FCT805T 3243 tbl 13 IDT Clock Solution for IDT709279/69 Dual-Port

6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 12/9/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Pages 13 & 14 Updated timing waveforms Page 15 Added Depth and Width Expansion section 06/03/99: Changed drawing format Page 3 Deleted note 6 for Table II 11/10/99: Replaced IDT logo 03/31/00: Combined Pipelined 709279 family and Flow-through 70927 family offerings into one data sheet Changed ±200mV in waveform notes to 0mV Added corresponding part chart with ordering information 05/24/00: Page 1 Inserted diamond in copy Page 4 Changed information in Truth Table II, Increased storage temperature parameter, clarified TA parameter Page 5 Changed DC Electrical parameters–changed wording from "Open" to "Disabled" Page 16 Fixed typeface in heading Added Industrial Temperature Ranges and removed related notes 08/24/01: Pages 1, 16 and Page Header Removed Preliminary status Page 5 & 7 Removed Industrial Temperature Ranges for 15ns speed from DC and AC Electrical Characteristics Page 16 Removed Industrial Temperature from 15ns speed in ordering information 06/21/04: Consolidated multiple devices into one datasheet Page 2 Added date revision to pin configuration Page 4 Added Junction Temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Page 5 & 6 Added 6ns & 7ns speed DC power numbers to the DC Electrical Characteristics Table Page 8 Added 6ns & 7ns speed AC timing numbers to the AC Electrical Characteristics Table Page 17 Added 6ns & 7ns speed grades to ordering information Added IDT Clock Solution Table Page 1 & 18 Replaced old  logo with new TM logo 01/29/09: Page 17 Removed "IDT" from orderable part number 06/24/15: Page 1 Added green availability to Features Page 2 Removed IDT in reference to fabrication Page 2 Removed date from the 100-pin TQFP configuration Page 2 & 17 The package code PN100-1 changed to PN100 to match standard package codes Page 5 Removed the X6 & X7 speed grade options and combined the X9, X12 & X15 speed grade options into one DC Elec Chars table Page 7 Removed the X6 & X7 speed grade options from the AC Elec Chars table Page 16 Added Green and Tape & Reel indicators to the Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 02/02/18: