7054L20PRFG

IDT7054S_15 IDT | Alldatasheet

Document overview

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Technical content

Features

– Commercial: 20/25/35ns (max.) – Industrial: 25ns (max.) ◆◆◆◆◆ Low-power operation – IDT7054S Active: 750mW (typ.) Standby: 7.5mW (typ.) – IDT7054L Active: 750mW (typ.) Standby: 1.5mW (typ.) ◆◆◆◆◆ True FourPort memory cells which allow simultaneous access of the same memory locations ◆◆◆◆◆ Fully asynchronous operation from each of the four ports: P1, P2, P3, and P4 ◆◆◆◆◆ TTL-compatible; single 5V (±10%) power supply ◆◆◆◆◆ Available in 128 pin Thin Quad Flatpack package ◆◆◆◆◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆◆◆◆◆ Green parts available, see ordering information

Description

The IDT7054 is a high-speed 4K x 8 FourPort™ Static RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT7054 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when all ports simulta- neously access the same FourPort RAM location. The IDT7054 provides four independent ports with separate control, Functional Block Diagram HIGH-SPEED 4K x 8 FourPort TM STATIC RAM MEMORY ARRAY COLUMN I/O PORT 1 ADDRESS DECODE LOGIC PORT 2 ADDRESS DECODE LOGIC COLUMN I/O COLUMN I/O PORT 4 ADDRESS DECODE LOGIC PORT 3 ADDRESS DECODE LOGIC COLUMN I/O R/WP1 I/O0P1-I/O7P1 CEP1 OEP1 A0P1 -A 11P1 R/WP2 CEP2 OEP2 3241 drw 01 I/O0P2-I/O7P2 A0P2 -A 11P2 R/WP4 I/O0P4-I/O7P4 CEP4 OEP4 A0P4 -A 11P4 R/WP3 CEP3 OEP3 I/O0P3-I/O7P3 A0P3 -A 11P3

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. All V CC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode. Fabricated using CMOS high-performance technology, this FourPort SRAM typically operates on only 750mW of power. The IDT7054 is packaged in a 128-pin Thin Quad Flatpack (TQFP). Pin Configuration(1,2,3)

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperatu re Ranges Pin Configurations(1,2) NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. Absolute Maximum Ratings(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > VCC + 10%. NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. Recommended DC Operating Conditions Maximum Operating Temperature and Supply Voltage(1) NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. Capacitance (1) (TA = +25°C, f = 1.0MHz) TQFP ONLY NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. Symbol Pin Name A0 P1 - A 11 P1 Address Lines - Port 1 A0 P2 - A 11 P2 Address Lines - Port 2 A0 P3 - A 11 P3 Address Lines - Port 3 A0 P4 - A 11 P4 Address Lines - Port 4 I/O0 P1 - I/O7 P1 Data I/ O - Port 1 I/O0 P2 - I/O7 P2 Data I/ O - Port 2 I/O0 P3 - I/O7 P3 Data I/ O - Port 3 I/O0 P4 - I/O7 P4 Data I/ O - Port 4 R/W P1 Read/Write - Port 1 R/W P2 Read/Write - Port 2 R/W P3 Read/Write - Port 3 R/W P4 Read/Write - Port 4 GND Ground CE P1 Chip Enable - Port 1 CE P2 Chip Enable - Port 2 CE P3 Chip Enable - Port 3 CE P4 Chip Enable - Port 4 OE P1 Output Enab le - Port 1 OE P2 Output Enab le - Port 2 OE P3 Output Enab le - Port 3 OE P4 Output Enab le - Port 4 VCC Power 3241 tbl 01 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V G N D G r o u n d 000 V VIH Input High Voltage 2.2 ____ 6.0(2) V VIL Input Low Voltage -0.5 (1) ____ 0.8 V 3241 tbl 02 Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance V IN = 0V 9 pF COUT Output Capacitance VOUT = 0V 10 pF 3241 tbl 03 Grade Ambient Temperature GND Vcc Commercial 0 °C to +70°C0 V 5.0V + 10% Industrial -40°C to +85°C 0V 5.0V + 10% 3241 tbl 04 Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC IOUT DC Output Current 50 mA 3241 tbl 05

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. 'X' in part number indicates power rating (S or L). 2. V CC = 5V, T A = +25°C and are not production tested. 3. f = 0 means no address or control lines change. 4. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%) NOTE: 1. At Vcc < 2.0V input leakages are undefined. Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) Symbol Parameter Test Conditions 7054S 7054L UnitMin. Max. Min. Max. |ILI| Input Leakage Current (1) VCC = 5.5V, V IN = 0V to V CC ___ 10 ___ 5µ A |ILO| Output Leakage Current CE = V IH, V OUT = 0V to V CC ___ 10 ___ 5µ A VOL Output Low Voltage I OL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ 2.4 ___ V 2674 tbl 07 Symbol Parameter Condition 7054X20 Com'l Only 7054X25 Com'l & Ind 7054X35 Com'l Only ICC1 Operating Power Supply Current (All Ports Active) CE = V IL Outputs Disabled f = 0(3) COM'L. S L 150 150 300 250 150 150 300 250 150 150 300 250 mA IND. S L ____ ____ ____ ____ 150 150 360 300 150 150 360 300 mA ICC2 Dynamic Operating Current (All Ports Active) CE = V IL Outputs Disabled f = fMAX(4) COM'L. S L 240 210 370 325 225 195 350 305 210 180 335 290 mA IND. S L ____ ____ ____ ____ 225 195 400 340 210 180 395 330 mA ISB Standby Current (All Ports - TTL Level Inputs) CE = V IH f = fMAX(4) COM'L. S L mA IND. S L ____ ____ ____ ____ 115 110 mA ISB1 Full Standby Current (All Ports - All CMOS Level Inputs) All Ports CE > V CC - 0.2V VIN > V CC - 0.2V or COM'L. S L 1.5 0.3 1.5 1.5 0.3 1.5 1.5 0.3 1.5 mA IND. S L ____ ____ ____ ____ 1.5 0.3 4.5 1.5 0.3 4.5 mA 3241 tbl 06

Figure 1. AC Output Test Load Figure 2. Output Test Load

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 2, Any Port(1, 2) NOTES: 1. R/ W = V IH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW. Operating Temperature and Supply Voltage(3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L). 7054X20 Com'l Only 7054X25 Com'l & Ind 7054X35 Com'l Only READ CYCLE tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 20 ____ 25 ____ 35 ns 3241 tbl 09 3241 drw 06 tAOE tLZ tHZ DATAOUT CE tACE VALID DATA OE CURRENT ICC ISB tPU 50% tLZ tPD 50% tHZ

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperatu re Ranges Operating Temperature and Supply Voltage(5) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required t DW. If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Specified for OE = V IH (refer to “Timing Waveform of Write Cycle”, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. 'X' in part number indicates power rating. 7054X20 Com'l Only 7054X25 Com'l & Ind 7054X35 Com'l Only WRITE CYCLE t tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tDW Data Valid to End-of-Write 15 ____ 15 20 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 12 ____ 15 ____ 15 ns tOW Output Active from End-of-Write (1,2) 0 ____ 0 ____ 0 ____ ns tWDD Write Pulse to Data Delay (4) ____ 35 ____ 45 ____ 55 ns tDDD Write Data Valid to Read Data Delay (4) ____ 30 ____ 35 ____ 45 ns 3241 tbl 10

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Ranges CE 3241 drw 08 tAW tAS tWR tDW DATAIN ADDRESS tWC R/W tEW tDH (6) (2) (3) Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8) Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) NOTES: 1. R/ W or CE = V IH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a CE = V IL and a R/ W = V IL. 3. t WR is measured from the earlier of CE or R/ W = V IH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/ W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guarant eed but is not production tested. 8. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off data to be placed on the bus for the required t DW. If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. CE 3241 drw 07 tAW tAS tWR tDW DATAIN ADDRESS tWC R/W tWP DATAOUT tWZ(7) (4) (4) (2) tOW OE (7)tHZtLZ (7) tHZ (6) (3) tDH

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperatu re Ranges Timing Waveform of Write with Port-to-Port Read(1, 2) Functional Description The IDT7054 provides four ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = V IH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. READ/ WRITE conditions are illustrated in the table. Table I – Read/Write Control NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don’t Care, "Z "= High Impedance 2. For valid write operation, no more than one port can write to the same address location at the same time. 3241 drw 09 ADDR"A" tWC DATA"B" MATCH tWP R/W"A" DATAIN"A" ADDR"B" tDH VALID MATCH VALID tDDD tWDD tDW NOTES: 1. OE = V IL for the reading ports. 2. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port. Any Port(1 ) R/W CE OE D0-7 Function X H X Z Port Deselected: Power-Down XHX Z CEP1=CEP2=CEP3=CEP4=VIH Power Down Mode I SB or I SB1 LLX D A T A IN Data on port written into memory (2) HL L D A T A OU T Data in memory output on port XXH Z O u t p u t s D i s a b l e d 3241 tbl 11

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTE: 1. Industrial temperature range is available. For other speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History 1/18/99: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations 6/4/99: Changed drawing format Page 1 Corrected DSC number 9/1/99: Removed Preliminary 11/10/99: Replaced IDT logo 5/23/00: Page 4 Increased storage temperature parameter Clarified T A parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes 10/22/01: Page 2 & 3 Added date revision for pin configurations Page 5, 7 & 8 Added Industrial temp to column heading for 25ns speed to DC & AC Electrical Characteristics Page 11 Added Industrial temp offering to 25ns ordering information Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables Page 6 Changed 5ns to 3ns in AC Test Conditions table Page 1 & 11 Replace TM logo with ® logo

6.42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperatu re Ranges The IDT logo is a registered trademark of Integrated Device Technology, Inc. CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com Datasheet Document History (con't) 02/20/15: Page 1 Added green availability to features Page 2 Removed IDT in reference to fabrication Page 2 2V battery backup for Low-power versions are no longer offered Page 2,3 & 10 The package code PK128-1 changed to PK128 to match standard package codes Page 10 Added Tape and Reel and Green to Ordering Information Pages 1-10 Removed all military data including the G108 pin configuration, changed table headings and ordering information to indicate that there is no longer a military offering for this 7054 device