IDT7052S_16 IDT | Alldatasheet
Document overview
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Technical content
Features
– Commercial: 20/25/35ns (max.) – Industrial: 25ns (max.) – Military: 25/35ns (max.) ◆◆◆◆◆ Low-power operation – IDT7052S Active: 750mW (typ.) Standby: 7.5mW (typ.) – IDT7052L Active: 750mW (typ.) Standby: 1.5mW (typ.) ◆◆◆◆◆ True FourPort memory cells which allow simultaneous access of the same memory locations ◆◆◆◆◆ Fully asynchronous operation from each of the four ports: P1, P2, P3, P4 ◆◆◆◆◆ Versatile control for write-inhibit: separate BUSY input to control write-inhibit for each of the four ports MEMORY ARRAY COLUMN I/O PORT 1 ADDRESS DECODE LOGIC PORT 2 ADDRESS DECODE LOGIC COLUMN I/O COLUMN I/O PORT 4 ADDRESS DECODE LOGIC PORT 3 ADDRESS DECODE LOGIC COLUMN I/O R/WP1 I/O0P1-I/O7P1 CEP1 OEP1 A0P1 -A 10P1 BUSYP2 R/WP2 CEP2 OEP2 2674 drw 01 I/O0P2-I/O7P2 A0P2 -A 10P2 BUSYP1 R/WP4 I/O0P4-I/O7P4 CEP4 OEP4 A0P4 -A 10P4 BUSYP3 R/WP3 CEP3 OEP3 I/O0P3-I/O7P3 A0P3 -A 10P3 BUSYP4 ◆◆◆◆◆ Battery backup operation—2V data retention ◆◆◆◆◆ TTL-compatible; single 5V (±10%) power supply ◆◆◆◆◆ Available in 120 pin Thin Quad Flatpacks and 108 pin PGA ◆◆◆◆◆ Military product compliant to MIL-PRF-38535 QML ◆◆◆◆◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆◆◆◆◆ Green parts available, see ordering information
Description
The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT7052 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges NOTES: 1. All V CC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Configurations(1,2,3) systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when all ports simultaneously access the same FourPort RAM location. The IDT7052 provides four independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode. Fabricated using CMOS high-performance technology, this FourPort SRAM typically operates on only 750mW of power. Low-power (L) versions offer battery backup data retention capability, with each port typically consuming 50µW from a 2V battery. The IDT7052 is packaged in a ceramic 108-pin Pin Grid Array (PGA) and 120-pin Thin Quad Flatpack (TQFP). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications de- manding the highest level of performance and reliability. 2674 drw 02 OE I/O2 I/O3 I/O6 P1 VCC GND I/O2 I/O5 OE 77 74 72 69 68 65 63 60 83 78 76 73 70 67 64 61 5984 56 8687 8890 9192 9495 9796 100 99 103 101 105 104 31 34 35 37 39 40 44 43 48 46 52 49 55 51 IDT7052G G108(4) 108-Pin PGA Top View(5) A B C D E F G H J K L M 81 57 54 82 79 75 71 66 62 58 50 R/W NC NC R/W BUSY BUSY CE CEA1 3 6 9 11 14 15 18 20 23 29 30 26 27 102 106 107 108 NC GND VCC CE OE I/O0 R/W BUSY I/O1 VCC V CC V CC GND I/O6 I/O4 I/O7 I/O0 I/O2 I/O4 I/O6 I/O1 I/O3 I/O5 I/O7 I/O3 I/O4 I/O5 NC I/O1 I/O3 I/O5 I/O7 I/O0 I/O2 I/O4 I/O6 I/O0 I/O1 GND A 7 A 8 NC A 9 OE R/W GND I/O 7 BUSY GND CE A A10 A10 A10 INDEX
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) NOTES: 1. All V CC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. PN120-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2674 drw 04 7052 PN120(4) CEP1 N/C A2P1 A3P1 A4P1 BUSYP1 I/O0P1 I/O1P1 I/O2P1 I/O3P1 N/C N/C OEP2 BUSYP2 A9P1 A0P1 A1P1 R/WP1 A8P1 A5P1 A6P1 A10P1 VCC A7P1 OEP1 GND I/O4P1 N/C I/O5P1 N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2425 26 27 28 29 30 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 7372 71 70 69 68 6766 65 64 63 62 61 CEP4 N/C A2P4 A3P4 A4P4 BUSYP4 I/O7P4 I/O6P4 I/O5P4 I/O4P4 N/C N/C BUSYP3 A9P4 A0P4 A1P4 R/WP4 A8P4 A5P4 A6P4 A10P4 GND A7P4 OEP4 GND I/O3P4 N/C I/O2P4 N/C GND I/O2P2 I/O3P2 I/O4P2 I/O5P3 I/O6P3 I/O7P3 I/O0P4 N/C I/O6P1 N/C I/O2P3 I/O0P2 I/O1P2 I/O1P3 I/O5P2 I/O6P2 I/O7P2 VCC I/O0P3 GND I/O1P4 N/C VCC GND N/C I/O3P3 I/O4P3 VCC I/O7P1 R/WP3 CEP3 OEP3 N/C A9P3 A8P3 A7P3 A10P3 A6P3 A5P3 A4P3 A3P3 A2P3 A1P3 A0P3 N/C A0P2 A1P2 A2P2 A4P2 A3P2 A5P2 A6P2 A7P2 A10P2 A8P2 A9P2 N/C R/WP2 CEP2 VCC INDEX
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2) NOTES: 1. All V CC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply Absolute Maximum Ratings(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > VCC + 10%. Capacitance(1) (TA = +25°C, f = 1.0MHz) TQFP only NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. Maximum Operating Temperature and Supply Voltage(1) Recommended DC Operating Conditions NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. NOTE: 1. This is the parameter T A. This is the "instant on" case temperature. Symbol Pin Name A0 P1 - A 10 P1 Address Lines - Port 1 A0 P2 - A 10P2 Address Lines - Port 2 A0 P3 - A 10 P3 Address Lines - Port 3 A0 P4 - A 10 P4 Address Lines - Port 4 I/O0 P1 - I/O7 P1 Data I/O - Port 1 I/O0 P2 - I/O7 P2 Data I/O - Port 2 I/O0 P3 - I/O7 P3 Data I/O - Port 3 I/O0 P4 - I/O7 P4 Data I/O - Port 4 R/W P1 Read/Write - Port 1 R/W P2 Read/Write - Port 2 R/W P3 Read/Write - Port 3 R/W P4 Read/Write - Port 4 GND Ground CE P1 Chip Enable - Port 1 CE P2 Chip Enable - Port 2 CE P3 Chip Enable - Port 3 CE P4 Chip Enable - Port 4 OE P1 Output Enab le - Port 1 OE P2 Output Enab le - Port 2 OE P3 Output Enab le - Port 3 OE P4 Output Enab le - Port 4 BUSY P1 Write Disable - Port 1 BUSY P2 Write Disable - Port 2 BUSY P3 Write Disable - Port 3 BUSY P4 Write Disable - Port 4 V CC Power 2674 tbl 01 Symbol Rating Commercial & Industrial Military Unit VTERM(2) Terminal Voltage with Respect to GND TBIAS Temperature Under Bias -55 to +125 -65 to +135 oC TST G Storage Temperature -65 to +150 -65 to +150 oC IOUT DC Output Current 50 50 mA 2674 tbl 02 Grade Ambient Temperature GND Vcc Military -55 OC to+125OC0 V 5 . 0 V + 10% Commercial 0 OC to +70OC0 V 5 . 0 V + 10% Industrial -40 OC to +85OC0 V 5 . 0 V + 10% 2674 tbl 04 Symbol Parameter Conditions (2) Max. Unit CIN Input Capacitance V IN = 0V 9 pF COUT Output Capacitance V OUT = 0V 10 pF 2674 tbl 03 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(2) V VIL Input Low Voltage -0.5 (1) ____ 0.8 V 2674 tbl 05
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges NOTES: 1. 'X' in part number indicates power rating (S or L). 2. V CC = 5V, T A = +25°C and are not production tested. 3. f = 0 means no address or control lines change. 4. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) NOTE: 1. At Vcc < 2.0V input leakages are undefined. Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%) Symbol Parameter Condition 7052X20 Com'l Only 7052X25 Com'l, Ind & Military 7052X35 Com'l & Military ICC1 Operating Power Supply Current (All Ports Active) CE = V IL Outputs Disabled f = 0(3) COM'L. S L 150 150 300 250 150 150 300 250 150 150 300 250 mA MIL. & IND. S L ____ ____ ____ ____ 150 150 360 300 150 150 360 300 ICC2 Dynamic Operating Current (All Ports Active) CE = V IL Outputs Disabled f = fMAX(4) COM'L. S L 240 210 370 325 225 195 350 305 210 180 335 290 mA MIL. & IND. S L ____ ____ ____ ____ 225 195 400 340 210 180 395 330 ISB Standby Current (All Ports - TTL Level Inputs) CE = V IH f = fMAX(4) COM'L. S L mA MIL. & IND. S L ____ ____ ____ ____ 115 110 ISB1 Full Standby Current (All Ports - All CMOS Level Inputs) All Ports CE > VCC - 0.2V VIN > VCC - 0.2V or COM'L. S L 1.5 0.3 1.5 1.5 0.3 1.5 1.5 0.3 1.5 mA MIL. & IND. S L ____ ____ ____ ____ 1.5 0.3 4.5 1.5 0.3 4.5 2674 tbl 06 Symbol Parameter Test Conditions 7052S 7052L UnitMin. Max. Min. Max. |ILI| Input Leakage Current (1) VCC = 5.5V, V IN = 0V to V CC ___ 10 ___ 5µ A |ILO| Output Leakage Current CE = V IH, VOUT = 0V to V CC ___ 10 ___ 5µ A VOL Output Low Voltage I OL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ 2.4 ___ V 2674 tbl 07
- This parameter is guaranteed but not production tested.
- Industrial temperature: For other speeds, packages and powers contact your sales office.
Figure 1. AC Output Test Load Figure 2. Output Test Load
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges 2674 drw 08 tAOE tLZ tHZ DATAOUT CE tACE VALID DATA OE CURRENT ICC ISB tPU 50% tLZ tPD 50% tHZ 2674 drw 07 tAA tOH tOH DATAOUT ADDRESS tRC DATA VALIDPREVIOUS DATA VALID Timing Waveform of Read Cycle No. 1, Any Port(1) Operating Temperature and Supply Voltage(3) NOTES: 1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2) 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L) Timing Waveform of Read Cycle No. 2, Any Port(1,2) NOTE: 1. R/ W = V IH, OE = V IL and CE = V IL. NOTES: 1. R/ W = V IH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW. 7052X20 Com'l Only 7052X25 Com'l, Ind & Military 7052X35 Com'l & Military READ CYCLE tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 20 ____ 25 ____ 35 ns 2674 tbl 09
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage(7) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off data to be placed on the bus for the required t DW. If OE = V IH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. Specified for OE = V IH (refer to “Timing Waveform of Write Cycle”, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four port s and Port "B" is any other port. 6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports a nd Port "B" is any other port. 7. 'X' in part number indicates power rating. 7052X20 Com'l Only 7052X25 Com'l & Military 7052X35 Com'l & Military WRITE CYCLE tEW Chip Enable to End-of-Write (3 ) 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 12 ____ 15 ____ 15 ns tOW Output Active from End-of-Write (1,2) 0 ____ 0 ____ 0 ____ ns tWDD Write Pulse to Data Delay (4) ____ 35 ____ 45 ____ 55 ns tWDD Write Data Valid to Read Data Delay (4) ____ 30 ____ 35 ____ 45 ns BUSY INPUT TIMING 2674 tbl 10
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8) Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5) NOTES: 1. R/ W or CE = V IH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a CE = V IL and a R/ W = V IL. 3. t WR is measured from the earlier of CE or R/ W = V IH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/ W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guarant eed but is not production tested. 8. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required t DW. If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. CE 2674 drw 09 tAW tAS tWR tDW DATAIN ADDRESS tWC R/W tWP DATAOUT tWZ (7) (4) (4) (2) tOW OE tHZtLZ (7) tHZ (6) (3) (9) tDH (7) CE 2674 drw 10 tAW tAS tWR tDW DATAIN ADDRESS tWC R/W tEW tDH (9) (6) (2) (3)
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read(1,2,3) Functional Description The IDT7052 provides four ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = V IH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. READ/ WRITE conditions are illustrated in the table below. Timing Waveform of Write with BUSY Input NOTE: 1. BUSY is asserted on Port "B" blocking R/ W"B" until BUSY"B" goes HIGH. Truth Table I – Read/Write Control(3) NOTES: 1. "H" = V IH, "L" = V IL, "X" = Don’t Care, "Z "= High Impedance 2. If BUSY = V IL, write is blocked. 3. For valid write operation, no more than one port can write to the same address location at the same time. NOTES: 1. Assume BUSY input = V IH and CE = V IL for the writing port. 2. OE = V IL for the reading ports. 3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port. 2674 drw 11 ADDR"A" tWC DATA"B" MATCH tWP R/W"A" DATAIN"A" ADDR"B" tDH VALID MATCH VALID tDDD tWDD tDW 2674 drw 12 R/W"A" BUSY"B" tWP tWH tWB R/W"B" (1) Any Port(1 ) R/W CE OE D0-7 Function X H X Z Port Deselected: Power-Down XHX Z CEP1=CEP2=CEP3=CEP4=VIH Power Down Mode I SB or I SB1 LLX D A T A IN Data on port written into memory (2) HL L D A T A OU T Data in memory output on port XXH Z O u t p u t s D i s a b l e d 2674 tbl 11
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
Ordering Information
Datasheet Document History 1/18/99: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations 6/4/99: Changed drawing format Page1 Corrected DSC number 11/10/99: Replaced IDT logo 11/18/99: Page 10 Fixed typo in caption for BUSY Input waveform 5/23/00: Page 4 Increased storage temperature parameter Clarified T A parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes 10/22/01: Pages 2 & 3 Added date revision for pin configurations Page 5, 7 & 8 Added Industrial temp to column heading for 25ns speed to DC & AC Electrical Characteristics Page 11 Added Industrial temp offering to 25ns ordering information Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables Page 1 & 11 Replace TM logo with ® logo 07/24/06: Page 1 Added green availability to features Page 11 Added green indicator to ordering information 01/19/09: Page 11 Removed "IDT" from orderable part number 02/05/15: Page 2 Removed IDT in reference to fabrication Page 2,3 & 11The package codes G108-1 & PN120-1changed to G108 & PN120 respectively to match standard package codes Page 11 Added Tape and Reel to Ordering Information Page 1&3Removed 132-pin PQF offering from the Features & the pin configuration Page 11 Removed the 132-pin PQF package from the Ordering Information NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office.
6.42 IDT7052S/L High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges The IDT logo is a registered trademark of Integrated Device Technology, Inc. CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 D ualPortHelp@idt.com www.idt.com Datasheet Document History (con't) 07/08/16: Page 3 Changed diagram for the PN120 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Added the IDT logo to the PN120 pin configurations and changed the text to be in alignment with new diagram marking specs and removed the date revision indicator from all pin configurations Updated footnote references for PN120 pin configuration by removing footnote 4 & 5