7035S15PFG8

IDT7035S_18 IDT | Alldatasheet

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Features

◆ ◆◆ ◆◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆◆ ◆◆ High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) ◆ ◆◆ ◆◆ Low-power operation – IDT7035S Active: 800mW (typ.) Standby: 5mW (typ.) – IDT7035L Active: 800mW (typ.) Standby: 1mW (typ.) ◆ ◆◆ ◆◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆◆ ◆◆ IDT7035 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device ◆ ◆◆ ◆◆ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave ◆ ◆◆ ◆◆ On-chip port arbitration logic ◆ ◆◆ ◆◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆◆ ◆◆ Fully asynchronous operation from either port ◆ ◆◆ ◆◆ Battery backup operation—2V data retention ◆ ◆◆ ◆◆ TTL-compatible, single 5V (±10%) power supply ◆ ◆◆ ◆◆ Available in 100-pin Thin Quad Flatpack Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆◆ ◆◆ Green parts available. See ordering information Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ra nges

Description

The IDT7035 is a high-speed 8K x 18 Dual-Port Static RAM. The IDT7035 is designed to be used as a stand-alone 144K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT7035 utilizes a 18-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/ reception error checking. Fabricated using CMOS high-performance technology, these de- vices typically operate on only 800mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consump- tion of 500µW from a 2V battery. Pin Configurations(1,2,3) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Index 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 IDT7035PF PN100 (4) 100-Pin TQFP Top View(5) N/C N/C I/O I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L VCC GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R I/O6R I/O8R I/O17R N/C N/C 4088 drw 02 N/C N/C N/C N/C A A4L A3L A2L A1L A0L INTL GND M/S BUSY R INTR A0R N/C N/C N/C N/C BUSY L A1R A2R A3R A4R I/O 10L I/O I/O I/O I/O I/O I/O I/O GND I/O I/O OEL VCC R/W L SEM L CE L UB L LBL A 11L A 10L A A A A I/O I/O I/O 10R I/O 11R I/O 12R I/O 13R I/O 14R I/O 15R GND I/O 16R OE R R/W R SEM R CE R UB R LB R GND A 11R A 10R A A A A A A12L A 12R

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Truth Table I: Non-Contention Read/Write Control NOTE: 1. A 0L — A 12L ≠ A0R — A 12R Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 12L A0R - A 12R Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 4088 tbl 01 Inputs(1 ) Outputs ModeCE R/W OE UB LB SEM I/O9-17 I/O0-8 H X X X X H High-Z High-Z Deselected: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected LLXLH H D ATAIN High-Z Write to Upper Byte Only LLXHLH H igh-Z D ATAIN Write to Lower Byte Only LLXLLH D ATAIN DAT AIN Write to Both Bytes LHLLHH D ATAOUT High-Z Read Upper Byte Only LHLHLH H igh-Z D ATAOUT Read Lower Byte Only LHLLLH D ATAOUT DAT AOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 4088 tbl 02

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ra nges Recommended DC Operating Conditions Maximum Operating Temperature and Supply Voltage (1) Capacitance (TA = +25°C, f = 1.0MHz) (1) Absolute Maximum Ratings (1) NOTE: 1. There are eight semaphore flags written to via I/O 0 and read from I/O 0 - I/O 17. These eight semaphores are addressed by A 0 - A 2. Truth Table II: Semaphore Read/Write Control(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20 mA for the period over V TERM > Vcc + 10%. NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. NOTES: 1. This parameter is determined by device characterization but is not production tested. For TQFP Package Only. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. Inputs Outputs ModeCE R/W OE UB LB SEM I/O9-17 I/O0-8 HHLXX L D ATAOUT DATAOUT Read Data in Semaphore Flag XHLHHL D ATAOUT DATAOUT Read Data in Semaphore Flag H ↑ XXXL D ATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ XHHL D ATAIN DATAIN Write I/O0 into Semaphore Flag 4088 tbl 03 Symbol Rating Commercial & Industrial Unit VTERM(2) T erminal Voltage with Respect to GND -0.5 to +7.0 V T BI AS T emperature Under Bias -55 to +125 oC TST G Storage T emperature -65 to +150 oC IOUT DC Output Current 50 mA 4088 tbl 04 Grade Ambient Temperature GND Vcc Commercial 0 OC to +70OC0 V 5 .0V + 10% Industrial -40 OC to +85OC0 V 5 .0V + 10% 4088 tbl 05 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(2 ) V VIL Input Low Voltage -0.5 (1 ) ____ 0.8 V 4088 tbl 06 Symbol Parameter Conditions (2 ) Max. Unit CIN Input Capacitance V IN = 3dV 9 pF COUT Output Capacitance V OUT = 3dV 10 pF 4088 tbl 07

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) NOTE: 1. At Vcc < 2.0V input leakages are undefined. Temperature and Supply Volta ge Range (1) (VCC = 5.0V ± 10%) NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. V CC = 5V, T A = +25°C, and are not production tested. Icc dc = 120mA (TYP) 3. At f = f MAX , address and I/O' S are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". Symbol Parameter Test Conditions 7035S 7035L UnitMin. Max. Min. Max. |ILI| Input Leakage Current (1) VCC = 5.5V, V IN = 0V to V CC ___ 10 ___ 5µ A |ILO| Output Leakage Current CE = V IH, VOUT = 0V to V CC ___ 10 ___ 5µ A VOL Output Low Voltage I OL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ 2.4 ___ V 4088 tbl 08 Symbol Parameter Test Condition Version 7035X15 Com'l Only Typ.(2) Max. 7035X20 Com'l & Ind Typ.(2) Max. Unit ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = fMAX(3) COM'L S L 170 170 310 260 160 160 290 240 mA IND S L ____ ____ ____ ____ 160 160 370 320 I SB1 Standby Current (Both Ports - TTL Level Inputs) CE L = CER = V IH SEMR = SEML = V IH f = fMAX(3) COM'L S L mA IND S L ____ ____ ____ ____ I SB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=f MAX(3) SEMR = SEML = V IH COM'L S L 105 105 190 160 180 150 mA IND S L ____ ____ ____ ____ 240 210 I SB3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CE L and CER > VCC - 0.2V VIN > VCC - 0.2V or SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 1.0 0.2 mA IND S L ____ ____ ____ ____ 1.0 0.2 ISB4 Full Standby Current (One Port - All CMOS Level Inputs) CE "A" < 0.2V and CE"B" > VCC - 0.2V (5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = f MAX(3) COM'L S L 100 100 170 140 155 130 mA IND S L ____ ____ ____ ____ 225 200 4088 tbl 09

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges tRC R/W CE ADDR tAA OE UB,LB 4088 drw 05 (4) tACE (4) tAOE (4) tABE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATA OUT BUSYOUT VALID DATA (4) Operating Temperature and Supply Voltage Range (4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = V IL, UB or LB = V IL, and SEM = V IH. To access semaphore, CE = V IH or UB & LB = V IH, and SEM = V IL. 4. 'X' in part numbers indicates power rating (S or L). NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. t BDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or t BDD. 5. SEM = V IH. Waveform of Read Cycles (5) 7035X15 Com'l Only 7035X20 Com'l & Ind UnitSymbol P arameter M in.M ax.M in.M ax. READ CYCLE tAA Address Access T ime ____ 15 ____ 20 ns tACE Chip Enable Access Time (3 ) ____ 15 ____ 20 ns tABE Byte Enable Access Time (3 ) ____ 15 ____ 20 ns tAOE Output Enable Access Time ____ 10 ____ 12 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 12 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ ns tPD Chi p Disable to Power Down Time (2) ____ 15 ____ 20 ns tSOP Semaphore Flag Update Pulse (OE or SEM)(3) 10 ____ 10 ____ ns tSAA Semaphore Address Access T ime (3) ____ 15 ____ 20 ns 4088 tbl 12

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ra nges Operating Temperature and Supply Volta ge(5) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = V IL, UB or LB = V IL, SEM = V IH. To access semaphore, CE = V IH or UB & LB = V IH, and SEM = V IL. Either condition must be valid for the entire tEW time. 4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW. 5. 'X' in part numbers indicates power rating (S or L). Timing of Pow er-Up Pow er-Dow n CE 4088 drw 06 tPU ICC ISB tPD 50% 50% Symbol Parameter 7035X15 Com'l Only 7035X20 Com'l & Ind UnitMin. Max. Min. Max. WRITE CYCLE t tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ ns tWP Write Pulse Width 12 ____ 15 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 12 ns tWZ Write Enable to Output in High-Z (1,2) ____ 10 ____ 12 ns tOW Output Active from End-of-Write (1 , 2 ,4 ) 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ ns 4088 tbl 13

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) NOTES: 1. R/ W or CE or UB & LB must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a LOW UB or LB and a LOW CE and a LOW R/ W for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W) going HIGH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the high-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/ W, or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load (Figure 2). 8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. 9. To access RAM, CE = V IL, UB or LB = VIL, and SEM = V IH. To access semaphore, CE = V IH or UB & LB = VIH, and SEM = V IL. tEW must be met for either condition. R/W tWC tHZ tAW tWRtAS tWP DATA OUT (2) tWZ tDW tDH tOW OE ADDRESS DATA IN (6) (4) (4) (7) UB orLB 4088 drw 07 (9) CE orSEM (9) (7) (3) 4088 drw 08 tWC tAS tWR tDW tDH ADDRESS DATA IN R/W tAW tEW UB orLB (3)(2)(6) CE orSEM (9) (9)

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ra nges Timing Waveform of Sema phore Read after Write Timin g, Either Side(1) NOTES: 1. CE = V IH or UB & LB = V IH for the duration of the above timing (both write and read cycle). 2. "DATA OUT VALID' represents all I/Os (I/O 0-I/O17) equal to the semaphore value. NOTES: 1. D OR = D OL = V IL, CER = CEL = V IH, or both UB & LB = V IH. 2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/ W"A" or SEM"A" going HIGH to R/ W"B" or SEM"B" going HIGH. 4. If t SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. Timing Waveform of Semaphore Write Contention (1,3,4) SEM 4088 drw 09 tAW tEW tSOP DATA 0 VALID ADDRESS tSAA R/W tWR tOH tACE VALID ADDRESS DATA IN VALID DATA OUT tDW tWP tDHtAS tSWRD tAOE tSOP Read CycleWrite Cycle A0 -A2 OE VALID(2) SEM"A" 4088 drw 10 tSPS MATCH R/W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/W"B" A0"B"-A2"B" SIDE (2) "B"

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = V IH)" or "Timing Waveform of Write with Port-To-Port Delay (M/ S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0ns, t WDD – t WP (actual) or t DDD – t DW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention with Port "A". 6. 'X' in part numbers indicates power rating (S or L). Operating Temperature and Supply Voltage Range (6) Symbol Parameter 7035X15 Com'l Only 7035X20 Com'l & Ind UnitMin. Max. Min. Max. BUSY TIMING (M/ S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ns tBDA BUSY Disable T ime from Address Not Matched ____ 15 ____ 20 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 15 ____ 20 ns tBDC BUSY Access Time from Chip Enable High ____ 15 ____ 17 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (3) ____ 18 ____ 30 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns BUSY TIMING (M/ S=VIL) tWB BUSY Input to Write (4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 30 ____ 45 ns tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 30 ns 4088 tbl 14

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ra nges Timing Waveform of Write Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4) Timing Waveform of Write w ith BUSY NOTES: 1. t WH must be met for both BUSY input (slave) output master. 2. BUSY is asserted on port "B" Blocking R/ W"B", until BUSY"B" goes HIGH 3. t WB is only for the 'Slave' Version . NOTES: 1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (slave). 2. CEL = CER = V IL. 3. OE = V IL for the reading port. 4. If M/ S = V IL (SLAVE) then BUSY is an input BUSY"A" = V IL and BUSY"B" = "don't care." 5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A". 4088 drw 11 tDW tAPS ADDR "A" tWC DATA OUT "B" MATCH tWP R/W"A" DATA IN "A" ADDR "B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD tBAA 4088 drw 12 R/W"A" BUSY"B" tWP tWB R/W"B" tWH (1) (2) (3)

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Operating Temperature and Supply VoltageRange (1) Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) NOTE: 1. 'X' in part numbers indicates power rating (S or L). Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (1) (M/S = VIH) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 4088 drw 13 ADDR "A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 4088 drw 14 ADDR "A" ADDRESS "N" ADDR "B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" Symbol Parameter 7035X15 Com'l Only 7035X20 Com'l & Ind UnitMin. Max. Min. Max. INTERRUPT TIMING tAS Address Set-up T ime 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 20 ns 4088 tbl 15

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ra nges Waveform of Interrupt Timing (1) Truth Table III — Interrupt Flag(1,2) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Flag Truth Table III. 3. Timing depends on which enable signal ( CE or R/ W) is asserted last. 4. Timing depends on which enable signal ( CE or R/ W) is de-asserted first. NOTES: 1. Assumes BUSYL = BUSYR = V IH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = V IL, then no change. 4. INTR and INTL must be initialized at power-up. 4088 drw 15 ADDR "A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR(3) (4) tINS (3) INT"B" (2) 4088 drw 16 ADDR "B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR (3) INT"B" (2) Left Port Right Port FunctionR/WL CEL OEL A0L-A12L IN TL R/WR CER OER A0R-A12R INTR LLX 1 FFF XXXX X L (2 ) Set Right INTR Flag X X XXX X L L 1 FFF H (3) Reset Right INTR Flag XXX X L (3) L L X 1FFE X Set Left INTL Flag X L L 1FFE H (2) X X X X X Reset Left INTL Flag 4088 tbl 16

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT7035 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7035 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX), where a write is defined as the CER = R/WR = VIL per Truth Table III. The left port clears the interrupt by an address location 1FFE access when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 1FFF, The message (18 bits) at 1FFE or 1FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Truth Table V — Example of Semaphore Procurement Seq uence (1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7035. 2. There are eight semaphore flags written to via I/O 0 and read from all I/0's. These eight semaphores are addressed by A 0 - A 2. 3. CE = V IH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7035 are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If t APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Inputs Outputs FunctionCEL CER AOL-A12L AOR-A12R BUSYL(1) BUSYR(1) X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit (3) 4088 tbl 17 Functions D 0 - D17 Left D 0 - D17 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore t oken Left Port Writes "0" to Semaphore 1 0 No change. Left port has no wri te access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphor e token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore to ken Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 4088 tbl 1 8

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7035 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simulta- neous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7035’s Dual-Port RAM. Say the 8K x 18 RAM was to be divided into two 4K x 18 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task was successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port RAM with each other.

given a common meaning as was shown in the example above. their assigned portions of memory continuously without any wait states. Figure 4. IDT7035 Semaphore Logic

0 D Q

thereby guaranteeing a consistent data structure.

6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to + 85°C) PF 100-pin TQFP (PN100) Commercial Only Commercial & Industrial S L Standard Power Low Power XXXXX Device Type 144K (8K x 18) Dual-Port RAM7035 Speed in nanoseconds G (2) Green Blank Tube or Tray Tape and Reel A A The IDT logo is a registered trademark of Integrated Device Technology, Inc. Datasheet Document History 01/18/99: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations 05/19/99: Page 9 Fixed typographical error 06/04/99: Changed drawing format Page 1 Corrected DSC number 09/01/99: Removed Preliminary 10/04/99: Added Industrial Temperature Ranges and removed corresponding notes 11/10/99: Replaced IDT logo 05/23/00: Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±500mV to 0mV in notes 08/20/01: Page 14 Corrected note superscript in Truth Table III 01/29/09: Page 19 Removed "IDT" from orderable part number 06/05/15: Page 1 Added Green availability to Features Page 2 Removed IDT in reference to fabrication Page 2 & 19 The package code for PN100-1 changed to PN100 to match the standard package codes Page 19 Added Green and T&R indicators and the correlating footnotes to Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available . For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 05/25/18: