7016L35PFGB

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◆ True Dual-Ported memory cells which allow simulta- neous reads of the same memory location ◆ High-speed access – Commercial:12/15/20/25/35ns (max.) – Industrial: 20ns (max.) – Military: 20/25/35ns (max.) ◆ Low-power operation – IDT7016S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7016L Active: 750mW (typ.) Standby: 1mW (typ.) HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM IDT7016S/L NOTES: 1. In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DescriptionDescriptionDescriptionDescriptionDescription The IDT7016 is a high-speed 16K x 9 Dual-Port Static RAM. The IDT7016 is designed to be used as stand-alone Dual-Port RAMs or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or- more wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in full-speed, error-free operation without the need for addi- tional discrete logic. This device provides two independent ports with separate con- trol, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7016 is packaged in a ceramic 68-pin PGA, a 64-pin PLCC and an 80-pinTQFP (Thin Quad Flatpack). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military tempera- ture applications demanding the highest level of performance and reliability. Pin Configurations (1,2,3) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 4. This package code is used to reference the package diagram. 5. This text does not imply orientation of Part-marking. Pin Names Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13 L A0R - A 13R Address I/O0L - I/O8L I/O0R - I/O8R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3190 tbl 01

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations (1,2,3) (con't.) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm. G68-1 package body is approximately 1.18 in x 1.18 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Recommended DC Operating Conditions Maximum Operating Temperature and Supply Volt- age (1) Truth Table II: Semaphore Read/Write Control (1) Absolute Maximum Ratings (1) Truth Table I: Non-Contention Read/Write Control NOTE: 1. There are eight semaphore flags written to via I/O 0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2. NOTE: 1. Condition: A 0L — A 13L ≠ A0R — A 13R NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. Inputs(1 ) Outputs ModeCE R/W OE SEM I/O0-8 H X X H High-Z Deselct ed: Power-Down LLXH D A T A IN Write to Memory LHLH D A T A OUT Read Memory X X H X High-Z Outputs Disabled 319 0 tbl 0 2 Inputs Outputs ModeCE R/W OE SEM I/O0-8 HHL L D A T A OUT Read Semaphore Flag Data Out (I/O 0 - I/O8) H ↑ XL D A T A IN Write I/O0 into Semaphore Flag LXXL ____ Not Allowed 3190 tbl 0 3 Symbol Rating Commercial & Industrial Military Unit VTE RM(2) Terminal Voltage with Respect to GND T BI AS Temperature Under Bias -55 to +125 -65 to +135 oC TST G Storage Temperature -65 to +150 -65 to +150 oC IOUT DC Output Current 50 50 mA 3190 tbl 0 4 Grade Ambient Temperature GND Vcc Military -55 OC to +125OC0 V5 . 0 V + 10% Commercial 0 OC to +70OC0 V 5 . 0 V + 10% Industrial -40 OC to +85OC0 V 5 . 0 V + 10% 3190 tbl 05 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(2 ) V VIL Input Low Voltage -0.5 (1 ) ____ 0.8 V 319 0 tbl 0 6

At Vcc < 2.0V, Input leakages are undefined.
This parameter is determined by device characteristics but is not production tested.
3dV references the interpolated capacitance when the input and output signals switch

from 0V to 3V or from 3V to 0V . Figure 1. AC Output Test Load Figure 2. Output Test Load

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range (1) (con't.) (VCC = 5.0V ± 10%) NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. V CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.) 3. At f = f MAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 7016X12 Com'l Only 7016X15 Com'l Only Symbol Parameter Test Condition Version Typ. (2) Max. Typ. (2 ) Max. Unit ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SE M = V IH f = fMAX(3 ) COM'L S L 170 170 325 275 170 170 310 260 mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ ISB1 Standby Current (Both Ports - TTL Level Inputs) CER = CEL = V IH SE MR = SEML = V IH f = fMAX(3 ) COM'L S L mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ ISB 2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = V IH(5) Active Port Outputs Disabled, f=fMAX(3) SE MR = SE ML = V IH COM'L S L 105 105 200 170 105 105 190 160 mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ ISB 3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CE L and CER > VCC - 0.2V VIN > V CC - 0.2V or SE MR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 1.0 0.2 mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ ISB 4 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V (5 ) SE MR = SEML > VCC - 0.2V VIN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3 ) COM'L S L 100 100 180 150 100 100 170 140 mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 3190 tbl 10 7016X20 Com'l, Ind & Military 7016X25 Com'l & Military 7016X35 Com'l & Military ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = fMAX(3) COM'L S L 160 160 290 240 155 155 265 220 150 150 250 210 mA MIL & IND S L 160 160 380 310 155 155 340 280 150 150 300 250 ISB1 Standby Current (Both Ports - TTL Level Inputs) CER = CEL = V IH SEMR = SEML = V IH f = fMAX(3) COM'L S L mA MIL & IND S L ISB 2 Standby Current (One Port - TTL Level Inputs) CE"A " = V IL and CE"B" = V IH(5 ) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = V IH COM'L S L 180 150 170 140 155 130 mA MIL & IND S L 240 210 215 180 190 160 ISB 3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 1.0 0.2 1.0 0.2 mA MIL & IND S L 1.0 0.2 1.0 0.2 1.0 0.2 ISB 4 Full Standby Current (One Po rt - All CMOS Level Inputs) CE"A " < 0.2V and CE"B " > VCC - 0.2V (5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 155 130 145 120 135 110 mA MIL & IND S L 230 200 200 170 175 150 3190 tbl 11

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range (4) NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 7016X12 Com'l Only 7016X15 Com'l Only UnitSymbol Parameter Min. Max. Min. Max. READ CYCLE tAA Address Access Time ____ 12 ____ 15 ns tACE Chip Enable Access Time (3 ) ____ 12 ____ 15 ns tAO E Output Enable Access Time ____ 8 ____ 10 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Lo w-Z Time(1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 10 ns tPU Chip Enable to Power Up Time (2 ) 0 ____ 0 ____ ns tPD Chip Disable t o Power Down Time (2 ) ____ 12 ____ 15 ns tSO P Semaphore Flag Update Pulse ( OE or SEM)1 0 ____ 10 ____ ns tSA A Semaphore Address Access Time ____ 12 ____ 15 ns 3190 tb l 12a 7016X20 Com'l, Ind & Military 7016X25 Com'l & Military 7016X35 Com'l & Military READ CYCLE tACE Chip Enable Access Time (3 ) ____ 20 ____ 25 ____ 35 ns tPU Chip Enable to Power Up Time (2 ) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2 ) ____ 20 ____ 25 ____ 35 ns tSO P Semaphore Flag Update Pulse ( OE or SEM)1 0 ____ 10 ____ 10 ____ ns tSA A Semaphore Address Access Time ____ 20 ____ 25 ____ 35 ns 3190 tbl 12b

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges tRC R/W CE ADDR tAA OE 3190 drw 07 (4) tACE (4) tAOE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATAOUT BUSYOUT VALID DATA (4) Waveform of Read Cycles (5) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE. 3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up / Power-Down CE 3190 drw 08 tPU ICC ISB tPD 50% 50%

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). Operating Temperature and Supply Voltage (5) Symbol Parameter 7016X12 Com'l Only 7016X15 Com'l Only UnitMin. Max. Min. Max. WRITE CYCLE tEW Chip Enable to End-of-Write (3 ) 10 ____ 12 ____ ns tAW Address Valid to End-of-Write 10 ____ 12 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ ns tWP Writ e Pulse Widt h 10 ____ 12 ____ ns tWR Write Recovery Time 2 ____ 2 ____ ns tDW Data Valid to End-of-Write 10 ____ 10 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 10 ns tWZ Write Enable to Output in High-Z (1,2) ____ 10 ____ 10 ns tOW Output Active from End-of-Write (1 , 2 ,4 ) 3 ____ 3 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ ns tSP S SEM Flag Contention Window 5 ____ 5 ____ ns 3190 tb l 13a Symbol Parameter 7016X20 Com'l, Ind & Military 7016X25 Com'l & Military 7016X35 Com'l & Military WRITE CYCLE t tEW Chip Enable to End-of-Write (3 ) 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 12 ____ 15 ____ 20 ns tOW Output Active from End-of-Write (1 , 2 ,4 ) 3 ____ 3 ____ 3 ____ ns 3190 tbl 13b

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing(1,5,8) NOTES: 1. R/ W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) R/W tWC tHZ tAW tWRtAS tWP DATAOUT (2) tWZ tDW tDH tOW OE ADDRESS DATAIN CE or SEM (6) (4) (4) (3) 3190 drw 09 (7) (9) (7) tLZ 3190 drw 10 tWC tAS tWR tDW tDH ADDRESS DATAIN CE or SEM R/W tAW tEW (3)(2)(6) (9)

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTES: 1. D OR = DOL =VIH, CER = CEL =VIH. 2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/ W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If t SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. Timing Waveform of Semaphore Write Condition (1,3,4) NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. “DATA OUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value. SEM 3190 drw 11 tAW tSOP I/O VALID ADDRESS tSAA R/W tWR tOH tACE VALID ADDRESS DATAIN VALID DATAOUT tDW tDHtAS tAOE Read CycleWrite Cycle A0-A2 OE VALID(2) tSWRD tEW tWP SEM"A" 3190 drw 12 tSPS MATCH R/W"A" MATCH A0"A"-A2" A " SIDE "A" (2) SEM"B" R/W"B"SIDE "B" (2) A0"B"-A2" B "

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range (6) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention on Port "A". 6. 'X' in part numbers indicates power rating (S or L). 7016X12 Com'l Only 7016X15 Com'l Only Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (M/ S = V IH) tBA A BUSY Access T ime from Address Match ____ 12 ____ 15 ns tBDA BUSY Disable Time from Address Not Matched ____ 12 ____ 15 ns tBA C BUSY Access T ime from Chip Enable Low ____ 12 ____ 15 ns tBDC BUSY Disab le Time from Chip Enable High ____ 12 ____ 15 ns tAP S Arbitration Priority Set-up Time (2 ) 5 ____ 5 ____ ns tBDD BUSY Disable t o V alid Dat a(3 ) ____ 15 ____ 18 ns tWH Write Hold After BUSY(5 ) 11 ____ 13 ____ ns BUSY INPUT TIMING (M/ S = V IL) tWB BUSY Input to Write (4 ) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5 ) 11 ____ 13 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1 ) ____ 25 ____ 30 ns tDD D Write Data Valid to Read Data Delay (1) ____ 20 ____ 25 ns 3190 tbl 14a 7016X20 Com'l, Ind & Military 7016X25 Com'l & Military 7016X35 Com'l & Military BUSY TIMING (M/ S = V IH) tBA A BUSY Access T ime from Address Match ____ 20 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 20 ____ 20 ____ 20 ns tBA C BUSY Access T ime f rom Ch ip Ena ble L ow ____ 20 ____ 20 ____ 20 ns tBDC BUSY Disab le Time from Chip Enable High ____ 17 ____ 17 ____ 20 ns tAP S Arbitration Priority Set-up Time (2 ) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable t o V alid Dat a(3 ) ____ 30 ____ 30 ____ 35 ns BUSY INPUT TIMING (M/ S = V IL) PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1 ) ____ 45 ____ 50 ____ 60 ns tDD D Write Data Valid to Read Data Delay (1) ____ 30 ____ 35 ____ 45 ns 3190 tbl 14b

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 3190 drw 13 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD(3) tWDD Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) Timing Waveform of Write with BUSY(3) NOTES: 1. t WH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL. 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/ S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". 3190 drw 14 R/W"A" BUSY"B" tWP tWB R/W"B" tWH (1) (2)

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range (1) Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = V IH) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. NOTE: 1. 'X' in part numbers indicates power rating (S or L). 3190 drw 15 ADDR"A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 3190 drw 16 ADDR"A" ADDRESS "N" ADDR"B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" 7016X12 Com'l Only 7016X15 Com'l Only S y m b o l P a r a m e t e r M i n .M a x .M i n .M a x . U n i t INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 12 ____ 15 ns tINR Interrupt Reset Time ____ 12 ____ 15 ns 3190 tbl 15a 7016X20 Com'l, Ind & Military 7016X25 C om'l & Military 7016X35 Com'l & Military INTERRUPT TIMING 3190 tbl 15b

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing (1) Truth Table III — Interrupt Flag (1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt truth table. 3. Timing depends on which enable signal ( CE or R/W) is asserted last. 4. Timing depends on which enable signal ( CE or R/W) is de-asserted first. NOTES: 1. Assumes BUSY L = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 3190 drw 17 ADDR"A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR(3) (4) tINS (3) INT"B" (2) 3190 drw 18 ADDR"B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR (3) INT"B" (2) Left Port Right Port FunctionR/WL CEL OEL A13L-A0L INTL R/WR CER OER A13R-A0R INTR LLX 3 F F F XXXX X L (2) Set Right INTR Flag X X XXX X L L 3 F F F H (3) Reset Right INTR Flag XXX X L (3 ) L L X 3FFE X Set Left INTL Flag XLL 3 F F E H (2 ) X X X X X Reset Left INTL Flag 3190 tbl 16

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7016 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence (1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016. 2. There are eight semaphore flags written to via I/O 0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2. e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table. interrupt flag (INTL) is asserted when the right port writes to memory location 3FFE where a write is defined as the CE = R/W = VIL per Truth Table III. The left port clears the interrupt by an address location 3FFE access when CE R =OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFF and to clear the interrupt flag (INT R), the right port must access memory location 3FFF. The message (9 bits) at 3FFE or 3FFF is user-defined since it is in an addressable SRAM location. If the interrupt function is not used, address locations 3FFE and 3FFF are not used as mail boxes but are still part of the random access memory. Refer to Truth Table III for the interrupt opera- tion. Functional Description The IDT7016 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7016 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port Inputs Outputs FunctionCEL CER AOL-A13 L AOR-A13R BUSYL(1 ) BUSYR(1) X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit (3 ) 3190 tbl 17 Functions D 0 - D8 Left D 0 - D8 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 3190 tbl 18

Figure 3. Busy and chip enable routing for both width and depth expansion activity on the left port in no way slows the access time of the right port. shown in Truth Table I where CE and SEM are both HIGH. requiring complex programming. system designer total flexibility in system architecture. advantage in very high-speed systems. slave mode the BUSY pin operates solely as a write inhibit input pin. port by tying the BUSY pin for that port LOW. push-pull type outputs and do not require pull up resistors to operate. as a slave (M/ S pin = L) as shown in Figure 3. for the other part of the word. before the actual write pulse can be initiated with the R/ W signal. inhibit signal and corrupted data in the slave.

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/ WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4.Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if sema- phores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores-Some Examples Perhaps the simplest application of semaphores is their applica- tion as resource markers for the IDT7016’s Dual-Port RAM. Say the 16K x 9 RAM was to be divided into two 8K x 9 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8K. Meanwhile the right processor was attempt- resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7016 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/ W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A 0 – A 2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D 0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable ( OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the

Figure 4. IDT7016 Semaphore Logic

0 D Q

during a transfer and the I/O device cannot tolerate any wait states. tinuously without any wait states. assigned RAM segments at full speed. thereby guaranteeing a consistent data structure.

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History 01/11/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations 06/03/99 Changed drawing format Page 1 Corrected DSC number 11/10/99: Replaced IDT logo 05/19/00: Page 4 Increased storage temperature parameter Clarified T A parameter Page 6 DC Electrical parameters–changed wording from open to disabled Changed ±200mV to 0mV in notes 01/10/02: Pages 2 & 3 Added date revision for pin configurations Pages 4, 6, 7, 9 & 12 Removed Industrial temp footnote from all tables Pages 6, 7, 9, 12 & 14 Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics Page 20 Added Industrial temp offering to 20ns ordering information Pages 1 & 20 Replaced TM logo with ® logo 04/04/06: Page 1 Added green availability to features Page 20 Added indicator to ordering information 01/09/09: Page 20 Removed "IDT" from orderable part number

6.42 IDT7016S/L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. Datasheet Document History (con't) 10/03/14: Page 20 Added Tape and Reel to Ordering Information Page 2, 3, 4 & 20 The package codes PN80-1, G68-1 & J68-1 changed to PN80, G68 & J68 respectively to match standard package codes 10/10/14: Page 20 Corrected two typos

Summary

HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM

Description

HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM

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