IDT7015S_17 IDT | Alldatasheet
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©2017 Integrated Device Technology, Inc. OCTOBER 2017 DSC 2954/12 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/WL CEL OEL BUSYL A12L A0L 2954 drw 01 I/O0L-I / O8L CEL OEL R/WL SEML INTL M/S BUSYR I/O0R -I/O8R A12R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/WR CER OER R/WR 1313 Functional Block Diagram ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible, single 5V (±10%) power supply ◆ Available in 68-pin PLCC and an 80-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Features: ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial: 12/15/17/20/25/35ns (max.) – Industrial: 20ns (max.) ◆ Low-power operation – IDT7015S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7015L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ IDT7015 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM IDT7015S/L NOTES: 1. In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers. LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT7015 is a high-speed 8K x 9 Dual-Port Static RAM. The IDT7015 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18- bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for Pin Configurations(1,2,3) NOTES: 1. All V CC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 4. This package code is used to reference the package diagram. reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these de- vices typically operate on only 750mW of power. The IDT7015 is packaged in a 64-pin PLCC and an 80-pinTQFP (Thin Quad Flatpack). Pin Names Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 12L A0R - A 12R Address I/O0L - I/O8L I/O0R - I/O8R Data Input/Output SE ML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 2954 tbl 01 2954 drw 02 1213141516171819202122 VCC VCC I/O1R I/O2R I/O3R I/O4R INTL GND A4L A3L A2L A1L A0L A3R A0R A1R A2R I/O2L A5L R/WL 11 10 M/S 23242526 5857565554535251504948 59 6047464544 I/O3L GND I/O0R VCC A4R BUSYL GND BUSYR INTR A12R I/O7R I/O8R GND OER R/WR SEMR CER OEL SEML CEL I/O8L I/O0L I/O1L 7015 J68(4) I/O4L I/O5L I/O6L I/O7L I/O5R I/O6R N/C A12L N/C A11R N/C A10R A9R A8R A7R A6R A5R A11L A10L A9L A8L A7L A6L N/C
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges NOTES: 1. All Vcc must be connected to power supply. 2. All GND must be connected to ground supply. 3. PN80 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. Pin Configurations(1,2,3) (con't.) 7015 I/O2L GND GND A4R BUSYL BUSYR INTR INTL GND M/S NC VCC NC GND I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O8R A12R A11R A10R A9R A3R A2R A1R A0R A0L A1L A2L A3L A4L A6L A7L A8L A9L A10L A11L A12L I/O0L I/O6R I/O7R NC VCC A8R A7R A6R NC NC A5L NC I/O8L I/O1L 2954 drw 03 NC NC NC NC NC NC NC A5R NC NC NC SEMR SEML R/WL R/WROEL CEL CER OER PN80 (4) INDEX
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I: Non-Contention Read/Write Control Recommended DC Operating Conditions Maximum Operating Temperature and Supply Voltage(1) Absolute Maximum Ratings(1) Truth Table II: Semaphore Read/Write CONTROL(1) NOTE: 1. Condition: A 0L — A 12L = A0R — A 12R NOTE: 1. There are eight semaphore flags written to via I/O 0 and read from all I/O s (I/O0 - I/O 8). These eight semaphores are addressed by A 0 - A 2. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > Vcc + 10%. NOTES: 1. This is the parameter T A. There is the "instant on" case temperature. NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. Inputs(1) Outputs ModeCE R/W OE SEM I/O0-8 H X X H High-Z Deselected: Power-Down LLXHD A T A IN Write to Memory LHLH D A T A OUT Read Memory X X H X High-Z Outputs Disabled 2954 tbl 02 Inputs(1) Outputs ModeCE R/W OE SEM I/O0-8 HHL LD A T A OUT Read Semaphore Flag Data Out (I/O0-8) H ↑ XL D A T A IN Write I/O0 into Semaphore Flag LXXL ____ Not Allowed 2954 tbl 03 Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 oC TSTG Storage Temperature -65 to +150 oC IOUT DC Output Current 50 mA 2954 tbl 04 Grade Ambient Temperature GND Vcc Commercial 0 OC to +70 OC0 V 5 . 0 V + 10% Industrial -40 OC to +85 OC0 V 5 . 0 V + 10% 2954 tbl 05 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(2) V VIL Input Low Voltage -0.5 (1 ) ____ 0.8 V 295 4 tbl 06
- At Vcc < 2.0V, Input leakages are undefined.
- This parameter is determined by device characteristics but is not
- 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V . Figure 1. AC Output Test Load Figure 2. Output Test Load
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%) NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. V CC = 5V, T A = +25°C, and are not production tested. I CCDC = 120mA(typ.) 3. At f = f MAX, address and I/O' S are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite of port "A". 7015X12 Com'l Only 7015X15 Com'l Only 7015X17 Com'l Only ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = f MAX(3) COM'L S L 170 170 325 275 170 170 310 260 170 170 310 260 mA IND. S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ISB1 Standby Current (Both Ports - TTL Level Inputs) CE R = CEL = V IH SEMR = SEML = V IH f = f MAX(3) COM'L S L mA IND. S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = V IH(5), Active Port Outputs Disabled, f=f MAX(3) SEMR = SEML = V IH COM'L S L 105 105 200 170 105 105 190 160 105 109 190 160 mA IND. S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > V CC - 0.2V VIN > V CC - 0.2V or SEMR = SEML >VCC - 0.2V COM'L S L 1.0 0.2 1.0 0.2 1.0 0.2 mA IND. S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ISB4 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > V CC - 0.2V (5) SEMR = SEML >VCC - 0.2V VIN > V CC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = f MAX(3) COM'L S L 100 100 180 150 100 100 170 140 100 100 170 140 mA IND. S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 2954 tbl 10 7015X20 Com'l & Ind 7015X25 Com'l Only 7015X35 Com'l Only ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = f MAX(3) COM'L S L 160 160 290 240 155 155 265 220 150 150 250 210 mA IND. S L 160 160 380 310 ____ ____ ____ ____ ____ ____ ____ ____ ISB1 Standby Current (Both Ports - TTL Level Inputs) CE R = CEL = V IH SEMR = SEML = V IH f = f MAX(3) COM'L S L mA IND. S L ____ ____ ____ ____ ____ ____ ____ ____ ISB2 Standby Current (One Port - TTL Level Inputs) CE "A" = V IL and CE"B" = V IH(5), Active Port Outputs Disabled, f=f MAX(3) SEMR = SEML = V IH COM'L S L 180 150 170 140 155 130 mA IND. S L 240 210 ____ ____ ____ ____ ____ ____ ____ ____ ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CE L and CER > V CC - 0.2V VIN > V CC - 0.2V or SEMR = SEML >VCC - 0.2V COM'L S L 1.0 0.2 1.0 0.2 1.0 0.2 mA IND. S L 1.0 0.2 ____ ____ ____ ____ ____ ____ ____ ____ ISB4 Full Standby Current (One Port - All CMOS Level Inputs) CE "A" < 0.2V and CE"B" > V CC - 0.2V (5) SEMR = SEML >VCC - 0.2V VIN > V CC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = f MAX(3) COM'L S L 155 130 145 120 135 110 mA IND. S L 230 200 ____ ____ ____ ____ ____ ____ ____ ____ 2954 tbl 11
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with load (Figures 1 and 2). 2. This parameter is guaranteed by device characterization but not tested. 3. To access RAM, CE = V IL and SEM = V IH. To access semaphore, CE = V IH and SEM = V IL. 4. 'X' in part numbers indicates power rating (S or L). Operating Temperature and Supply Voltage Range(4) 7015X12 Com'l Only 7015X15 Com'l Only 7015X17 Com'l Only READ CYCLE tPU Chip Enable to Power Up Time (2 ) 0 ____ 0 ____ 0 ____ ns tPD Chi p Disable to Power Down Time (2) ____ 12 ____ 15 ____ 17 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)1 0 ____ 10 ____ 10 ____ ns tSAA Semaphore Address Access Time ____ 12 ____ 15 ____ 17 ns 2954 tbl 12a 7015X20 Com'l & Ind 7015X25 Com'l Only 7015X35 Com'l Only READ CYCLE tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 20 ____ 25 ____ 35 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)1 0 ____ 10 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 20 ____ 25 ____ 35 ns 2954 tbl 12b
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE. 3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simul taneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last t AOE, tACE, tAA or t BDD. 5. SEM = V IH. Timing of Power-Up / Power-Down tRC R/W CE ADDR tAA OE 2954 drw 07 (4) tACE (4) tAOE (4) (1) tLZ tOH (2) tHZ (3,4) tBDD DATA OUT BUSYOUT VALID DATA (4) CE 2954 drw 08 tPU ICC ISB tPD 50% 50%
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not tested. 3. To access RAM, CE = V IL and SEM = V IH. To access semaphore, CE = V IH and SEM = V IL. Either condition must be valid for the entire t EW time. 4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW. 5. 'X' in part numbers indicates power rating (S or L). Operating Temperature and Supply Voltage(5) Symbol Parameter 7015X12 Com'l Only 7015X15 Com'l Only 7015X17 Com'l Only WRITE CYCLE tEW Chip Enable to End-of-Write (3) 10 ____ 12 ____ 12 ____ ns tAW Address Valid to End-of-Write 10 ____ 12 ____ 12 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 10 ____ 10 ____ 10 ns tOW Output Active from End-of-Write (1, 2,4) 3 ____ 3 ____ 0 ____ ns 2954 tbl 13a Symbol Parameter 7015X20 Com'l & Ind 7015X25 Com'l Only 7015X35 Com'l Only WRITE CYCLE tEW Chip Enable to End-of-Write (3) 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tWZ Write Enable to Output in High-Z (1,2) ____ 12 ____ 15 ____ 20 ns tOW Output Active from End-of-Write (1,2,4) 3 ____ 3 ____ 3 ____ ns 2954 tbl 13b
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. R/ W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a LOW CE and a LOW R/ W for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/ W. 7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from stead y state with the Output Test Load (Figure 2). 8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = V IL and SEM = V IH. To access Semaphore, CE = V IH and SEM = V IL. tEW must be met for either condition. Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) R/W tWC tHZ tAW tWRtAS tWP DATA OUT (2) tWZ tDW tDH tOW OE ADDRESS DATA IN CE orSEM (6) (4) (4) (3) 2954 drw 09 (7) (9) (7) tLZ tHZ (7) 2954 drw 10 tWC tAS tWR tDW tDH ADDRESS DATA IN CE or SEM R/W tAW tEW (3)(2)(6) (9) Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTES: 1. D OR = D OL =VIH, CER = CEL =VIH. 2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/ W “A” or SEM“A” going high to R/ W“B” or SEM“B” going HIGH. 4. If t SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. Timing Waveform of Semaphore Write Contention(1,3,4) NOTES: 1. CE = V IH for the duration of the above timing (both write and read cycle). 2. “DATA OUT VALID” represents all I/O's (I/O 0-I/O8) equal to the semaphore value. SEM 2954 drw 11 tAW tEW tSOP I/O VALID ADDRESS tSAA R/W tWR tOH tACE VALID ADDRESS DATA IN VALID DATA OUT tDW tWP tDHtAS tAOE Read CycleWrite Cycle A0-A2 OE VALID(2) tSWRD SEM"A" 2954 drw 12 tSPS MATCH R/W"A" MATCH A0"A"-A2" A " SIDE "A" (2) SEM"B" R/W"B"SIDE "B" (2) A0"B"-A2" B "
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range(6) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/ S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention on Port "A". 6. 'X' in part numbers indicates power rating (S or L). 7015X12 Com'l Only 7015X15 Com'l Only 7015X17 Com'l Only BUSY TIMING (M/ S = V IH) tBAA BUSY Access T ime from Address ____ 12 ____ 15 ____ 17 ns tBDA BUSY Disable T ime from Address ____ 12 ____ 15 ____ 17 ns tBAC BUSY Access Time from Chip Enable ____ 12 ____ 15 ____ 17 ns tBDC BUSY Disable Time from Chip Enable ____ 12 ____ 15 ____ 17 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (3) ____ 15 ____ 18 ____ 18 ns BUSY INPUT TIMING (M/ S = V IL) PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 25 ____ 30 ____ 40 ns tDDD Write Data Valid to Read Data Delay (1) ____ 20 ____ 25 ____ 35 ns 2954 tbl 14a 7015X20 Com'l & Ind 7015X25 Com'l Only 7015X35 Com'l Only BUSY TIMING (M/ S = V IH) tBAA BUSY Access Time from Address ____ 20 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 20 ns tBDC BUSY Disable Time from Chip Enable ____ 17 ____ 17 ____ 20 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (3) ____ 30 ____ 30 ____ 35 ns BUSY INPUT TIMING (M/ S = V IL) PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 45 ____ 50 ____ 60 ns tDDD Write Data Valid to Read Data Delay (1) ____ 30 ____ 35 ____ 45 ns 2954 tbl 14b
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges 2954 drw 13 tDW tAPS ADDR "A" tWC DATA OUT "B" MATCH tWP R/W"A" DATA IN "A" ADDR "B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) Timing Waveform of Write with BUSY(3) NOTES: 1. t WH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/ W"B", until BUSY"B" goes HIGH. 3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". NOTES: 1. To ensure that the earlier of the two ports wins. t APS is ignored for M/S=V IL 2. CEL = CER = V IL 3. OE = V IL for the reading port. 4. If M/ S=VIL (SLAVE), BUSY is an input. Then for this example, BUSY“A”=VIH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". 2954 drw 14 R/W"A" BUSY"B" tWP tWB R/W"B" tWH (1) (2)
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Operating Temperature and Supply Voltage Range(1) Waveform of BUSY Arbitration Controlled by CE timing(1) (M/S = VIH) Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2954 drw 15 ADDR "A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 2954 drw 16 ADDR "A" ADDRESS "N" ADDR "B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" 7015X12 Com'l Only 7015X15 C om'l Only 7015X17 Com'l Only INTERRUPT TIMING 2954 tbl 15a 7015X20 Com'l & Ind 7015X25 Com'l Only 7015X35 Com'l Only INTERRUPT TIMING 2954 tbl 15b
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges Truth Table III — Interrupt Flag(1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal ( CE or R/ W) is asserted last. 4. Timing depends on which enable signal ( CE or R/ W) is de-asserted first. NOTES: 1. Assumes BUSYL = BUSYR = V IH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = V IL, then no change. 2954 drw 17 ADDR "A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR(3) (4) tINS (3) INT"B" (2) 2954 drw 18 ADDR "B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR (3) INT"B" (2) Left Port Right Port FunctionR/WL CEL OEL A12L-A0L INTL R/WR CER OER A12R-A0R INTR LLX 1 F F F XXXX X L (2) Set Right INTR Flag X X XXX X L L 1 F F F H (3) Reset Right INTR Flag XXX X L (3) L L X 1FFE X Set Left INTL Flag X L L 1FFE H (2) XXX X X R e s e t L e f t INTL Flag 2954 tbl 16 Waveform of Interrupt Timing(1)
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7015 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If t APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015. 2. There are eight semaphore flags written to via I/O 0 and read from all I/O s (I/O0 - I/O 8). These eight semaphores are addressed by A 0 - A 2. 3. CE = V IH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functional Description The IDT7015 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7015 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE where a write is defined as the CE = R/W = VIL per Truth Table III. The left port clears the interrupt by an address location 1FFE access when CER =OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF and to clear the interrupt flag (INTR), the right port must access memory location 1FFF. The message (9 bits) at 1FFE or 1FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes but are still part of the random access memory. Refer to Table III for the interrupt operation. Inputs Outputs FunctionCEL CER AOL-A12L AOR-A12R BUSYL(1) BUSYR(1) XXN O M A T C H H H N o r m a l H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit (3) 2954 tbl 17 Functions D 0 - D15 Left D 0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 295 4 tbl 1 8
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7015 RAMs. Truth Table I where CE and SEM are both HIGH. flexibility in system architecture. two accesses to proceed and signals the other side that the RAM is “busy”. to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. prevented to a port by tying the BUSY pin for that port LOW. resulting array requires the use of an external AND gate. array and another master indicating BUSY on one other side of the array. inhibit the write operations from the other port for the other part of the word. Port RAM or any other shared resource.
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simulta- neous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7015’s Dual-Port RAM. Say the 8K x 9 RAM was to be divided into two 4K x 9 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7015 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A 0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in inter processor communications. (A thorough discussing on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the
given a common meaning as was shown in the example above. their assigned portions of memory continuously without any wait states.
0 D Q
Figure 4. IDT7015 Semaphore Logic thereby guaranteeing a consistent data structure.
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Ordering Information
NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 Datasheet Document History 01/11/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations 06/03/99: Changed drawing format Page 1 Corrected DSC number 11/10/99: Replaced IDT logo 05/19/00: Page 4 Increased storage temperature parameter Clarified T A parameter Page 6 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes 01/24/02: Pages 2 & 3 Added date revision for pin configurations Pages 4, 6, 7, 9 & 12 Removed Industrial temp footnote from all tables Pages 6, 7, 9, 12 & 14 Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics Page 20 Added Industrial temp offering to 20ns ordering information Pages 1 & 20 Replaced TM logo with ® logo 2954 drw 21 A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF J 80-pin TQFP (PN80) 68-pin PLCC (J68) Commercial Only Commercial Only Commercial Only Commercial & Industrial Commercial Only Commercial Only S L Standard Power Low Power XXXXX Device Type 72K (8K x 9) Dual-Port RAM7015 Speed in nanoseconds A G (2) Green Blank Tube or Tray Tape and Reel A
6.42 IDT7015S/L High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercia l Temperature Ranges CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. Datasheet Document History (con't) 04/04/06: Page 1 A dded green availability to features Page 20 Added green indicator to ordering information 10/21/08: Page 20 Removed "IDT" from orderable part number 08/18/14: Page 20 Added Tape & Reel to Ordering Information Page 2, 3 & 20 The package codes PN80-1, G68-1 & J68-1 changed to PN80, G68 & J68 to match standard package codes 03/04/16: Page 2 Changed diagram for the J68 pin configuration by rotating package pin labels and pin numbers 90 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1 Removed J68 chamfer and aligned the top and bottom pin labels in the standard direction Page 3 Changed diagram for the PN80 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Corrected the PN80 pin label spacing and removed the chamfer Added the IDT logo to the J68 and PN80 pin configurations and changed the text to be in alignment with new diagram marking specs and removed the date revision indicator from all pin configurations Updated footnote references for PN80 pin configuration Deleted all ceramic 68 pin PGA references including the G68 pin configuration Page 4 Military grade removed from Absolute Max and Max Operating tables Page 6, 7, 9, 12 & 14 Military grade removed from all DC Elec & all AC Elec tables for all speeds Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 10/10/17: