7013

AD7013 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

REV. A Tel: 617/329-4700 Fax: 617/326-8703 a Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. CMOS TIA IS-54 Baseband Receive Port GENERAL DESCRIPTION The AD7013 is a complete low power, CMOS, TIA IS-54 base- band receive port with single +5 V power supply. The part is designed to perform the baseband conversion of I and Q waveforms in accordance with the American (TIA IS-54) Digital Cellular Telephone system. The receive path consists of two high performance sigma-delta ADCs, each followed by a FIR digital filter. A primary and auxiliary set of IQ differential analog inputs are provided, where either can be selected as inputs to the sigma-delta ADCs. Also, a choice of two frequency responses are available for the receive FIR filters; a Root-Raised-Cosine filter for digital mode or a brick wall response for analog mode. Differential analog inputs are provided for both I and Q channels. On-chip calibration logic is also provided to remove either on-chip offsets or remove system offsets. A 16-bit serial interface is provided, interfacing easily to most DSPs. The receive path also provides a means to vary the sampling instant, giving a resolution to 1/32 of a symbol interval. The auxiliary section provides two 8-bit DACs and one 10-bit DAC for functions such as automatic gain control (AGC), automatic frequency control (AFC) and power amplifier control. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has receive and auxiliary power down options. The AD7013 is housed in a space efficient 28-pin SSOP (Shrink Small Outline Package). FUNCTIONAL BLOCK DIAGRAM DxCLK AD7013 VAA DGND VDD AGND BYPASS MCLK IRx IRx Rx CLK Rx DATA Rx FRAME AUX DAC1 AUX DAC2 AUX DAC3 D S–D MODULATOR AUX IRx AUX IRx QRx QRx AUX QRx AUX QRx MUX MUX DATA IN FRAME IN RECEIVE CHANNEL SERIAL INTERFACE ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER FS ADJUST AGND AGND MODE1 FRAME OUT SERIAL INTERFACE ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER OFFSET ADJUST OFFSET ADJUST SWITCHED CAP FILTER SWITCHED CAP FILTER D S–D MODULATOR 1.23V REFERENCE LATCH 8-BIT AUX DAC FULL-SCALE ADJUST LATCH 8-BIT AUX DAC LATCH 10-BIT AUX DAC

FEATURES

Differential or Single-Ended Analog Inputs Auxiliary Set of Analog I & Q Inputs Two Sigma-Delta A/D Converters Choice of Two Digital FIR Filters Root-Raised-Cosine Rx Filters, α = 0.35 Brick Wall FIR Rx Filters On-Chip or User Rx Offset Calibration ADC Sampling Vernier Three Auxiliary DACs On-Chip Voltage Reference Low Active Power Dissipation, Typical 45 mW Low Sleep Mode Power Dissipation, <50 µW 28-Pin SSOP

APPLICATIONS

American TIA Digital Cellular Telephony American Analog Cellular Telephony Digital Baseband Receivers

Parameter AD7013A Units Test Conditions/Comments RECEIVE SECTION ADC SPECIFICATION Number of Input Channels 4 (IRx–IRx) and QRx–QRx); CR12 = 0 (AUX IRx–AUX IRx) and (AUX QRx–AUX QRx); CR12 = 1 Number of ADC Channels 2 Resolution 15 Bits ADC Signal Range 2.6 Volts p-p Measured Using an Input Sine Wave of 3 kHz Differential Signal Range V BIAS ± 0.65 Volts For Both Noninverting and Inverting Analog Inputs Single-Ended Signal Range V BIAS ± 1.3 Volts For Noninverting Analog Inputs; Inverting Analog Inputs = V BIAS VBIAS 0.65 to (VAA–0.65) Volts min/max Differential 1.3 to (VAA–1.3) Volts min/max Single-Ended Input Range Accuracy ± 7.5 % Accuracy Bias Offset Error ± 7.5 mV Autocalibration; V BIAS = min/max ± 55 mV User Calibration; I & Q Offset Adjust Registers Equal to Zero Dynamic Specifications CMRR –40 dB typ Measured Using an Input Sine Wave of 3 kHz with Both Noninverting and Inverting Inputs Tied Together Dynamic Range 70 dB typ Digital Mode Filter; CR11 = 0 65 dB typ Analog Mode Filter; CR11 = 1 SNR 2 65 dB min Digital Mode Filter; CR11 = 0 68 dB typ 60 dB min Analog Mode Filter; CR11 = 1 63 dB typ Input Sampling Rate 1.5552/1.28 MHz MCLK = 6.2208 MHz/5.12 MHz; MCLK/4 Output Word Rate 97.2/80 kHz MCLK = 6.2208 MHz/5.12 MHz; 4 × Sampling of the Symbol Rate, MCLK/64 48.6/40 kHz MCLK = 6.2208 MHz/5.12 MHz; 2 × Sampling of the Symbol Rate, MCLK/128 RECEIVE DIGITAL FILTERS Digital Mode MCLK = 6.2208 MHz Root-Raised-Cosine α = 0.35 Settling Time 329.2 µs Absolute Group Delay 164.6 µs Frequency Response 0–7.8975 kHz ± 0.05 dB max 11.9 kHz –3.0 dB 16.4025 kHz –19 dB > 30 kHz –66 dB max Analog Mode MCLK = 5.12 MHz Brick Wall Filter Settling Time 400 µs Absolute Group Delay 200 µs Frequency Response 0–8 kHz 0 to –0.5 dB max 11.4 kHz –3.0 dB 15 kHz –24 dB >17 kHz –68 dB max TIA IS-54 RECEIVE SPECIFICATIONS Error Vector Magnitude 3 2 % rms typ Measured Using a Full-Scale Input Error Offset Magnitude 3 1 % rms typ (VAA = VDD = +5 V ± 10%; AGND = DGND = 0 V; f MCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted) –2– REV. A AD7013–SPECIFICATIONS1

Parameter AD7013A Units Test Conditions/Comments AUXILIARY SECTION AUX DAC1 AUX DAC2 AUX DAC3 Resolution 10 8 8 Bits DC Accuracy Integral ± 3 ± 1 ± 1 LSBs max Differential –1.5/+4 ± 1 ± 1 LSBs max AUX DAC2 & AUX DAC3 Guaranteed Monotonic Zero Code Leakage ± 500 ± 500 ± 500 nA max Gain Error ± 7.5 ± 7.5 ± 7.5 % max Output Full-Scale Current 566 280 280 µAR SET = 18 kΩ Output Impedance 4 2M Ω typ Output Voltage Compliance 2.6 Volts max Coding Binary Power Down Option Yes REFERENCE SPECIFICATIONS VREF 1.23 Volts typ Reference Accuracy ± 5 % max Reference Impedance 20 k Ω typ LOGIC INPUTS VINH, Input High Voltage V DD–0.9 V min VINL, Input Low Voltage 0.9 V max IINH, Input Current 10 µA max CIN, Input Capacitance 10 pF max LOGIC OUTPUTS VOH, Output High Voltage V DD–0.4 V min |I OUT| ≤ 40 µA VOL, Output Low Voltage 0.4 V max |I OUT| ≤ 1.6 mA POWER SUPPLIES VDD 4.5/5.5 V MIN/VMAX IDD All Sections Active 10.5 mA max CR14 = CR15 = CR16 = CR17 = 1 9 mA typ MCLK = 6.2208 MHz; 80 pF Load on DxCLK ADCs Active Only 8.6 mA max CR14 = 1; CR15 = CR16 = CR17 = 0 MCLK = 6.2208 MHz; 80 pF Load on DxCLK AUX DACs Active Only 2.2 mA max CR14 = 0; CR15 = CR16 = CR17 = 1; MCLK Inactive, MCLK = 0 V 10-Bit AUX DAC Active 1.6 mA max CR14 = CR15 = CR16 = 0; CR17 = 1; MCLK Inactive, MCLK = 0 V All Sections Powered Down 6 2 mA max CR14 = CR15 = CR16 = CR17 = 0 MCLK = 6.2208 MHz; 80 pF Load on DxCLK 30 µA typ MCLK =100 kHz; 80 pF Load on DxCLK 10 µA max MCLK Inactive, MCLK = 0 V NOTES 1Operating temperature ranges as follows: A version: –40 °C to +85°C. 2SNR calculation includes noise and distortion components. 3See Terminology. 4Sampled tested only. 5Measured while the digital inputs are static and equal to 0 V or V DD. 6With all sections powered down, I DD is proportional to the capacitive load on DxCLK. For example, I DD is typically 1.7 mA with 80 pF load and 600 µA with 10 pF load. Specifications subject to change without notice. –3–REV. A AD7013

–4– REV. A AD7013 ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) Operating Temperature Range Lead Temperature Soldering NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions extended periods may affect device reliability. TERMINOLOGY Sampling Rate This is the rate at which the modulators on the receive channels sample the analog input. Output Rate This is the rate at which data words are made available at the RxDATA pin. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the DAC or ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or ADC. Dynamic Range Dynamic Range is the ratio of the maximum rms input signal to the rms noise of the converter, expressed logarithmically, in decibels (dB = 20 log 10 [ratio]). Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for a sine wave is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Settling Time This is the digital filter settling time in the AD7013 receive section. Bias Offset Error This is the amount of offset in the receive channel ADC when the differential inputs are tied together. Receive Error Vector Magnitude This is a measure of the rms signal error vector introduced by the receive Root-Raised Cosine digital filter. This is measured by applying an ideal transmit signal (i.e., an ideal π/4 DQPSK modulator and an ideal transmit Root-Raised Cosine filter) to the receive channel and measuring the resulting rms error vector. Offset Vector Magnitude This is a measure of the offset vector introduced by the AD7013 as illustrated in the figure below. The offset vector is calculated so as to minimize the rms error vector for each of the constellation points. ERROR VECTOR SIGNAL VECTOR OFFSET VECTOR Q I PIN CONFIGURATION VAA IRx BYPASS AGND AUX IRx QRx AUX QRx AUX DAC1 AUX DAC2 AUX DAC3 AUX IRx IRx FS ADJUST AGND QRx VDD AUX QRx MCLK AGND DxCLK MODE1 DATA IN Rx FRAME FRAME IN Rx DATA DGND Rx CLK FRAME OUT TOP VIEW (Not to Scale) AD7013 ORDERING GUIDE Model Temperature Range Package Option* AD7013ARS –40 °C to +85°C RS-28 *RS = SSOP. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom- mended to avoid performance degradation or loss of functionality.

REV. A AD7013 –5– PIN FUNCTION DESCRIPTIONS SSOP Pin Number Mnemonic Function POWER SUPPLY 1V AA Positive Power Supply for Analog section. A 0.1 µF decoupling capacitor should be connected between this pin and AGND. 21 V DD Positive Power Supply for Digital section. A 0.1 µF decoupling capacitor should be connected between this pin and DGND. Both V AA and VDD should be externally tied together. 10, 25, 27 AGND Analog Ground. 16 DGND Digital Ground. Both AGND and DGND should be externally tied together. ANALOG SIGNAL AND REFERENCE 28 BYPASS Reference Decoupling Output. A 10 nF decoupling capacitor should be connected between this pin and AGND. 2, 4 IRx, IRx Differential Analog Inputs for the I receive channel. These are the primary receive analog inputs and are selected by setting CR12 to a zero in the command register. 6, 8 QRx, QRx Differential Analog Inputs for the Q receive channel. These are the primary receive analog inputs and are selected by setting CR12 to a zero in the command register. 3, 5 AUX IRx, AUX IRx Auxiliary Differential Analog Inputs for the I receive channel. The Auxiliary inputs are selected by setting CR12 to a one in the command register. 7, 9 AUX QRx, AUX QRx Auxiliary Differential Analog Inputs for the Q receive channel. The Auxiliary inputs are selected by setting CR12 to a one in the command register. 24 AUX DAC1 Analog output from the 10-bit auxiliary DAC. 3, 22 AUX DAC2, AUX DAC3 Analog outputs from the 8-bit auxiliary DACs.

26 FS ADJUST An external resistor is connected from this pin to ground to determine the full-

scale current for AUX DAC1, AUX DAC2, and AUX DAC3. SERIAL INTERFACE AND CONTROL 20 MCLK Master Clock, Digital Input. When operating in IS-54 Digital mode this pin should be driven by a 6.2208 MHz CMOS compatible clock source and 5.12 MHz clock source for Analog Mode. 19 DxCLK Transmit Clock, Digital Output. This is a continuous clock equal to MCLK/2 which can be used to clock the serial port of a DSP. 17 FRAME IN Digital Input. This is used to frame the clocking in of 16-bit words for the control registers serial interface. 18 DATA IN Digital Input. Transmit Serial Data, digital input. This pin is used to clock in data for the serial interface on the rising edge of DxCLK. 15 FRAME OUT Digital Output. This output represents a buffered version of FRAME IN and is controlled by the MODE1 pin. This pin can be used to daisy chain the FRAME IN signal. 11 MODE1 Digital Input. This pin determines the state of FRAME OUT. When MODE1 is high, FRAME IN is buffered and made available on FRAME OUT. When MODE1 is low, FRAME OUT is in 3-STATE. RECEIVE INTERFACE AND CONTROL 14 RxCLK Output Clock for the receive section interface. 12 RxFRAME Synchronization output for framing I and Q data at the receive interface. 13 RxDATA Receive Data, digital output. I and Q data are available at this pin via a 16-bit serial interface. Data is valid on the falling edge of RxCLK. I and Q data are clocked out as two 16-bits words, with the I word being clocked first. The last bit in each 16-bit word is a I/Q flag bit, indicating whether that word is an I word or a Q word.

0 I LSB 1 Q MSB

Figure 3. Receive Serial Interface Timing with 4 × Sampling of the Symbol Rate (CR10 = 1)

word to be subtracted from subsequent ADC samples. word to be subtracted from subsequent ADC samples. AUX DAC1 0 1 1 1 10 Bits All Zeros The 10-bit auxiliary DAC current output is determined by this register. AUX DAC2 1 0 0 0 8 Bits All Zeros The 8-bit auxiliary DAC current output is determined by this register. connected between FS ADJUST and AGND. AUX DAC3 1 0 0 1 8 Bits All Zeros The 8-bit auxiliary DAC current output is determined by this register. connected between FS ADJUST and AGND. Table IV, is used to write to any of the internal registers. N/A 0 0 0 0 N/A N/A No Action. N/A 1 1 1 1 N/A N/A No Action. Figure 6. AD7013 Registers

Figure 7. Internal AD7013 Registers CR10 = 0 Low ADC sample rate. The sample rate of the receive ADCs are equal to 2 × the symbol rate or equal to MCLK/128. = 1 High ADC sample rate. The sample rate of the ADCs are equal to 4 × the symbol rate or equal to MCLK/64. CR11 = 0 RRC Receive FIR filter. This selects the root-raised consine filter response for the receive sigma-delta ADCs. response is shown in Figure 17. AUX QRx as the Q channel inputs. automatically calibrated out. allowing the AD7013 to also calibrate out external offsets. = 1 Receive ADC active mode. This activates the receive ADCs for normal operation. CR15 = 0 8-Bit AUX DAC3 sleep mode. This enters the 8-bit auxiliary DAC into a low power sleep mode. = 1 8-Bit AUX DAC3 active mode. This activates the 8-bit auxiliary DAC for normal operation. = 1 8-Bit AUX DAC2 active mode. This activates the 8-bit auxiliary DAC for normal operation. CR17 = 0 10-Bit AUX DAC1 sleep mode. This enters the 10-bit auxiliary DAC into a low power sleep mode. = 1 10-Bit AUX DAC1 active mode. This activates the 10-bit auxiliary DAC for normal operation. CR18 = 0 3-State Enable. This enables the 3-state buffers on the receive serial interface.

minimal current between receive bursts. MCLK/8 as shown in Figure 9. Figure 8. Switched Capacitor and Digital Filter Transfer connected to the differential inputs of the sigma-delta modulator. thereby setting the single-ended input range equal to 0 V to 2.46 V. Figure 9. External RC Network for Differential Signals

1.23 VOLTS 295

Figure 10. External RC Network for Single-Ended Signals

REV. A –17– 10-Bit AUX DAC1 Integral Nonlinearities (INL) 8-Bit AUX DAC2 Integral Nonlinearities (INL) 8-Bit AUX DAC3 Integral Nonlinearities (INL) 10-Bit AUX DAC1 Differential Nonlinearities (DNL) 8-Bit AUX DAC2 Differential Nonlinearities (DNL) 8-Bit AUX DAC3 Differential Nonlinearities (DNL) 0 1024 768 512 256 DAC CODE 1.5 –1.5 0.5 –0.5 DNL ERROR – LSBs 0.5 –0.5 0 256 192 12864 0.25 –0.25 DAC CODE DNL ERROR – LSBs 0.5 –0.5 0 256 192 12864 0.25 –0.25 DAC CODE DNL ERROR – LSBs INL ERROR – LSB S 0.5 –0.5 –0.25 0.25 256 64 0 192 128 DAC CODE 0.5 –0.5 256 –0.25 64 0 0.25 192 128 INL ERROR – LSB S DAC CODE 1.5 –1.5 256 –0.5 1024 768 512 DAC CODE INL ERROR – LSB S 0.5 Typical Performance Characteristics–AD7013

–18– REV. A AD7013 400 10 20 30 FREQUENCY – kHz MAGNITUDE – dB –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 400 10 20 30 FREQUENCY – kHz MAGNITUDE – dB –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 Q Channel Digital Mode FFT; MCLK = 6.2208 MHz π/4 DQPSK Constellation Diagram; Typical Error Vector 2% RMS π/4 DQPSK I and Q Receive Samples I Channel Digital Mode FFT; MCLK = 6.2208 MHz Q Channel Analog Mode FFT; MCLK = 5.12 MHzI Channel Analog Mode FFT; MCLK = 5.12 MHz 48.60 12.15 24.3 36.45 FREQUENCY – kHz MAGNITUDE – dB –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 48.60 12.15 24.3 36.45 FREQUENCY – kHz MAGNITUDE – dB –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –1 1 I SAMPLES Q SAMPLES 0 –1 1 I SAMPLES Q SAMPLES

REV. A AD7013 –19– I Channel ADC Noise Histogram with IRx and IRx Tied Together and Offset Register = 0; Number Codes = 1000, Standard Deviation = 4.44 Codes Q Channel ADC Noise Histogram with QRx and QRx Tied Together and Offset Register = 0; Number Codes = 1000, Standard Deviation = 3.82 Codes AD7013 Sleep Current as a Function of DxCLK Load Capacitance 140 –40 –41 120 100 ADC CODE NUMBER OF OCCURRENCES 140 –40 –41 120 100 ADC CODE NUMBER OF OCCURRENCES 50 0 200 150 100 DxCLK LOAD CAPACITANCE – pF SLEEP MODE I DD – mA 1.5 0.5 2.5 VAA = VDD = +5V MCLK = 6.2208 MHz CR14 = CR15 = CR16 = CR17 = 0

–20– REV. A AD7013 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead SSOP (RS-28) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 0°0.0256 (0.65) BSC 0.407 (10.34) 0.397 (10.08) 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) PIN 1 14 1 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) PRINTED IN U.S.A. C1862a–7.5–7/94