7009L15PFG

4839pgm.PMD

Document overview

• Manufacturer or author: lruddell
• PDF pages: 17

Technical content

Features

◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) ◆ Low-power operation – IDT7009L Active: 1W (typ.) Standby: 1mW (typ.) ◆ Dual chip enables allow for depth expansion without external logic ◆ IDT7009 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM IDT7009L NOTES: 1. BUSY is an input as a Slave (M/ S = V IL) and an output when it is a Master (M/ S = V IH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT7009 is a high-speed 128K x 8 Dual-Port Static RAM. The IDT7009 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or- more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE 0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only1W of power. The IDT7009 is packaged in a 100-pin Thin Quad Flatpack (TQFP). NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. Pin Configurations(1,2,3)

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A 16L A0R - A 16R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 4839 tbl 01 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. Capacitance (TA = +25°C, f = 1.0MHz) (TQFP Only) Absolute Maximum Ratings(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > Vcc + 10%. NOTES: 1. V IL > -1.5V for pulse width less than 10ns. 2. V TERM must not exceed Vcc + 10%. Recommended DC Operating Conditions NOTES: 1. This is the parameter T A. This is the "instant on" case temperature. Maximum Operating Temperature and Supply Voltage Symbol Rating Commercial & Industrial Military Unit VTE RM(2) T erminal Voltage with Respect to GND TBIAS Temperature Under Bias -55 to +125 -65 to +135 oC TST G Storage Temperature -65 to +150 -65 to +150 oC IOUT DC Output Current 50 50 mA 483 9 tbl 02 Grade Ambient Temperature(2 ) GND Vcc Military -55 OC to +125OC0 V 5 . 0 V + 10% Commercial 0 OC to +70 OC0 V 5 . 0 V + 10% Industrial -40 OC to +85 OC0 V 5 . 0 V + 10% 4839 tbl 0 3 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(2 ) V VIL Input Low Voltage -0.5 (1 ) ____ 0.8 V 483 9 tbl 0 4 Symbol Parameter (1 ) Conditions(2) Max. Unit CIN Input Capacitance V IN = 3dV 9 pF COUT Output Capacitance V OUT = 3dV 10 pF 4839 tbl 05

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I: Chip Enable(1,2) Truth Table II: Non-Contention Read/Write Control NOTES: 1. A 0L – A 16L ≠ A0R – A 16R. 2. Refer to Chip Enable Truth Table. Truth Table III: Semaphore Read/Write Control(1) NOTES: 1. There are eight semaphore flags written to via I/O 0 and read from all the I/Os (I/O 0-I/O7). These eight semaphore flags are addressed by A 0-A2. 2. Refer to Chip Enable Truth Table. NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE 1 levels, CE is a reference only. 2. 'H' = V IH and 'L' = V IL. 3. CMOS standby requires 'X' to be either < 0.2V or > V CC - 0.2V. CE CE 0 CE1 Mode L VIL VIH Port Selected (TTL Active) < 0.2V > VCC -0.2V Port Selected (CMOS Active) H VIH X Port Deselected (TTL Inactive) XV IL Port Deselected (TTL Inactive) >VCC -0.2V X Port Deselected (CMOS Inactive) X< 0.2V Port Deselected (CMOS Inactive) 4839 tbl 06 Inputs(1 ) Outputs ModeCE(2 ) R/W OE SEM I/O0-7 H X X H High-Z Deselected: Power-Down LLXH D A T A IN Write to memory LHLH D A T A OUT Read memory X X H X High-Z Outputs Disabled 4839 drw 0 7 Inputs Outputs ModeCE(2) R/W OE SEM I/O0-7 HHL L D A T A OUT Read Semaphore Flag Data Out H ↑ XL D A T A IN Write I/O0 int o Semaphore Flag 4839 tbl 0 8

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%) NOTES: 1. At Vcc < 2.0V, input leakages are undefined. 2. Refer to Chip Enable Truth Table. Symbol Parameter Test Conditions 7009L UnitMin. Max. |ILI| Input Leakage Current (1 ) VCC = 5.5V, V IN = 0V to V CC ___ 5µ A |ILO| Output Leakage Current CE = V IH, VOUT = 0V to V CC ___ 5µ A VOL Output Low Voltage I OL = 4mA ___ 0.4 V VOH Output High Voltage I OH = -4mA 2.4 ___ V 4839 tbl 09 NOTES: 1. V CC = 5V, T A = +25°C, and are not production tested. I CCDC = 120mA (Typ.) 2. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t RC, and using “AC Test Conditions” of input levels of GND to 3V. 3. f = 0 means no address or control lines change. 4. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5. Refer to Chip Enable Truth Table. Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) Symbol Parameter Test Condition Version 7009L15 Com'l Only 7009L20 Com'l & Ind UnitTyp.(1 ) Max Typ. (1) Ma x ICC Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = fMAX(2 ) COM'L L 220 340 200 300 mA ISB1 Standby Current (Bot h Port s - TT L Level Inputs) CEL = CER = V IH SEMR = SEML = V IH f = fMAX(2 ) COM'L L 65 100 50 75 mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = VIH(4) Active Port Outputs Disabled, f=fMAX(2 ), SEMR = SEML = V IH COM'L L 145 225 130 195 mA ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V, V IN > VCC - 0.2V or VIN < 0.2V, f = 0 (3 ) SEMR = SEML > VCC - 0.2V COM'L L 0.2 3.0 0.2 3.0 mA ISB4 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(4), SEMR = SEML > VCC - 0.2V, VIN > VCC - 0.2V or V IN < 0.2V, Active Port Outputs Disabled, f = f MAX(2) COM'L L 135 220 120 190 mA 4839 tbl 10

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges Operating Temperature and Supply Voltage NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranted by device characterization, but is not production tested. 3. To access RAM, CE= V IL and SEM = V IH. To access semaphore, CE = V IH and SEM = V IL. Either condition must be valid for the entire t EW time. 4. The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and tOW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW. Operating Temperature and Supply Voltage Range 7009L15 Com'l Only 7009L20 Com'l & Ind UnitS y m b o l P a r a m e t e r M i n .M a x .M i n .M a x . READ CYCLE tAA Address Access Time ____ 15 ____ 20 ns tACE Chip Enable Access Time (4) ____ 15 ____ 20 ns tAOE Output Enable Access Time ____ 10 ____ 12 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 10 ns tPU Chip Enable to Power Up Time (2 ) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2 ) ____ 15 ____ 20 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)1 0 ____ 10 ____ ns tSAA Semaphore Address Access Time ____ 15 ____ 20 ns 4839 tbl 12 Symbol Parameter 7009L15 Com'l Only 7009L20 Com'l & Ind UnitMin. Max. Min. Max. WRITE CYCLE t tEW Chip Enable to End-of-Write (3 ) 12 ____ 15 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ ns tAS Address Set-up Time (3 ) 0 ____ 0 ____ ns tWP Write Pulse Width 12 ____ 15 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ ns tHZ Output High-Z Time(1,2) ____ 10 ____ 10 ns tWZ Write Enable to Output in High-Z(1,2) ____ 10 ____ 10 ns tOW Output Active from End-of-Write (1 , 2 ,4 ) 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ ns 4839 tbl 13

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) NOTES: 1. R/ W or CE = V IH during all address transitions. 2. A write occurs during the overlap (t EW or t WP) of a CE = V IL and a R/ W = V IL for memory array writing cycle. 3. t WR is measured from the earlier of CE or R/W (or SEM or R/ W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/ W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = V IL during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. 9. To access RAM, CE = V IL and SEM = V IH. To access semaphore, CE = V IH and SEM = V IL. tEW must be met for either condition. 10. Refer to Chip Enable Truth Table. R/W tWC tHZ tAW tWRtAS tWP DATAOUT (2) tWZ tDW tDH tOW OE ADDRESS DATAIN CE or SEM (6) (4) (4) (3) 4839 drw 07 (7) (7) (9,10) 4839 drw 08 tWC tAS tWR tDW tDH ADDRESS DATAIN R/W tAW tEW (3)(2)(6) CE or SEM(9,10)

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) NOTES: 1. D OR = D OL = V IL, CEL = CER = VIH (Refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A" . 3. This parameter is measured from R/ W"A" or SEM"A" going HIGH to R/ W"B" or SEM"B" going HIGH. 4. If t SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtai n the flag. Timing Waveform of Semaphore Write Contention(1,3,4) NOTES: 1. CE = V IH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). 2. "DATA OUT VALID" represents all I/O's (I/O 0 - I/O 7) equal to the semaphore value. SEM 4839 drw 09 tAW tEW DATA0 VALID ADDRESS tSAA R/W tWR tOH tACE VALID ADDRESS DATAIN VALID DATAOUT VALID(2) tDW tWP tDHtAS tSWRD tAOE tSOP Read CycleWrite Cycle A0-A2 OE tSOP SEM"A" 4839 drw 10 tSPS MATCH R/W"A" MATCH A0"A"-A2"A" SIDE "A"(2) SEM"B" R/W"B" A0"B"-A2"B" SIDE "B" (2)

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". Operating Temperature and Supply Voltage Range 7009L15 Com'l Only 7009L20 Com'l & Ind Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (M/ S=VIH) tBA A BUSY Access T ime from Address Match ____ 15 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ns tBA C BUSY Access T ime from Chip Enable Low ____ 15 ____ 20 ns tBDC BUSY Access T ime from Chip Enable High ____ 15 ____ 17 ns tAP S Arbitration Priority Set-up Time (2 ) 5 ____ 5 ____ ns tBDD BUSY Disable t o V alid Dat a(3 ) ____ 15 ____ 17 ns tWH Write Hold After BUSY(5 ) 12 ____ 15 ____ ns BUSY TIMING (M/ S=VIL) tWB BUSY Input to Write (4 ) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5 ) 12 ____ 15 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1 ) ____ 30 ____ 45 ns tDD D Write Data Valid to Read Data Delay (1) ____ 25 ____ 30 ns 4839 tbl 14

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges 4839 drw 11 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) Timing Waveform of Write with BUSY (M/S = VIL) NOTES: 1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S = V IL (SLAVE). 2. CEL = CER = V IL, refer to Chip Enable Truth Table. 3. OE = V IL for the reading port. 4. If M/ S = V IL (SLAVE), BUSY is an input. Then for this example BUSY "A" = V IH and BUSY "B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". NOTES: 1. t WH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W "B", until BUSY"B" goes HIGH. 3. t WB is only for the 'Slave' version. 4839 drw 12 R/W"A" BUSY"B" tWP tWB(3) R/W"B" tWH(1) (2)

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3) Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 3. Refer to Chip Enable Truth Table. Operating Temperature and Supply Voltage Range 4839 drw 13 ADDR"A" and "B" ADDRESSES MATCH CE"A" CE"B" BUSY"B" tAPS tBAC tBDC (2) 4839 drw 14 ADDR"A" ADDRESS "N" ADDR"B" BUSY"B" tAPS tBAA tBDA (2) MATCHING ADDRESS "N" 7009L15 Com'l Only 7009L20 Com'l & Ind S y m b o l P a r a m e t e r M i n .M a x .M i n .M a x .U n i t INTERRUPT TIMING tAS Address Set -up T ime 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Inte rrupt Se t Time ____ 15 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 20 ns 4839 tbl 15

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges Waveform of Interrupt Timing(1,5) Truth Table IV — Interrupt Flag(1,4,5) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal ( CE or R/ W) is asserted last. 4. Timing depends on which enable signal ( CE or R/ W) is de-asserted first. 5. Refer to Chip Enable Truth Table. NOTES: 1. Assumes BUSYL = BUSYR =V IH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = V IL, then no change. 4. INTL and INTR must be initialized at power-up. 5. Refer to Chip Enable Truth Table. 4839 drw 15 ADDR"A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR (3) (4) tINS(3) INT"B" (2) 4839 drw 16 ADDR"B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR(3) INT"B" (2) Left Port Right Port FunctionR/WL CEL OEL A16L-A0L INTL R/WR CER OER A16R-A0R INTR L L X 1FFFF X X X X X L (2) Set Right INTR Flag X X X X X X L L 1FFFF H (3) Reset Right INTR Flag XXX X L (3 ) L L X 1FFFE X Set Left INTL Flag X L L 1FFFE H (2) X X X X X Reset Left INTL Flag 4839 tbl 16

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT7009 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7009 has an automatic power down feature controlled by CE. The CE 0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = V IH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFFE (HEX), where a write is defined as CER = R/WR = VIL per Truth Table IV. The left port clears the interrupt through access of address location 1FFFE when CE L = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFFF. The message (8 bits) at 1FFFE or 1FFFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFFE and 1FFFF are not used as mail boxes, but as part of the random access memory. Refer to Table IV for the interrupt operation. NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7009 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If t APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. Refer to Chip Enable Truth Table. NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7009. 2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O 0-I/O7). These eight semaphores are addressed by A 0-A2. 3. CE = V IH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Truth Table V —Address BUSY Arbitration(4) Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3) Inputs Outputs FunctionCEL CER AOL-A16L AOR-A16R BUSYL(1) BUSYR(1 ) X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal LL M A T C H ( 2 ) ( 2 ) Write Inhibit(3 ) 4839 tbl 17 Functions D 0 - D7 Left D 0 - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free 4839 tbl 18

two accesses to proceed and signals the other side that the RAM is “busy”. to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. prevented to a port by tying the BUSY pin for that port LOW. resulting array requires the use of an external AND gate. the Dual-Port RAM or any other shared resource. Truth Table II where CE and SEM are both HIGH. flexibility in system architecture. array and another master indicating BUSY on one other side of the array. inhibit the write operations from the other port for the other part of the word. Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7009 RAMs.

the left side should succeed in gaining control. the other address pins has any effect. state in the middle of a read cycle due to a write cycle from the other side. gap between the read and write cycles. Figure 4. IDT7009 Semaphore Logic semaphores alone do not guarantee that access to a resource is secure. or misinterpreted, a software error can easily happen. to assure that they will be free when needed.

0 D Q

6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial T emperature Ranges

Ordering Information

NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. The IDT logo is a registered trademark of Integrated Device Technology, Inc. Datasheet Document History 09/30/99: Initial Public Release 11/10/99: Replace d IDT logo 01/05/01: Page 3 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Page 14 Added IV to Truth Table in Interrupts paragraph Changed ±200mV to 0mV in notes Removed Preliminary specification 01/24/02: Page 2 Added date revision for pin configuration Pages 3, 5, 7, 10 & 12 Removed Industrial temp footnote from all tables Pages 5, 7, 10 & 12 Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics Page 17 Added Industrial temp offering to 20ns ordering information Pages 1 & 17 Replaced TM logo with ® logo 01/31/06: Page 1 Added green availability to features Page 17 Added green indicator to ordering information 11/11/08: Page 17 Removed "IDT" from orderable part number 08/04/14: Page 17 Added Tape and Reel to Ordering Information Page 2 & 17 The package code PN100-1 changed to PN100 to match the standard pagckage code CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualP ortHelp@idt.com www.idt.com