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STM32F469XX STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 217

Technical content

Datasheet sections

• 1 Description
• 1.1 Compatibility throughout the family
• 1.1.1 LQFP176 package
• 1.1.2 LQFP208 package
• 1.1.3 UFBGA176 package
• 1.1.4 TFBGA216 package
• 2 Functional overview
• 2.1 ARM ® Cortex®-M4 with FPU and embedded Flash and SRAM
• 2.2 Adaptive real-time memory accelerator (ART Accelerator™)
• 2.3 Memory protection unit
• 2.4 Embedded Flash memory
• 2.5 CRC (cyclic redundancy check) calculation unit
• 2.6 Embedded SRAM
• 2.7 Multi-AHB bus matrix
• 2.8 DMA controller (DMA)
• 2.9 Flexible Memory Controller (FMC)
• 2.10 Quad-SPI memory interface (QUADSPI)
• 2.11 LCD-TFT controller
• 2.12 DSI Host (DSIHOST)
• 2.13 Chrom-ART Accelerator™ (DMA2D)
• 2.14 Nested vectored interrupt controller (NVIC)
• 2.15 External interrupt/event controller (EXTI)
• 2.16 Clocks and startup
• 2.17 Boot modes
• 2.18 Power supply schemes
• 2.19 Power supply supervisor
• 2.19.1 Internal reset ON
• 2.19.2 Internal reset OFF
• 2.20 Voltage regulator
• 2.20.1 Regulator ON
• 2.20.2 Regulator OFF

Datasheet sections

• 4 Memory mapping
• 5 Electrical characteristi cs
• 5.1 Parameter conditions
• 5.1.1 Minimum and maximum values
• 5.1.2 Typical values
• 5.1.3 Typical curves
• 5.1.4 Loading capacitor
• 5.1.5 Pin input voltage
• 5.1.6 Power supply scheme
• 5.1.7 Current consumption measurement
• 5.2 Absolute maximum ratings
• 5.3 Operating conditions
• 5.3.1 General operating conditions
• 5.3.2 VCAP1/VCAP2 external capacitor
• 5.3.3 Operating conditions at power-up / power-down (regulator ON)
• 5.3.4 Operating conditions at power-up / power-down (regulator OFF)
• 5.3.5 Reset and power control block characterist ics
• 5.3.6 Over-drive switching characteristics
• 5.3.7 Supply current characteristics
• 5.3.8 Wakeup time from low-power modes
• 5.3.9 External clock source characteristics
• 5.3.10 Internal clock source charac teristics
• 5.3.11 PLL characteristics
• 5.3.12 PLL spread spectrum clock generatio n (SSCG) characteristics
• 5.3.13 MIPI D-PHY characteristics
• 5.3.14 MIPI D-PHY PLL characteristics
• 5.3.15 MIPI D-PHY regulator characteristics
• 5.3.16 Memory characteristics
• 5.3.17 EMC characteristics
• 5.3.18 Absolute maximum ratings (electrical sensitivity)
• 5.3.19 I/O current injection characteristics
• 5.3.20 I/O port characteristics
• 5.3.21 NRST pin characteristics
• 5.3.22 TIM timer characteristics
• 5.3.23 Communications interfaces

Features

• Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories – Up to 2 MB of Flash memory organized into two banks allowing read-while-write – Up to 384+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR, SDRAM, Flash NOR/NAND memories – Dual-flash mode Quad-SPI interface
• Graphics: – Chrom-ART Accelerator™ (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface with minimum CPU load – LCD parallel interface, 8080/6800 modes – LCD TFT controller supporting up to XGA resolution –M I P I ® DSI host controller supporting up to 720p 30Hz resolution
• Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration
• Low power – Sleep, Stop and Standby modes –V BAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. 2x watchdogs and SysTick timer
• Debug mode – SWD & JTAG interfaces –C o r t e x®-M4 Trace Macrocell™
• Up to 161 I/O ports with interrupt capability – Up to 157 fast I/Os up to 90 MHz – Up to 159 5 V-tolerant I/Os
• Up to 21 communication interfaces – Up to 3 × I 2C interfaces (SMBus/PMBus) – Up to 4 USARTs and 4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to 6 SPIs (45 Mbits/s), 2 with muxed full- duplex I2S for audio class accuracy via internal audio PLL or external clock – 1 x SAI (serial audio interface) – 2 × CAN (2.0B Active) – SDIO interface
• Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full- speed PHY and ULPI – Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to

54 Mbytes/s

• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID

Table 1. Device summary

2.26 Universal synchronous/asynchronous re ceiver transmitters (USART) . . 39

2.28 Inter-integrated sound (I

2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 42

Table 24. Typical and maximum current consumption in Run mode, code with data processing Table 25. Typical and maximum current consumption in Run mode, code with data processing Table 26. Typical and maximum current consumption in Run mode, code with data Table 31. Typical and maximum current consumption in V Table 38. LSE oscillator characteristics (f

Table 77. ADC static accuracy at f

Table 113. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package Table 114. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package Table 115. WLCSP168 - 168-pin, 4.891 x 5.69 2 mm, 0.4 mm pitch wafer level chip scale Table 116. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball Table 117. LQFP176, 24 x 24 mm, 176- pin low-profile quad flat package Table 118. UFBGA176+25, - 201-ba ll, 10 x 10 mm, 0.65 mm pitch, Table 120. LQFP208, 28 x 28 mm, 208- pin low-profile quad flat package Table 121. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm

1 Description

The STM32F469xx devices are based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM® single-precision data- processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F469xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, and a true random number generator (RNG). They also feature standard and advanced communication interfaces:

• Up to three I 2Cs
• Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
• Four USARTs plus four UARTs
• An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI),
• Two CANs
• One SAI serial audio interface
• An SDMMC host interface
• Ethernet and camera interface
• LCD-TFT display controller
• Chrom-ART Accelerator™
• DSI Host. Advanced peripherals include an SDMMC interface, a flexible memory control (FMC) interface, a Quad-SPI Flash memory, and camera interface for CMOS sensors. Refer to Table 2 for the list of peripherals available on each part number. The STM32F469xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full speed mode, is available on all packages. The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F469xx devices are offered in eight packages, ranging from 100 to 216 pins. The set of included peripherals changes with the device chosen, according to Table 2.

• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances Figure 5 shows the general block diagram of the device family.

Table 2. STM32F469xx features and peripheral counts

1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

Table 2. STM32F469xx features and peripheral counts (continued)

1.1 Compatibility throughout the family

STM32F469xx devices are not compatible with other STM32F4xx devices. Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and LQFP208 packages (highlighted pins). The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices, only few IO port pins are substituted, as shown in Figure 3 and Figure 4. The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other STM32F4xx devices.

1.1.1 LQFP176 package

Figure 1. Incompatible board design for LQFP176 package

1. Pins from 85 to 133 are not compatible.

1.1.2 LQFP208 package

Figure 2. Incompatible board design for LQFP208 package

1. Pins from 118 to 128 and pin 137 are not compatible

1.1.3 UFBGA176 package

Figure 3. UFBGA176 port-to-terminal assignment differences

1. The highlighted pins are substi tuted with dedicated DSI IO pins on STM32F469xx/479xx devices.

1.1.4 TFBGA216 package

Figure 4. TFBGA216 port-to-terminal assignment differences

1. The highlighted pins are substituted with dedi cated DSI IO pins on STM32F469xx/479xx devices.

Figure 5. STM32F469xx block diagram

1. The timers connected to APB2 are clocked from TI MxCLK up to 180 MHz, while the timers connected to

in the RCC_DCKCFGR register.

STM32F469xx Functional overview

2 Functional overview

2.1 ARM ® Cortex®-M4 with FPU and embedded Flash and SRAM

The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM ® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F46x line is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F46x line. Note: Cortex ®-M4 with FPU core is binary compatible with the Cortex®-M3 core.

2.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which normally require the processor to wait for the Flash memory at higher frequencies. To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark ® benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.

2.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real- time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.

Functional overview STM32F469xx

2.4 Embedded Flash memory

The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data.

2.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

2.6 Embedded SRAM

All devices embed:

• Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.

2.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 6. STM32F469xx Multi-AHB matrix

2.8 DMA controller (DMA)

buffers without requiring any special code. source and destination are independent.

Functional overview STM32F469xx The DMA can be used with the main peripherals:

• SPI and I2S
• I2C
• USART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDIO
• Camera interface (DCMI)
• ADC
• SAI1
• QUADSPI.

2.9 Flexible Memory Controller (FMC)

The Flexible memory controller (FMC) includes three memory controllers:

• The NOR/PSRAM memory controller
• The NAND/memory controller
• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

STM32F469xx Functional overview

2.10 Quad-SPI memory interface (QUADSPI)

All STM32F469xx devices embeds a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can work in direct mode through registers, external flash status register polling mode and memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting 8, 16 and 32-bit access. Code execution is supported. The opcode and the frame format are fully programmable. Communication can be either in Single Data Rate or Dual Data Rate.

2.11 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features:

• 2 displays layers with dedicated FIFO (64x32-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 Input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events.

2.12 DSI Host (DSIHOST)

The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. These interfaces are as follows:

• LTDC interface: – Used to transmit information in Video Mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI). – Through a customized for mode, this interf ace can be used to transmit information in full bandwidth in the Adapted Command Mode (DBI).
• APB slave interface: – Allows the transmission of generic information in Command mode, and follows a proprietary register interface. – Can operate concurrently with either LT DC interface in either Video Mode or Adapted Command Mode.
• Video mode pattern generator: – Allows the transmission of horizontal/ver tical color bar and D-PHY BER testing pattern without any kind of stimuli.

Functional overview STM32F469xx The DSI Host main features:

• Compliant with MIPI® Alliance standards
• Interface with MIPI® D-PHY
• Supports all commands defined in the MIPI® Alliance specification for DCS: – Transmission of all Command mode packets through the APB interface – Transmission of commands in low-power and high-speed during Video Mode
• Supports up to two D-PHY data lanes
• Bidirectional communication and escape mode support through data lane 0
• Supports non-continuous clock in D-PHY clock lane for additional power saving
• Supports Ultra Low-Power mode with PLL disabled
• ECC and Checksum capabilities
• Support for End of Transmission Packet (EoTp)
• Fault recovery schemes
• 3D transmission support
• Configurable selection of system interfaces: – AMBA APB for control and optional support for Generic and DCS commands – Video Mode interface through LTDC – Adapted Command Mode interface through LTDC
• Independently programmable Virtual Channel ID in – Video Mode – Adapted Command Mode – APB Slave Video Mode interfaces features:
• LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2, and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB
• Programmable polarity of all LTDC interface signals
• Extended resolutions beyond the DPI standard maximum resolution of 800x480 pixels: maximum resolution is limited by available DSI physical link bandwidth: – Number of lanes: 2 – Maximum speed per lane: 500Mbps Adapted interface features:
• Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands
• LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2, and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB

STM32F469xx Functional overview Video mode pattern generator:

• Vertical and horizontal color bar generation without LTDC stimuli
• BER pattern without LTDC stimuli

2.13 Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:

• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs.

2.14 Nested vectored inter rupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex ®- M4 with FPU core.

• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency.

2.15 External interrupt/ event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected to the 16 external interrupt lines.

Functional overview STM32F469xx

2.16 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full

temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is 90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz. The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I 2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

2.17 Boot modes

At startup, boot pins are used to select one out of three boot options:

• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details.

2.18 Power supply schemes

• VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. Note: V DD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
• VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers. For example, when device is powered at 1.8V, an independent power supply 3.3V can be connected to V DDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear.

–V DDUSB rising and falling time rate specifications must be respected. supplies both USB transceivers (USB OTG_HS and USB OTG_FS). the other USB transceiver are still supplied by VDDUSB. by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 7. VDDUSB connected to an external independent power supply

• VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D- PHY. This supply must be connected to global VDD.
• VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally to VDD12DSI.
• VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.
• VSSDSI pin is an isolated supply ground used for DSI sub-system.
• If DSI functionality is not used at all, then: – VDDDSI pin must be connected to global VDD. – VCAPDSI pin must be connected extern ally to VDD12DSI but the external capacitor is no more needed. – VSSDSI pin must be grounded. 9''86%B0,1 9''B0,1 WLPH 9''86%B0$; 86%IXQFWLRQDODUHD 9'' 9''$ 86%QRQ IXQFWLRQDO DUHD 9''86% 3RZHURQ 3RZHUGRZQ2SHUDWLQJPRGH 86%QRQ IXQFWLRQDO DUHD

2.19 Power supply supervisor

2.19.1 Internal reset ON

VPOR/PDR or VBOR, without the need for an external reset circuit. message and/or put the MCU into a safe state. The PVD is enabled by software.

2.19.2 Internal reset OFF

reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. connected to VSS, as shown in Figure 8. Figure 8. Power supply supervisor interconnection with internal reset OFF A comprehensive set of power-saving mode allows to design low-power applications.

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages allow to disable the internal reset through the PDR_ON signal when connected to VSS.

Figure 9. PDR_ON control with internal reset OFF

1. PDR_ON signal to be kept always low.

2.20 Voltage regulator

• Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down
• Regulator OFF

2.20.1 Regulator ON

BYPASS_REG low. On all other packages, the regulator is always enabled.

• MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep mode The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode).
• LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode).
• Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on V CAP_1 and VCAP_2 pin. Refer to Section 2.18 and Table 124. All packages have the regulator ON feature.

2.20.2 Regulator OFF

externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Table 3. Voltage regulator configuration mode versus device operating mode(1)

1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when V DD = 1.7 to 2.1 V.

2.20.3 Regulator ON/OFF and inte rnal reset ON/OFF availability

2.21 Real-time clock (RTC), back up SRAM and backup registers

• The real-time clock (RTC)
• 4 Kbytes of backup SRAM
• 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary- coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.22). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when V DD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.22). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

powered either from the VDD supply when present or from the VBAT pin.

2.22 Low-power modes

• Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5): – Normal mode (default mode when MR or LPR is enabled) – Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
• Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

2.23 V BAT operation

Table 5. Voltage regulator modes in stop mode

VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. do not exit it from VBAT operation. more available and VBAT pin should be connected to VDD.

2.24 Timers and watchdogs

timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. Table 6. Timer feature comparison

1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the

Functional overview STM32F469xx

2.24.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for:

• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation.

2.24.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F46x devices (see Table 6 for differences).

• TIM2, TIM3, TIM4, TIM5 The STM32F46x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto- reload up/down counter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

2.24.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation.

2.24.4 Independent watchdog

management. It is hardware- or software-configurable through the option bytes.

2.24.5 Window watchdog

2.24.6 SysTick timer

• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

2.25 Inter-integrated circuit interface (I2C)

generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 7).

2.26 Universal synchronous/asynch ronous receiver transmitters

transmitters (UART4, UART5, UART7, and UART8). Table 7. Comparison of I2C analog and digital filters

Functional overview STM32F469xx communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

2.27 Serial peripheral interface (SPI)

The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s, SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. Table 8. USART feature comparison (RTS/CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s APB mappingOversampling by 16 Oversampling by 8 USART1 X X X X X X 5.62 11.25 APB2 (max.

90 MHz)

USART2 X X X X X X 2.81 5.62 APB1 (max.

45 MHz)

USART3 X X X X X X 2.81 5.62 APB1 (max. UART4 X - X - X - 2.81 5.62 APB1 (max. UART5 X - X - X - 2.81 5.62 APB1 (max. USART6 X X X X X X 5.62 11.25 APB2 (max. UART7 X - X - X - 2.81 5.62 APB1 (max. UART8 X - X - X - 2.81 5.62 APB1 (max.

1. X = feature supported.

STM32F469xx Functional overview

2.28 Inter-integr ated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I 2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. Note: For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port B and GPIO Port D.

2.29 Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio sub-blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. SAI1 can be served by the DMA controller.

2.30 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output).

2.31 Audio and LCD PLL(PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock.

Functional overview STM32F469xx

2.32 Secure digital input/ output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features:

• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F4xx reference manual for details)
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time

2.34 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

STM32F469xx Functional overview FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN.

2.35 Universal serial bus on -the-go full-speed (OTG_FS)

The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

• Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Internal FS OTG PHY support
• HNP/SNP/IP inside (no need for any external resistor) For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

2.36 Universal serial bus on -the-go high-speed (OTG_HS)

The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

Functional overview STM32F469xx The major features are:

• Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

2.37 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image black & white.

2.38 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

2.39 General-purpose in put/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 90 MHz.

STM32F469xx Functional overview

2.40 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold
• Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

2.41 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as V BAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

2.42 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features:

• two DAC converters: one for each output channel
• 8-bit or 10-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• external triggers for conversion
• input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

Functional overview STM32F469xx

2.43 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP .

2.44 Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F46x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools.

3 Pinouts and pin description

Figure 13. STM32F46x LQFP100 pinout

1. The above figure shows the package top view.

Figure 14. STM32F46x LQFP144 pinout

1. The above figure shows the package top view.

Figure 15. STM32F46x WLCSP168 pinout

1. The above figure shows the package bottom view.

Figure 16. STM32F46x UFBGA169 ballout

1. The above figure shows the package top view.

Figure 17. STM32F46x UFBGA176 ballout

1. The above figure shows the package top view.

Figure 18. STM32F46x LQFP176 pinout

1. The above figure shows the package top view.

Figure 19. STM32F46x LQFP208 pinout

1. The above figure shows the package top view.

Figure 20. STM32F46x TFBGA216 ballout

1. The above figure shows the package top view.

Table 9. Legend/abbreviations used in the pinout table

Table 10. STM32F469xx pin and ball definitions

68 F 1 E 1 2 F 1 1 0 1 0 F 1

Table 10. STM32F469xx pin and ball definitions (continued)

1. Function availability depends on the chosen device.
2. NC (not-connected) pins are not bonded. They must be configur ed by software to output push-pull and forced to “0” in the

output data register to avoid extra current consumption in low power modes.

1. PC13, PC14, PC15 and PI8 are supplied through the power switch . Since the switch only sinks a limited amount of current

• The speed should not exceed 2 MHz with a maximum load of 30 pF.
• These I/Os must not be used as a current source (e.g. to drive an LED).

1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
2. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

STM32F469xx Pinouts and pin description 6. If the device is delivered in an WLCSP168, UFBGA169 , UFBGA176, LQFP176 or TFBGA216 package, and the BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low). 7. PI0 and PI1 cannot be used for I2S2 full-duplex mode.

Table 11. FMC pin definition

Table 11. FMC pin definition (continued)

Table 12. Alternate function

1 I2C1_SCL --- - CAN1_RX - ETH_MII_

1 I2C1_SDA SPI2_NSS/I

Table 12. Alternate function (continued)

3 FMC_A23 -- EVENT

4 Memory mapping

The memory map is shown in Figure 21. Figure 21. Memory map

Table 13. STM32F469xx register boundary addresses(1)

Table 13. STM32F469xx register boundary addresses(1) (continued)

1. The reserved boundary address are shown in grayed cells

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

the selected temperature range). mean value plus or minus three times the standard deviation (mean±3σ).

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 22.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 23. Figure 22. Pin loading conditions Figure 23. Pin input voltage

5.1.6 Power supply scheme

Figure 24. Power supply scheme

1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.
2. The two 2.2 µF ceramic capacitors on V CAP_1 and VCAP_2 should be replaced by two 100 nF decoupling

capacitors when the voltage regulator is OFF.

1. The 4.7 µF ceramic capacitor must be connected to one of the V DD pin.
2. V DDA and VSSA must be connected to VDD and VSS, respectively.

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

5.1.7 Current consumption measurement

Figure 25. Current consumption measurement scheme

5.2 Absolute maximum ratings

conditions for extended periods may affect device reliability. Table 14. Voltage characteristics

1. All main power (V DD, VDDA, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to

the external power supply, in the permitted range.

1. V IN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed

Table 15. Current characteristics

1. All main power (V DD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power

supply, in the permitted range.

1. This current consumption must be correctly distri buted over all I/Os and control pins. The total output
2. Positive injection is not possi ble on these I/Os and does not occur for input voltages lower than the
3. A positive injection is induced by V IN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must

never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.

1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the

positive and negative injected currents (instantaneous values). Table 16. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 17. General operating conditions

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. When the ADC is used, refer to Table 76.
3. If V REF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power V DD and VDDA from the same source. A maximum difference of 300 mV between VDD and

VDDA can be tolerated during power-up and power-down operation.

1. The over-drive mode is not supported when the internal regulator is OFF.

Table 17. General operating conditions (continued)

5.3.2 VCAP1/VCAP2 external capacitor

the VCAP1/VCAP2 pins. CEXT is specified in Table 19. Figure 26. External capacitor CEXT

1. Legend: ESR is the equivalent series resistance.
2. To sustain a voltage higher than VDD+0.3, the inter nal Pull-up and Pull-Down resistors must be disabled
3. If T A is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
4. In low power dissipation state, T A can be extended to this range as long as TJ does not exceed TJmax.

Table 18. Limitations depending on the operating power supply range

20 MHz(4)

168 MHz

180 MHz

24 MHz

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
3. Prefetch is not available.
4. When V DDUSB is connected to VDD, the voltage range for USB full speed PHYs can drop down to 2.7 V. However the

electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.

5.3.3 Operating conditi ons at power-up / power-down (regulator ON)

Subject to general operating conditions for TA. Table 20. Operating conditions at power-up / power-down (regulator ON)

5.3.4 Operating conditi ons at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.

5.3.5 Reset and power cont rol block characteristics

temperature and VDD supply voltage conditions summarized in Table 17. Table 19. VCAP1/VCAP2 operating conditions(1)

1. When bypassing the voltage regulator, the two 2.2 µF V CAP capacitors are not required and should be

replaced by two 100 nF decoupling capacitors. Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V DD reach below

Table 22. Reset and power control block characteristics

1. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first

instruction is read by the user application code.

5.3.6 Over-drive switching characteristics

system clock is stalled during the internal voltage set-up. operating conditions for TA.

5.3.7 Supply current characteristics

The current consumption is measured as described in Figure 25. Table 23. Over-drive switching characteristics(1)

50 MHz - 40 -

50 MHz - 15 -

Typical and maximum current consumption The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 18: Limitations depending on the operating power supply range).
• When the regulator is OFF, the V12 is provided externally, as described in Table 17: General operating conditions.
• The voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows: – Scale 3 for f HCLK ≤ 120 MHz – Scale 2 for 120 MHz < f HCLK ≤ 144 MHz – Scale 1 for 144 MHz < f HCLK ≤ 180 MHz. The over-drive is only ON at 180 MHz.
• The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
• External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
• The typical current consumption values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and for ambient temperature TA= 25 °C unless otherwise specified.
• The maximum values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and a maximum ambient temperature (TA), unless otherwise specified.
• For the voltage range 1.7 V ≤ VDD ≤ 2.1 V the maximum frequency is 168 MHz.

1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
3. When the ADC is ON (ADON bit set in the ADC_CR2 regist er), add an additional power consumption of 1.6 mA per ADC
4. Guaranteed by test in production.

1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
3. When the ADC is ON (ADON bit set in the ADC_CR2 regist er), add an additional power consumption of 1.6 mA per ADC

1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, DSI regulator, an additional power

consumption should be considered.

1. When the ADC is ON (ADON bit set in the ADC_CR2 regist er), add an additional power consumption of 1.6 mA per ADC

Table 27. Typical and maximum current consumption in Sleep mode, regulator ON

1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
3. When the ADC is ON (ADON bit set in the ADC_CR2 regist er), add an additional power consumption of 1.6 mA per ADC
4. Guaranteed by test in production.

Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF

1. Guaranteed based on test during characterization.

Table 29. Typical and maximum current consumption in Stop mode

1. Data based on characteriza tion, tested in production.

Table 30. Typical and maximum current consumption in Standby mode

1. PDR is off for V DD=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.

Figure 27. Typical VBAT current consumption Table 31. Typical and maximum current consumption in VBAT mode

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C L of 6 pF for typical values.
2. Based on characterization, tested in production.
3. Based on test during characterization.

Figure 28. Typical VBAT current consumption The current consumption of the I/O system has two components: static and dynamic. the pull-up/pull-down resistors values given in Table 58: I/O static characteristics. estimate the current consumption. configured as analog inputs.

Table 32. Switching output I/O current consumption(1)

• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• I/O compensation cell enabled.
• The ART accelerator is ON.
• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
• HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with only one peripheral clocked on HCLK = 180 MHz (Scale1 + over-drive ON), fHCLK = 144 MHz (Scale 2), fHCLK = 120 MHz (Scale 3)
• Ambient operating temperature is 25 °C and VDD=3.3 V. IDDIO I/O switching Current VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT + CS 2 MHz 0.18 mA 8 MHz 0.67 25 MHz 2.09 50 MHz 3.6 60 MHz 4.5 84 MHz 7.8 90 MHz 9.8 V DD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS 2 MHz 0.26 8 MHz 1.01 25 MHz 3.14 50 MHz 6.39 60 MHz 10.68 VDD = 3.3 V CEXT = 33 pF C = CINT + Cext + CS 2 MHz 0.33 8 MHz 1.29 25 MHz 4.23 50 MHz 11.02 1. C S is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 2. This test is performed by cutting the LQFP176 package pin (pad removal).

Table 32. Switching output I/O current consumption(1) (continued)

Table 33. Peripheral current consumption

180 MHz)

Table 33. Peripheral current consumption (continued)

1. When the I/O compensation cell is ON, I DD typical value increases by 0.22 mA.
2. DMA1/DMA2 current consumption is calculated by the equation. N: is the number of streams enabled,
3. The BusMatrix is automatically active when at least one master is ON.
4. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
5. When the DAC is ON and EN1/2 bits are set in DA C_CR register, add an additional power consumption of

0.8 mA per DAC channel for the analog part.

1. When the ADC is ON (ADON bit set in the ADC_CR 2 register), add an additional power consumption of

1.6 mA per ADC for the analog part.

5.3.8 Wakeup time from low-power modes

• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V.

Table 34. Low-power mode wakeup timings

1. Based on test during characterization.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
3. t WUSTDBY maximum value is given at –40 °C.

5.3.9 External clock source characteristics

waveform is shown in Figure 29. recommended clock input waveform is shown in Figure 30. Table 35. High-speed external user clock characteristics Table 36. Low-speed external user clock characteristics

characteristics (frequency, package, accuracy). design guide for ST microcontrollers” available from www.st.com. Figure 31. Typical application with an 8 MHz crystal

1. R EXT value depends on the crystal characteristics.

Table 37. HSE 4-26 MHz oscillator characteristics (1)

1. This parameter depends on the crystal used in the application. The minimum and maximum values must

be respected to comply with USB standard specifications.

1. t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

characterization results obtained with typical external components specified in Table 38. characteristics (frequency, package, accuracy). design guide for ST microcontrollers” available from www.st.com. Figure 32. Typical application with a 32.768 kHz crystal Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

1. LSE mode cannot be changed “on the fly” other wise, a glitch can be generated on OSCIN pin.
2. This parameter depends on the crystal used in t he application. Refer to application note AN2867.
3. t SU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized

measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

5.3.10 Internal clock source characteristics

ambient temperature and VDD supply voltage conditions summarized in Table 17. Figure 33. ACCHSI vs. temperature

1. Based on test during characterization.

Table 39. HSI oscillator characteristics (1)

1. V DD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on test during characterization.
3. Factory calibrated, parts not soldered.

Figure 34. ACCLSI versus temperature

5.3.11 PLL characteristics

temperature and VDD supply voltage conditions summarized in Table 17. Table 40. LSI oscillator characteristics (1)

1. V DD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on test during characterization.

Table 41. Main PLL characteristics

120 MHz

1. Take care of using the appropriate division factor M to obtai n the specified PLL input clock values. The M factor is shared
2. The use of 2 PLLs in parallel can degrade the Jitter up to +30%.
3. Based on test during characterization.

Table 41. Main PLL characteristics (continued) Table 42. PLLI2S (audio PLL) characteristics

12.288 MHz on 48KHz

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Value given with main PLL running.
3. Based on test during characterization.

Table 42. PLLI2S (audio PLL) characteristics (continued) Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics

12.288 MHz on

12.288 MHz

1. Take care of using the appropriate division fact or M to have the specified PLL input clock values.
2. Value given with main PLL running.
3. Based on test during characterization.

5.3.12 PLL spread spec trum clock generation (SSCG) characteristics

interferences (see Table 54). It is available only on the main PLL. fPLL_IN and fMod must be expressed in Hz. fVCO_OUT must be expressed in MHz. Table 44. SSCG parameters constraint

Tmode is the modulation period. Figure 35. PLL output clock waveforms in center spread mode Figure 36. PLL output clock waveforms in down spread mode

5.3.13 MIPI D-PHY characteristics

temperature and VDD supply voltage conditions summarized in Table 17. Table 45. MIPI D-PHY characteristics(1)

1. Guaranteed based on test during characterization.

Table 45. MIPI D-PHY characteristics(1) (continued)

Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1)

1. Guaranteed based on test during characterization.

Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram

5.3.14 MIPI D-PHY PLL characteristics

VDD supply voltage conditions summarized in Table 17. Table 47. DSI-PLL characteristics(1)

5.3.15 MIPI D-PHY re gulator characteristics

VDD supply voltage conditions summarized in Table 17.

1. Based on test during characterization.

Table 47. DSI-PLL characteristics(1) (continued) Table 48. DSI regulator characteristics(1)

10 MHz escape clock

20 MHz escape clock

300 Mbps - 1 data lane

300 Mbps - 2data lane

500 Mbps - 1 data lane

500 Mbps - 2data lane

1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.

5.3.16 Memory characteristics

The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 49. Flash memory characteristics Table 50. Flash memory programming

1. Based on test during characterization.
2. The maximum programming time is m easured after 100K erase operations.

Table 51. Flash memory programming with VPP

1. The maximum programming time is measured after 100K erase operations.
2. V PP should only be connected during programming/erasing.

Table 50. Flash memory programming (continued)

Table 52. Flash memory endurance and data retention

5.3.17 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization. While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 53. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Symbol Parameter Conditions Value Unit Min(1) 1. Based on test during characterization. NEND Endurance TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 kcycles tRET Data retention 1 kcycle(2) at TA = 85 °C 2. Cycling performed over the whole temperature range. Years1 kcycle(2) at TA = 105 °C 10 10 kcycles(2) at TA = 55 °C 20

Table 53. EMS characteristics

• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC ? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

5.3.18 Absolute maximum ratings (electrical sensitivity)

stressed in order to determine its performance in terms of electrical sensitivity. conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards. Table 54. EMI characteristics enabled, clock dithering disabled.

130 MHz to 1GHz 10 10

130 MHz to 1GHz 8 0

• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard.

5.3.19 I/O current in jection characteristics

sample basis during device characterization. the I/O pin, one at a time, the device is checked for functional failures. leakage current by positive injection. The test results are given in Table 57. Table 55. ESD absolute maximum ratings

1. Guaranteed based on test during characterization.

Table 56. Electrical sensitivities(1)

1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs.

potentially inject negative currents.

5.3.20 I/O port characteristics

Table 57. I/O current injection susceptibility(1) Table 58. I/O static characteristics

1. With a minimum of 200 mV.
2. Leakage could be higher than the maximum value, if negat ive current is injected on adjacent pins, Refer to Table 57
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
4. Pull-up resistors are designed with a true resistance in se ries with a switchable PMOS. This PMOS contribution to the

series resistance is minimum (~10% order).

1. Pull-down resistors are designed with a true resistance in se ries with a switchable NMOS. This NMOS contribution to the

series resistance is minimum (~10% order).

1. Hysteresis voltage between Schmitt trigger switchi ng levels. Based on test during characterization.

Table 58. I/O static characteristics (continued)

coverage of these requirements for FT I/Os is shown in Figure 39. Figure 39. FT I/O input characteristics mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

• The sum of the currents sourced by all the I/Os on V DD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 15).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 15). 069 9'' 9,/9,+ 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,+PLQ 9'' 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' %DVHGRQ'HVLJQVLPXODWLRQV9,/PD[ 9'' 77/UHTXLUHPHQW 9,+PLQ 9 77/UHTXLUHPHQW9,/PD[ $UHDQRW GHWHUPLQHG %DVHGRQ'HVLJQVLPXODWLRQV9,+PLQ 9''

Table 17. All I/Os are CMOS and TTL compliant. Table 59. Output voltage characteristics

1. The I IO current sunk by the device must always respect the absolute maximum rating specified in Table 15.

and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

1. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
2. The I IO current sourced by the device must always respect the absolute maximum rating specified in

Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

1. Based on characterization data.

Table 60. I/O AC characteristics(1)(2)

3.6 V -- 1 0 0 n s

Figure 40. I/O AC characteristics definition

1. The I/O speed is configured using the O SPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of

the GPIOx_SPEEDR GPIO port output speed register.

1. The maximum frequency is defined in Figure 40.
2. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.

Table 60. I/O AC characteristics(1)(2) (continued)

5.3.21 NRST pin characteristics

resistor, RPU (see Table 58). Figure 41. Recommended NRST pin protection

1. The reset network protects t he device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in

Table 61. Otherwise the reset is not taken into account by the device. Table 61. NRST pin characteristics

1. The pull-up is designed with a true resistance in seri es with a switchable PMOS. This PMOS contribution to the series

resistance must be minimum (~10% order).

5.3.22 TIM time r characteristics

external clock, PWM output).

5.3.23 Communications interfaces

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0386 reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. Refer to Section 5.3.20 for more details on the I2C I/O characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Table 62. TIMx characteristics(1)(2)

1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the

Table 63. I2C analog filter characteristics(1)

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). 1. Guaranteed based on test during characterization. 2. Spikes with widths below t AF(min) are filtered. 3. Spikes with widths above t AF(max) are not filtered

Table 64. SPI dynamic characteristics(1)

1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

Table 64. SPI dynamic characteristics(1) (continued)

Figure 44. SPI timing diagram - master mode(1)

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output alternate function characteristics (CK, SD, WS). Note: Refer to the I2S section of RM0386 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital

Table 65. I2S dynamic characteristics(1)

1. Guaranteed based on test during characterization.
2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output alternate function characteristics (SCK,SD,WS).

Table 66. SAI characteristics(1)

1. Guaranteed based on test during characterization.
2. APB clock frequency must be at least twice SAI clock frequency.

This interface is present in both the USB OTG HS and USB OTG FS controllers. observed on PA9 and PB13 when the feature is enabled. Table 67. USB OTG full speed startup time Table 68. USB OTG full speed DC electrical characteristics

1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed

electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.

1. RL is the load connected on the USB OTG full speed drivers.

Figure 49. USB OTG full speed timings: definition of data signal rise and fall time

• Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
• Capacitive load C = 20 pF / 15 pF, unless otherwise specified
• Measurement points are done at CMOS levels: 0.5 VDD. Refer to Section 5.3.20 for more details on the input/output characteristics.

Table 69. USB OTG full speed electrical characteristics(1)

1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

1. No external termination series resistors are requ ired on DP (D+) and DM (D-) pins since the matching

impedance is included in the embedded driver. Table 70. USB HS DC electrical characteristics

1. All the voltages are measured from the local ground potential.

Figure 50. ULPI timing diagram Table 71. USB HS clock timing parameters(1)

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD. Refer to Section 5.3.20 for more details on the input/output characteristics. Table 73 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 51 shows the corresponding timing diagram.

Figure 51. Ethernet SMI timing diagram Table 72. Dynamic characteristics: USB ULPI(1)

1. Guaranteed based on test during characterization.

corresponding timing diagram. Figure 52. Ethernet RMII timing diagram Table 73. Dynamics characteristics: Ethernet MAC signals for SMI(1)

1. Guaranteed based on test during characterization.

corresponding timing diagram. Figure 53. Ethernet MII timing diagram Table 74. Dynamics characteristics: Ethernet MAC signals for RMII(1)

1. Guaranteed based on test during characterization.

Table 75. Dynamics characteristics: Ethernet MAC signals for MII(1)

1. Guaranteed based on test during characterization.

conditions summarized in Table 17. Table 76. ADC characteristics

sampling periods defined in the ADC_SMPR1 register.

1. Based on test during characterization.

REF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

1. R ADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
2. For external triggers, a delay of 1/f PCLK2 must be added to the latency specified in Table 76.

Table 76. ADC characteristics (continued)

Table 77. ADC static accuracy at fADC = 18 MHz(1)

1. Better performance could be achieved in restricted V DD, frequency and temperature ranges.
2. Based on test during characterization.

Table 78. ADC static accuracy at fADC = 30 MHz(1)

1. Better performance could be achieved in restricted V DD, frequency and temperature ranges.
2. Based on test during characterization.

Table 79. ADC static accuracy at fADC = 36 MHz(1)

1. Better performance could be achieved in restricted V DD, frequency and temperature ranges.
2. Based on test during characterization.

ground) to analog pins which may potentially inject negative currents. Section 5.3.20 does not affect the ADC accuracy. Table 80. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)

1. Guaranteed based on test during characterization.

Table 81. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)

1. Guaranteed based on test during characterization.

5.3.25 Temperature sensor characteristics

5.3.26 V BAT monitoring characteristics

5.3.27 Reference voltage

temperature and VDD supply voltage conditions summarized in Table 17. Table 82. Temperature sensor characteristics

1. Based on test during characterization.

Table 83. Temperature sensor calibration values Table 84. VBAT monitoring characteristics

1. Shortest sampling time can be determined in the application by multiple iterations.

Table 85. internal reference voltage

5.3.28 DAC electri cal characteristics

1. Shortest sampling time can be determined in the application by multiple iterations.

Table 85. internal reference voltage (continued) Table 86. Internal reference voltage calibration values Table 87. DAC characteristics pin (when the buffer is ON).

• - ±0.5 LSB Given for the DAC in 10-bit configuration.
• - ±2 LSB Given for the DAC in 12-bit configuration.
• - ±1 LSB Given for the DAC in 10-bit configuration.
• - ±4 LSB Given for the DAC in 12-bit configuration.

1. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
2. Guaranteed based on test during characterization.

Table 87. DAC characteristics (continued)

Figure 58. 12-bit buffered/non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

configuring the BOFFx bit in the DAC_CR register.

5.3.29 FMC characteristics

• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output characteristics. Asynchronous waveforms and timings Figures 59 through 62 represent asynchronous waveforms, and Tables 88 through 95 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF %XIIHUHG1RQEXIIHUHG'$& '$&B287[ %XIIHU ELW GLJLWDOWR DQDORJ FRQYHUWHU DL9

Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings(1)

1. Based on test during characterization.

Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT

1. Based on test during characterization.

Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

1. Based on test during characterization.

Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT

1. Based on test during characterization.

Table 92. Asynchronous multiplexed PSRAM/NOR read timings(1)

1. Based on test during characterization.

Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

1. Based on test during characterization.

Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms Table 94. Asynchronous multiplexed PSRAM/NOR write timings(1)

1. Based on test during characterization.

• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1;
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period:
• For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 90 MHz at CL = 30 pF (on FMC_CLK).
• For 1.71 V≤ VDD<1.9 V, maximum FMC_CLK = 60 MHz at CL = 10 pF (on FMC_CLK).

Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

1. Based on test during characterization.

Figure 63. Synchronous multiplexed NOR/PSRAM read timings

Table 96. Synchronous multiplexed NOR/PSRAM read timings(1)

1. Based on test during characterization.

Figure 64. Synchronous multiplexed PSRAM write timings

Table 97. Synchronous multiplexed PSRAM write timings(1)

1. Based on test during characterization.

Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings Table 98. Synchronous non-multiplexed NOR/PSRAM read timings(1)

1. Based on test during characterization.

Figure 66. Synchronous non-multiplexed PSRAM write timings Table 99. Synchronous non-multiplexed PSRAM write timings(1)

1. Based on test during characterization.

• COM.FMC_SetupTime = 0x01;
• COM.FMC_WaitSetupTime = 0x03;
• COM.FMC_HoldSetupTime = 0x02;
• COM.FMC_HiZSetupTime = 0x01;
• ATT.FMC_SetupTime = 0x01;
• ATT.FMC_WaitSetupTime = 0x03;
• ATT.FMC_HoldSetupTime = 0x02;
• ATT.FMC_HiZSetupTime = 0x01;
• Bank = FMC_Bank_NAND;
• MemoryDataWidth = FMC_MemoryDataWidth_16b;
• ECC = FMC_ECC_Enable;
• ECCPageSize = FMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0;
• Capacitive load C L = 30 pF. In all timing tables, the THCLK is the HCLK clock period.

Figure 67. NAND controller waveforms for read access

Figure 70. NAND controller waveforms for common memory write access

• CL = 30 pF on data and address lines.
• CL = 10 pF on FMC_SDCLK unless otherwise specified.

Table 100. Switching characteristics for NAND Flash read cycles Table 101. Switching characteristics for NAND Flash write cycles

In all timing tables, the THCLK is the HCLK clock period.

• For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at CL = 30 pF (on FMC_SDCLK).
• For 1.71 V≤ VDD <1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and 60 MHz for CAS latency 1 or 2. CL = 10 pF (on FMC_SDCLK).

Figure 71. SDRAM read access waveforms (CL = 1) Table 102. SDRAM read timings(1)

1. Guaranteed based on test during characterization.

Figure 72. SDRAM write access waveforms Table 103. LPSDR SDRAM read timings(1)

1. Guaranteed based on test during characterization.

Table 104. SDRAM write timings(1)

1. Guaranteed based on test during characterization.

Table 105. LPSDR SDRAM write timings(1)

1. Guaranteed based on test during characterization.

5.3.30 Quad-SPI in terface characteristics

• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output alternate function characteristics.

Figure 73. Quad-SPI SDR timing diagram Table 106. Quad-SPI characteristics in SDR mode(1)

1. Guaranteed based on test during characterization.

Figure 74. Quad-SPI DDR timing diagram

5.3.31 Camera interface (D CMI) timing specifications

• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD

Table 107. Quad-SPI characteristics in DDR mode(1)

1. Guaranteed based on test during characterization.

Figure 75. DCMI timing diagram

5.3.32 LCD-TFT controller (LTDC) characteristics

• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD

Table 108. DCMI characteristics(1)

1. 1.Guaranteed based on test during characterization.

Figure 76. LCD-TFT horizontal timing diagram Table 109. LTDC characteristics(1)

1. Based on test during characterization.

Figure 77. LCD-TFT vertical timing diagram

5.3.33 SD/SDIO MMC card host in terface (SDIO) characteristics

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.20 for more details on the input/output characteristics.

Figure 78. SDIO high-speed mode

Figure 79. SD default mode Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)

1. Guaranteed based on test during characterization.

5.3.34 RTC characteristics

Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V(1)(2)

1. Guaranteed based on test during characterization.

Table 112. RTC characteristics

6 Package information

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

6.1 LQFP100 package information

Figure 80. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline

1. Values in inches are converted from mm and rounded to 4 decimal digits.

6.2 LQFP144 package information

Figure 83. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline

1. Values in inches are converted from mm and rounded to 4 decimal digits.

6.3 WLCSP168 package information

Figure 86. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip

Table 115. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bum p diameter parallel to primary datum Z.

6.4 UFBGA169 package information

Figure 87. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

Figure 88. UFBGA169 marking example (package top view)

1. Samples marked "ES" are to be considered as “Engineer ing Samples”: i.e. they are intended to be sent to

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. reliability qualification trials.

1. Values in inches are converted from mm and rounded to 4 decimal digits.

6.5 LQFP176 package information

Figure 89. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline Table 117. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 90. LQFP176 recommended footprint

1. Dimensions are expr essed in millimeters.

Figure 91. LQFP176 marking example (package top view)

1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. reliability qualification trials.

6.6 UFBGA176+25 package information

Figure 92. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, Table 118. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 93. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)

6.7 LQFP208 package information

Figure 94. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline Table 120. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 95. LQFP208 recommended footprint

1. Dimensions are expr essed in millimeters.

Figure 96. LQFP208 marking example (package top view)

1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. reliability qualification trials.

6.8 TFBGA216 package information

Figure 97. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 98. TFBGA216 marking example (package top view)

1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. reliability qualification trials.

6.9 Thermal characteristics

• TA max is the maximum ambient temperature in ° C,
• Θ JA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

Table 122. Package thermal characteristics

7 Part numbering

of this device, please contact your nearest ST sales office. Table 123. Ordering information scheme Chrom-ART graphical accelerator. 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C.

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
• The over-drive mode is not supported. A.1 Operating conditions

Table 124. Limitations depending on the operating power supply range

1. Applicable only when the code is executed from Flas h memory. When the code is executed from RAM, no
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does

performance equivalent to 0 wait state program execution.

2.1 V(3)

1. V DD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to

Section 2.19.1: Internal reset ON).

1.2 Msps

1. Prefetch is not available. Refer to AN3430 applic ation note for details on how to adjust performance and

168 MHz with 8

8 Revision history

Table 125. Document revision history 01-Sep-2015 1 Initial release. availability and Table 54: EMI characteristics. Updated title of Section 6.8: TFBGA216 package information. characteristics and Table 123: Ordering information scheme. Removed former Table 73: Ethernet DC electrical characteristics. STM32F46x LQFP176 pinout and Figure 33: ACCHSI vs. temperature. LQFP144 package information. definitions with footnote 2. Added footnote 3 to Table 14: Voltage characteristics. Updated footnote 1 of Figure 56 and footnote 1 of Figure 57.