695D106X0035G2T

TPS7201Q_07 TI | Alldatasheet

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TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Available in 5-V, 4.85-V, 3.3-V, 3.0-V, and 2.5-V Fixed-Output and Adjustable Versions /C0068Dropout Voltage <85 mV Max at I O = 100 mA (TPS7250) /C0068Low Quiescent Current, Independent of Load, 180 mA Typ /C00688-Pin SOIC and 8-Pin TSSOP Package /C0068Output Regulated to ± 2% Over Full Operating Range for Fixed-Output Versions /C0068Extremely Low Sleep-State Current, 0.5 mA Max /C0068Power-Good (PG) Status Output

description

The TPS72xx family of low-dropout (LDO) voltage regulators offers the benefits of low-dropout voltage, micropower operation, and miniaturized packaging. These regulators feature extremely low dropout voltages and quiescent currents compared to conventional LDO regulators. Offered in small-outline integrated-circuit (SOIC) packages and 8-terminal thin shrink small-outline (TSSOP), the TPS72xx series devices are ideal for cost-sensitive designs and for designs where board space is at a premium. A combination of new circuit design and process innovation has enabled the usual pnp pass transistor to be replaced by a PMOS device. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low – maximum of 85 mV at 100 mA of load current (TPS7250) – and is directly proportional to the load current (see Figure 1). Since the PMOS pass element is a voltage-driven device, the quiescent current is very low (300 mA maximum) and is stable over the entire range of output load current (0 mA to 250 mA). Intended for use in portable systems such as laptops and cellular phones, the low-dropout voltage and micropower operation result in a significant increase in system battery operating life. The TPS72xx also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current to 0.5 mA maximum at T J = 25°C. Other features include a power-good function that reports low output voltage and may be used to implement a power-on reset or a low-battery indicator. The TPS72xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). Copyright  2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SENSE †/FB‡ RESET/PG GND EN OUT OUT IN IN D, P, OR PW PACKAGE (TOP VIEW) † SENSE – Fixed voltage options only (TPS7225, TPS7230, TPS7233, TPS7248, and TPS7250) ‡ FB – Adjustable version only (TPS7201) Figure 1. Typical Dropout Voltage Versus

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2. Typical Application Configuration

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS72xx chip information These chips, when properly assembled, display characteristics similar to the TPS72xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. (6) (4) (3) (7) (2) (1) GND FB /C0277 OUT PG IN EN TPS72xx CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. (6) (7) (2) (5) (4) (3)(1) BONDING PAD ASSIGNMENTS SENSE /C0276(5) NOTE A. For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to the SENSE-pin connection discussion in the application information section of this data sheet. 7 6 5 2 3 † Fixed-voltage options only (TPS7225, TPS7230, TPS7233, TPS7248, and TPS7250) ‡ Adjustable version only (TPS7201) functional block diagram Vref = 1.188 V OUT SENSE ¶/FB EN IN GND PG TPS7201 TPS7225 TPS7230 TPS7233 TPS7248 TPS7250 DEVICE UNITR1 R2 257 357 420 726 756 233 233 233 233 233 W kW kW kW kW kW RESISTOR DIVIDER OPTIONS § Switch positions are shown with EN low (active). ¶ For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to the SENSE-pin connection discussion in application information section. NOTE A: Resistors are nominal values only.1.12 V § §§ MOS transistors Bilpolar transistors Diodes Capacitors Resistors COMPONENT COUNT 108

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)/C0276 † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Note 1 and Figure 3) PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°CPACKAGE A POWER RATING ABOVE T A = 25°C A POWER RATING A POWER RATING A POWER RATING D P 725 mW 1175 mW 5.8 mW/°C 8 74 mW/°C 464 mW 782 mW 377 mW 650 mW 145 mW 301 mWP PW 1175 mW 525 mW 8.74 mW/ °C 4.2 mW/°C 782 mW 336 mW 650 mW 273 mW 301 mW 105 mW DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Note 1 and Figure 4) PACKAGE TC ≤ 25°C DERATING FACTOR TC = 70°C TC = 85°C TC = 125°CPACKAGE C POWER RATING ABOVE T C = 25°C C POWER RATING C POWER RATING C POWER RATING D P 2063 mW 2738 mW 16.5 mW/°C 20 49 mW/°C 1320 mW 1816 mW 1073 mW 1508 mW 413 mW 689 mWP PW 2738 mW 2900 mW 20.49 mW/ °C 23.2 mW/°C 1816 mW 1856 mW 1508 mW 1508 mW 689 mW 580 mW NOTE 1: Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum of 150°C. For guidelines on maintaining junction temperature within the recommended operating range, see application information section. Figure 3 600 400 200 25 50 75 100 800 1000 1200 125 150 1100 900 700 500 300 100 – Maximum Continuous Dissipation – mW MAXIMUM CONTINUOUS DISSIPATION vs FREE-AIR TEMPERATURE PD TA – Free-Air Temperature – °C D Package R qJA = 172°C/W R qJA = 238°C/W P Package R qJA = 114.4°C/W Figure 4 – Maximum Continuous Dissipation – mW MAXIMUM CONTINUOUS DISSIPATION vs CASE TEMPERATURE PD TC – Case Temperature – °C 1500 1000 500 25 50 75 100 2000 2500 3000 125 150 D Package R qJC = 60.6°C/W R qJC = 43.1°C/W P Package R qJC = 48.8°C/W

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN MAX UNIT TPS7201Q 3 10 TPS7225Q 3.65 10 Input voltage VI† TPS7230Q 3.96 10 VInput voltage, VI† TPS7233Q 3.98 10 V TPS7248Q 5.24 10 TPS7250Q 5.41 10 High-level input voltage at EN, VIH 2 V Low-level input voltage at EN, VIL 0.5 V Output current, IO 0 250 mA Operating virtual junction temperature, TJ –40 125 °C † Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation: V I(min)/C0043V O(max) /C0041V DO(max load) Because the TPS7201 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rDS(on) is given in Note 3 under the TPS7201 electrical characteristics table. The minimum value of 3 V is the absolute lower limit for the recommended input-voltage range for the TPS7201.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS72xxQ UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Ground current (active mode) EN ≤ 0.5 V, VI = VO + 1 V, 25°C 180 225 mAGround current (active mode) EN ≤ 0.5 V, 0 mA ≤ IO ≤ 250 mA VI VO + 1 V, –40°C to 125°C 325 mA Input current (standby mode) EN V 3V ≤ V ≤ 10 V 25°C 0.5 mAInput current (standby mode) EN = VI, 3 V ≤ VI ≤ 10 V –40°C to 125°C 1 mA Output current limit threshold VO =0V VI=1 0V 25°C 0.6 1 AO utput current limit threshold VO = 0 V VI = 10 V –40°C to 125°C 1.5 A Pass-element leakage current in EN VI 3V ≤ VI≤ 10 V 25°C 0.5 mAg standby mode EN = VI, 3 V ≤ VI ≤ 10 V –40°C to 125°C 1 mA PG leakage current VPG =1 0V Normal operation 25°C 0.5 mAPG leakage current VPG = 10 V, Normal operation –40°C to 125°C 0.5 mA Output voltage temperature coefficient –40°C to 125°C 31 75 ppm/°C Thermal shutdown junction temperature 165 °C EN logic high (standby mode)

3 V ≤ VI ≤ 6 V

40°Ct o1 2 5°C VEN logic high (standby mode) 6 V ≤ VI ≤ 10 V –40°C to 125°C 2.7 V EN logic low (active mode) 3V ≤ VI≤ 10 V 25°C 0.5 VEN logic low (active mode) 3 V ≤ VI ≤ 10 V –40°C to 125°C 0.5 V EN hysteresis voltage 25°C 50 mV EN input current 0V ≤ VI≤ 10 V 25°C –0.5 0.5 mAEN input current 0 V ≤ VI ≤ 10 V mA Minimum VIfor activepass element 25°C 1.9 2.5 VMinimum VI for active pass element –40°C to 125°C 2.5 V Minimum VIfor valid PG IPG = 300mA 25°C 1.1 1.5 VMinimum VI for valid PG IPG = 300 mA –40°C to 125°C 1.9 V † CSR(compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7201Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS7201Q UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Reference voltage (measuredVI = 3.5 V, IO = 10 mA 25°C 1.188 Vg( at FB with OUT connected to FB)

3 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 250 mA, –40°C to 125°C 1.152 1.224 V Reference voltage temperature coefficient –40°C to 125°C 31 75 ppm/°C VI = 2.4 V,§ 50 mA ≤ IO ≤ 100 mA 25°C 2.1 VI = 2.4 V,§ 100 mA ≤ IO ≤ 200 mA 25°C 2.9 Pass-element series VI=29V 50 mA ≤ IO ≤ 250 mA 25°C 1.6 2.7 Wresistance (see Note 3) VI = 2.9 V, 50 mA ≤ IO ≤ 250 mA –40°C to 125°C 4.5 W VI = 3.9 V, 50 mA ≤ IO ≤ 250 mA 25°C 1 VI = 5.9 V, 50 mA ≤ IO ≤ 250 mA 25°C 0.8 Input regulation VI = 3 V to 10 V, 50 mA ≤ IO ≤ 250 mA, 25°C 23 mVInput regulation I , See Note 2 m O , –40°C to 125°C 36 mV IO = 5 mA to 250 mA,3 V ≤ VI ≤ 10 V, 25°C 15 25 Output regulation O , See Note 2 I , –40°C to 125°C 36 mVO utput regulation IO = 50 mA to 250 mA, 3 V ≤ VI ≤ 10 V, 25°C 17 27 mV O m , See Note 2 I , –40°C to 125°C 43 IO =5 0mA 25°C 49 60 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 32 dBRipple rejection f = 120 H z IO = 250 mA, 25°C 45 50 dB O , See Note 2 –40°C to 125°C 30 Output noise spectral densityf = 120 Hz 25°C 2 mV/√Hz

10 H ≤ f≤ 100 kH

C O = 4.7 mF 25°C 235 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR † =1 W C O = 10 mF 25°C 190 mVrmsCSR † = 1 W C O = 100 mF 25°C 125 PG trip-threshold voltage¶ VFB voltage decreasing from above VPG –40°C to 125°C 0.95× VFB(nom) V PG hysteresis voltage¶ Measured at VFB 25°C 12 mV PG output low voltage¶ IPG = 400mA VI= 2 13 V 25°C 0.1 0.4 VPG output low voltage¶ IPG = 400 mA, VI = 2.13 V –40°C to 125°C 0.4 V FB input current 25°C –10 0.1 10 nAFB input current –40°C to 125°C –20 20 nA † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § This voltage is not recommended. ¶ Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 2. When V I < 2.9 V and IO > 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 3. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figures 10 and 11.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7225Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS7225Q UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage VI = 3.5 V, IO = 10 mA 25°C 2.5 VO utput voltage 3.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 2.45 2.55 V Dropout voltage IO = 250 mA VI= 2 97 V 25°C 560 850 mV D ropout voltage IO = 250 mA , VI = 2.97 V –40°C to 125°C 1.1 V Pass element series resistance(2.97 V – VO )/IO , VI = 2.97 V, 25°C 2.24 3.4 WPass-element series resistance ( O ) O , IO = 250 mA I , –40°C to 125°C 3.84 W Input regulation VI=35Vt o1 0V 50 mA ≤ IO ≤ 250 mA 25°C 9 27 mVInput regulation VI = 3.5 V to 10 V, 50 mA ≤ IO ≤ 250 mA –40°C to 125°C 33 mV IO =5m At o2 5 0m A 35V ≤ VI≤ 10 V 25°C 28 36 Output regulation IO = 5 mA to 250 mA , 3.5 V ≤ VI ≤ 10 V –40°C to 125°C 60 mVO utput regulation IO =5 0mA to 250 mA 35V ≤ VI≤ 10 V 25°C 24 41 mV IO = 50 mA to 250 mA , 3.5 V ≤ VI ≤ 10 V –40°C to 125°C 73 IO =5 0mA 25°C 47 58 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 45 dBRipple rejection f = 120 H z IO = 250 mA 25°C 40 46 dB IO = 250 mA –40°C to 125°C 38 Output noise spectral densityf = 120 Hz 25°C 2 mV/√Hz C O = 4.7 mF 25°C 248 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR † = 1 W C O = 10 mF 25°C 200 mVrmsCSR † = 1 W C O = 100 mF 25°C 130 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 0.95× VO(nom) V PG hysteresis voltage 25°C 50 mV PG output low voltage IPG =12m A VI= 2 13 V 25°C 0.3 0.44 VPG output low voltage IPG = 1.2 mA , VI = 2.13 V –40°C to 125°C 0.5 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7230Q electrical characteristics, IO = 10 mA, VI = 4 V, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS7230Q UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage VI = 4 V, IO = 10 mA 25°C 3 VO utput voltage 4 V≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 2.94 3.06 V IO = 100 mA VI= 2 97 V 25°C 145 185 Dropout voltage IO = 100 mA , VI = 2.97 V –40°C to 125°C 270 mVD ropout voltage IO = 250 mA VI= 2 97 V 25°C 390 502 mV IO = 250 mA , VI = 2.97 V –40°C to 125°C 900 Pass element series resistance(2.97 V – VO )/IO , VI = 2.97 V, 25°C 1.56 2.01 WPass-element series resistance ( O ) O , IO = 250 mA I , –40°C to 125°C 3.6 W Input regulation VI=4Vt o1 0V 50 mA ≤ IO ≤ 250 mA 25°C 9 27 mVInput regulation VI = 4 V to 10 V, 50 mA ≤ IO ≤ 250 mA –40°C to 125°C 33 mV IO =5m At o2 5 0m A 4V ≤ VI≤ 10 V 25°C 34 45 Output regulation IO = 5 mA to 250 mA , 4 V ≤ VI ≤ 10 V –40°C to 125°C 74 mVO utput regulation IO =5 0mA to 250 mA 4V ≤ VI≤ 10 V 25°C 42 60 mV IO = 50 mA to 250 mA , 4 V ≤ VI ≤ 10 V –40°C to 125°C 98 IO =5 0mA 25°C 45 56 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 44 dBRipple rejection f = 120 H z IO = 250 mA 25°C 40 45 dB IO = 250 mA –40°C to 125°C 38 Output noise spectral densityf = 120 Hz 25°C 2 mV/√Hz C O = 4.7 mF 25°C 256 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR † = 1 W C O = 10 mF 25°C 206 mVrmsCSR † = 1 W C O = 100 mF 25°C 132 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 0.95 × VO(nom) V PG hysteresis voltage 25°C 50 mV PG output low voltage IPG =12m A VI= 2 55 V 25°C 0.25 0.44 VPG output low voltage IPG = 1.2 mA , VI = 2.55 V –40°C to 125°C 0.44 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7233Q electrical characteristics, IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS7233Q UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage VI = 4.3 V, IO = 10 mA 25°C 3.3 VO utput voltage 4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 3.23 3.37 V IO =1 0m A VI= 3 23 V 25°C 14 20 IO = 10 mA , VI = 3.23 V –40°C to 125°C 30 Dropout voltage IO = 100 mA VI= 3 23 V 25°C 140 180 mVD ropout voltage IO = 100 mA , VI = 3.23 V –40°C to 125°C 232 mV IO = 250 mA VI= 3 23 V 25°C 360 460 IO = 250 mA , VI = 3.23 V –40°C to 125°C 610 Pass element series resistance(3.23 V – VO )/IO , VI = 3.23 V, 25°C 1.5 1.84 WPass-element series resistance ( O ) O , IO = 250 mA I , –40°C to 125°C 2.5 W Input regulation VI=43Vt o1 0V 50 mA ≤ IO ≤ 250 mA 25°C 8 25 mVInput regulation VI = 4.3 V to 10 V, 50 mA ≤ IO ≤ 250 mA –40°C to 125°C 33 mV IO =5m At o2 5 0m A 43V ≤ VI≤ 10 V 25°C 32 42 Output regulation IO = 5 mA to 250 mA , 4.3 V ≤ VI ≤ 10 V –40°C to 125°C 71 mVO utput regulation IO =5 0mA to 250 mA 43V ≤ VI≤ 10 V 25°C 41 55 mV IO = 50 mA to 250 mA , 4.3 V ≤ VI ≤ 10 V –40°C to 125°C 98 IO =5 0mA 25°C 40 52 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 38 dBRipple rejection f = 120 H z IO = 250 mA 25°C 35 44 dB IO = 250 mA –40°C to 125°C 33 Output noise spectral densityf = 120 Hz 25°C 2 mV/√Hz C O = 4.7 mF 25°C 265 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR † = 1 W C O = 10 mF 25°C 212 mVrmsCSR † = 1 W C O = 100 mF 25°C 135 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 0.95× VO(nom) V PG hysteresis voltage 25°C 32 mV PG output low voltage IPG =12m A VI=28V 25°C 0.22 0.4 VPG output low voltage IPG = 1.2 mA , VI = 2.8 V –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS7248Q electrical characteristics, IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS7248Q UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage VI = 5.85 V, IO = 10 mA 25°C 4.85 VO utput voltage 5.85 V≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 4.75 4.95 V IO =1 0m A VI= 4 75 V 25°C 10 19 IO = 10 mA , VI = 4.75 V –40°C to 125°C 30 Dropout voltage IO = 100 mA VI= 4 75 V 25°C 90 100 mVD ropout voltage IO = 100 mA , VI = 4.75 V –40°C to 125°C 150 mV IO = 250 mA VI= 4 75 V 25°C 216 250 IO = 250 mA , VI = 4.75 V –40°C to 125°C 285 Pass element series resistance(4.75 V – VO )/IO , VI = 4.75 V, 25°C 0.8 1 WPass-element series resistance ( O ) O , IO = 250 mA I , –40°C to 125°C 1.4 W Input regulation VI=58 5Vt o1 0V 50 mA ≤ IO ≤ 250 mA 25°C 34 mVInput regulation VI = 5.85 V to 10 V, 50 mA ≤ IO ≤ 250 mA –40°C to 125°C 50 mV IO =5m At o2 5 0m A 58 5V ≤ VI≤ 10 V 25°C 43 55 Output regulation IO = 5 mA to 250 mA , 5.85 V ≤ VI ≤ 10 V –40°C to 125°C 95 mVO utput regulation IO =5 0mA to 250 mA 58 5V ≤ VI≤ 10 V 25°C 55 75 mV IO = 50 mA to 250 mA , 5.85 V ≤ VI ≤ 10 V –40°C to 125°C 135 IO =5 0mA 25°C 42 53 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 36 dBRipple rejection f = 120 H z IO = 250 mA 25°C 36 46 dB IO = 250 mA –40°C to 125°C 34 Output noise spectral densityf = 120 Hz 25°C 2 mV/√Hz C O = 4.7 mF 25°C 370 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR † = 1 W C O = 10 mF 25°C 290 mVrmsCSR † = 1 W C O = 100 mF 25°C 168 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 0.95 × VO(nom) V PG hysteresis voltage 25°C 50 mV PG output low voltage IPG =12m A VI= 4 12 V 25°C 0.2 0.4 VPG output low voltage IPG = 1.2 mA , VI = 4.12 V –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7250Q electrical characteristics, IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TJ TPS7250Q UNITPARAMETER TEST CONDITIONS ‡ TJ MIN TYP MAX UNIT Output voltage VI = 6 V, IO = 10 mA 25°C 5 VO utput voltage 6 V≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 250 mA –40°C to 125°C 4.9 5.1 V IO =1 0m A VI= 4 88 V 25°C 8 12 IO = 10 mA , VI = 4.88 V –40°C to 125°C 30 Dropout voltage IO = 100 mA VI= 4 88 V 25°C 76 85 mVD ropout voltage IO = 100 mA , VI = 4.88 V –40°C to 125°C 136 mV IO = 250 mA VI= 4 88 V 25°C 190 206 IO = 250 mA , VI = 4.88 V –40°C to 125°C 312 Pass element series resistance(4.88 V – VO )/IO , VI = 4.88 V, 25°C 0.76 0.825 WPass-element series resistance ( O ) O , IO = 250 mA I , –40°C to 125°C 1.25 W Input regulation VI=6Vt o1 0V 50 mA ≤ IO ≤ 250 mA 25°C 28 mVInput regulation VI = 6 V to 10 V, 50 mA ≤ IO ≤ 250 mA –40°C to 125°C 35 mV IO =5m At o2 5 0m A 6V ≤ VI≤ 10 V 25°C 46 61 Output regulation IO = 5 mA to 250 mA , 6 V ≤ VI ≤ 10 V –40°C to 125°C 100 mVO utput regulation IO =5 0mA to 250 mA 6V ≤ VI≤ 10 V 25°C 59 79 mV IO = 50 mA to 250 mA , 6 V ≤ VI ≤ 10 V –40°C to 125°C 150 IO =5 0mA 25°C 41 52 Ripple rejection f = 120 Hz IO = 50 mA –40°C to 125°C 37 dBRipple rejection f = 120 H z IO = 250 mA 25°C 36 46 dB IO = 250 mA –40°C to 125°C 32 Output noise spectral densityf = 120 Hz 25°C 2 mV/√Hz C O = 4.7 mF 25°C 390 Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR † = 1 W C O = 10 mF 25°C 300 mVrmsCSR † = 1 W C O = 100 mF 25°C 175 PG trip-threshold voltage VO voltage decreasing from above VPG –40°C to 125°C 0.95 × VO(nom) V PG hysteresis voltage 25°C 50 mV PG output low voltage IPG =12m A VI= 4 25 V 25°C 0.19 0.4 VPG output low voltage IPG = 1.2 mA , VI = 4.25 V –40°C to 125°C 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TPS72xxY UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Ground current (active mode) EN ≤ 0.5 V, 0 mA ≤ IO ≤ 250 mA VI = VO + 1 V, 180 mA Output current limit threshold VO = 0 V, VI = 10 V 0.6 A Thermal shutdown junction temperature 165 °C EN hysteresis voltage 50 mV Minimum VI for active pass element 1.9 V Minimum VI for valid PG IPG = 300 mA 1.1 V electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), TJ = 25°C, FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TPS7201Y UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Reference voltage (measured at FB with OUT connected to FB) VI = 3.5 V, IO = 10 mA 1.188 V VI = 2.4 V,§ 50 mA ≤ IO ≤ 100 mA 2.1 VI = 2.4 V,§ 100 mA ≤ IO ≤ 200 mA 2.9 Pass-element series resistance (see Note 3) VI = 2.9 V, 50 mA ≤ IO ≤ 250 mA 1.6 W VI = 3.9 V, 50 mA ≤ IO ≤ 250 mA 1 VI = 5.9 V, 50 mA ≤ IO ≤ 250 mA 0.8 Output regulation IO = 5 mA to 250 mA, 15 mVO utput regulation IO = 50 mA to 250 mA, 17 mV VI=35V IO = 50 mA 60 Ripple rejection VI = 3.5 V, f = 120 Hz IO = 250 mA, See Note 2 50 dB Output noise spectral density VI = 3.5 V, f = 120 Hz 2 mV/√Hz VI= 3.5 V, C O = 4.7 mF 235 Output noise voltage VI = 3.5 V,

10 Hz ≤ f ≤ 100 kHz,

C O = 10 mF 190 mVrms CSR † = 1 W C O = 100 mF 125 PG hysteresis voltage¶ VI = 3.5 V, Measured at VFB 12 mV PG output low voltage¶ VI = 2.13 V, IPG = 400 mA 0.1 V FB input current VI = 3.5 V 0.1 nA † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § This voltage is not recommended. ¶ Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 2 When V I < 2.9 V and IO > 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range.

3 To calculate dropout voltage, use equation:

VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figures 10 and 11.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), TJ = 25°C, FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TPS7225Y UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage VI = 3.5 V, IO = 10 mA 2.5 V Dropout voltage VI = 2.97 V, IO = 250 mA 560 mV Pass-element series resistance (2.97 V – VO )/IO , IO = 250 mA VI = 2.97 V, 2.24 W Input regulation VI = 3.5 V to 10 V,50 mA ≤ IO ≤ 250 mA 9 mV Output regulation

3.5 V ≤ VI ≤ 10 V IO = 5 mA to 250 mA 28

3.5 V ≤ VI ≤ 10 V IO = 50 mA to 250 mA 24

Ripple rejection VI = 3.5 V, IO = 50 mA 58 dBRipple rejection I , f = 120 Hz IO = 250 mA 46 dB Output noise spectral density VI = 3.5 V, f = 120 Hz 2 mV/√Hz VI= 3.5 V, C O = 4.7 mF 248 Output noise voltage VI = 3.5 V, CSR † C O = 10 mF 200 mVrms CSR † = 1 W C O = 100 mF 130 PG hysteresis voltage VI = 3.5 V 50 mV PG output low voltage VI = 2.13 V IPG = 1.2 mA 0.3 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ TPS7230Y UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage VI = 4 V, IO = 10 mA 3 V Dropout voltage VI = 2.97 V, IO = 100 mA 145 mVD ropout voltage VI = 2.97 V, IO = 250 mA 390 mV Pass-element series resistance (2.97 V – VO )/IO , IO = 250 mA VI = 2.97 V, 1.56 W Input regulation VI = 4 V to 10 V, 50 mA ≤ IO ≤ 250 mA 9 mV Output regulation

4 V ≤ VI ≤ 10 V IO = 5 mA to 250 mA 34

4 V ≤ VI ≤ 10 V IO = 50 mA to 250 mA 41

Ripple rejection VI = 4 V, IO = 50 mA 56 dBRipple rejection I , f = 120 Hz IO = 250 mA 45 dB Output noise spectral density VI = 4 V, f = 120 Hz 2 mV/√Hz VI= 4V , C O = 4.7 mF 256 Output noise voltage VI = 4 V, CSR † C O = 10 mF 206 mVrms CSR † = 1 W C O = 100 mF 132 PG hysteresis voltage VI = 4 V 50 mV PG output low voltage VI = 2.55 V IPG = 1.2 mA 0.25 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. PARAMETER TEST CONDITIONS ‡ TPS7233Y UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage VI = 4.3 V, IO = 10 mA 3.3 V VI = 3.23 V, IO = 10 mA 14 Dropout voltage VI = 3.23 V, IO = 100 mA 140 mV VI = 3.23 V, IO = 250 mA 360 Pass-element series resistance (3.23 V – VO )/IO , IO = 250 mA VI = 3.23 V, 1.5 W Input regulation VI = 4.3 V to 10 V,50 mA ≤ IO ≤ 250 mA 8 mV Output regulation

4.3 V ≤ VI ≤ 10 V, IO = 5 mA to 250 mA 32

4.3 V ≤ VI ≤ 10 V, IO = 50 mA to 250 mA 41

Ripple rejection VI = 4.3 V, IO = 50 mA 52 dBRipple rejection I , f = 120 Hz IO = 250 mA 44 dB Output noise spectral density VI = 4.3 V, f = 120 Hz 2 mV/√Hz VI= 4.3 V, C O = 4.7 mF 265 Output noise voltage VI = 4.3 V, CSR † C O = 10 mF 212 mVrms CSR † = 1 W C O = 100 mF 135 PG hysteresis voltage VI = 4.3 V 32 mV PG output low voltage VI = 2.8 V, IPG = 1.2 mA 0.22 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 mF (CSR† = 1 W ), TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS ‡ TPS7248Y UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage VI = 5.85 V, IO = 10 mA 4.85 V VI = 4.75 V, IO = 10 mA 10 Dropout voltage VI = 4.75 V, IO = 100 mA 90 mV VI = 4.75 V, IO = 250 mA 216 Pass-element series resistance (4.75 V – VO )/IO , IO = 250 mA VI = 4.75 V, 0.8 W Output regulation

5.85 V ≤ VI ≤ 10 V IO = 5 mA to 250 mA 43

5.85 V ≤ VI ≤ 10 V IO = 50 mA to 250 mA 55

Ripple rejection VI = 5.85 V, IO = 50 mA 53 dBRipple rejection I , f = 120 Hz IO = 250 mA 46 dB Output noise spectral density VI = 5.85 V, f = 120 Hz 2 mV/√Hz VI= 5.85 V, C O = 4.7 mF 370 Output noise voltage VI = 5.85 V, CSR † C O = 10 mF 290 mVrms CSR † = 1 W C O = 100 mF 168 PG hysteresis voltage VI = 5.85 V 50 mV PG output low voltage VI = 4.12 V IPG = 1.2 mA 0.2 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. PARAMETER TEST CONDITIONS ‡ TPS7250Y UNITPARAMETER TEST CONDITIONS ‡ MIN TYP MAX UNIT Output voltage VI = 6 V, IO = 10 mA 5 V VI = 4.88 V IO = 10 mA 8 Dropout voltage VI = 4.88 V IO = 100 mA 76 mV VI = 4.88 V, IO = 250 mA 190 Pass-element series resistance (4.88 V – VO )/IO , IO = 250 mA VI = 4.88 V, 0.76 W Input regulation VI = 6 V to 10 V, 50 mA ≤ IO ≤ 250 mA mV Output regulation

6 V ≤ VI ≤ 10 V, IO = 5 mA to 250 mA 46

6 V ≤ VI ≤ 10 V, IO = 50 mA to 250 mA 59

Ripple rejection VI = 6 V, IO = 50 mA 52 dBRipple rejection I , f = 120 Hz IO = 250 mA 46 dB Output noise spectral density VI = 6 V, f = 120 Hz 2 mV/√Hz VI= 6V , C O = 4.7 mF 390 Output noise voltage VI = 6 V, CSR † C O = 10 mF 300 mVrms CSR † = 1 W C O = 100 mF 175 PG hysteresis voltage VI = 6 V 50 mV PG output low voltage VI = 4.25 V, IPG = 1.2 mA 0.19 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO . ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Table of Graphs FIGURE IQ Quiescent current vs Output current 5 IQ Q uiescent current vs Input voltage 6 DIQ † Change in quiescent current vs Free-air temperature 7 VDO Dropout voltage vs Output current 8 DVDO Change in dropout voltage vs Free-air temperature 9 VDO Dropout voltage (TPS7201 only) vs Output current 10 rDS(on) Pass-element series resistance vs Input voltage 11 DVO Change in output voltage vs Free-air temperature 12 VO Output voltage vs Input voltage 13 Line regulation (TPS7201, TPS7233, TPS7248, TPS7250) 14 Load regulation (TPS7225, TPS7233, TPS7248, TPS7250) VO(PG) Power-good (PG) voltage vs Output voltage 16 rDS(on)PG Power-good (PG) on-resistance vs Input voltage 17 VI Minimum input voltage for valid PG vs Free-air temperature 18 Output voltage response from enable (EN) 19 Load transient response (TPS7201/TPS7233) 20 Load transient response (TPS7248/TPS7250) 21 Line transient response (TPS7201) 22 Line transient response (TPS7233) 23 Line transient response (TPS7248/TPS7250) 24 Ripple rejection vs Frequency 25 Output Spectral Noise Density vs Frequency 26 vs Output current (CO = 4.7 mF) 27 Com pensation series resistance (CSR) vs Added ceramic capacitance (CO = 4.7 mF) 28 Compensation series resistance (CSR) vs Output current (CO = 10 mF) 29 vs Added ceramic capacitance (CO = 10 mF) 30 † This symbol is not currently listed within EIA or JEDEC standards for semiconductor symbology.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Quiescent Current – 200 220 QUIESCENT CURRENT vs OUTPUT CURRENT 230 200 250 170 210 IQ Am IO – Output Current – mA TA = 25°C TPS7248 VI = 10 V TPS7233 VI = 10 V TPS7250 VI = 10 V TPS7248 VI = 5.85 V TPS7250 VI = 6.0 V TPS7233 VI = 4.3 V Figure 6 100 0123456 150 200 QUIESCENT CURRENT vs INPUT VOLTAGE 250 789 1 0 – Quiescent Current – IQ Am VI – Input Voltage – V TA 25°C IO = 250 mA TPS7248 TPS7233 TPS7250 TPS7201 With VO Programmed to 2.5 V Figure 7 – Change in Quiescent Current – CHANGE IN QUIESCENT CURRENT vs FREE-AIR TEMPERATURE D IQ Am –10 –20 –30 – 40 – 40 – 20 0 20 40 60 80 100 120 140 TA – Free-Air Temperature – °C IO = 10 mA VI = VO + 1 V Figure 8 200 0 50 100 150 – Dropout Voltage – mV DROPOUT VOLTAGE vs OUTPUT CURRENT 400 200 250 100 300 VDO IO – Output Current – mA TPS7233 TPS7248 TPS7250 TA = 25°C TPS7230 TPS7225 500 600

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Output Voltage – V 4.5 OUTPUT VOLTAGE vs INPUT VOLTAGE 5.5 78 9 1 0 3.5 2.5 1.5 0.5 VO VI – Input Voltage – V TPS7250 TPS7248 TPS7233 TA = 25°C IO = 250 mA TPS7201 With VO Programmed to 2.5 V D Figure 14 4 4.5 5 6 6.5 7 7.5 LINE REGULATION 8 8.5 9.5 105.5 9 –10 –15 –20 –25 TPS7250 TPS7233 TPS7248 TA = 25°C IO = 250 mA – Change in Output Voltage – mVDVO VI – Input Voltage – V TPS7201 With VO Programmed to 2.5 V Figure 15 0 50 100 150 200 250 –10 –20 –30 –40 –50 IO – Output Current – mA TA = 25°C – Change in Output Voltage – mVDVO TPS7233 TPS7250 TPS7248 TPS7225 LOAD REGULATION Figure 16 POWER-GOOD (PG) VOLTAGE vs OUTPUT VOLTAGE † GND 92 93 94 95 – Power-Good (PG) Voltage – V 96 98 TA = 25°C PG Pulled Up to VI With 5 kW Resistor VO – Output Voltage – % ÁÁ ÁÁ VO(PG) VI † VO as a percent of VO nom.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7201 (WITH VO PROGRAMMED TO 2.5 V) , TPS7233 LOAD TRANSIENT RESPONSE 200 100 –100 –200 – Output Current – mA 105 IO t – Time – ms 0 100 200 300 400 500 TA = 25°C VI = 6 V C I = 0 C O = 4.7 mF (CSR = 1 W ) – Change in Output Voltage – mVDVO Figure 20 LOAD TRANSIENT RESPONSE 200 100 –100 –200 105 TPS7248/TPS7250 t – Time – ms 0 100 200 300 400 500 TA = 25°C VI = 6 V C I = 0 C O = 4.7 mF (CSR = 1 W ) – Change in Output Voltage – mVDVO – Output Current – mAIO Figure 21

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–50 –100 – Input Voltage – V 6.5 6.25 V I TPS7248/TPS7250 t – Time – ms 0 100 200 300 400 500 TA = 25°C C I = 0 C O = 4.7 mF (CSR = 1 W ) – Change in Output Voltage – mVDVO Figure 24 Figure 25 Ripple Rejection – dB f – Frequency – Hz RIPPLE REJECTION vs FREQUENCY 10 100 1 K 10 K 100 K 1 M 10 M TA = 25°C No Input Capacitance Added VI = VO + 1 V IO = 100 mA C O = 4.7 mF (CSR = 1 W ) TPS7233 TPS7201 With VO Programmed to 2.5 V TPS7248/ TPS7250 Figure 26 10 100 1 k 10 k 100 k C O = 10 mF (CSR = 1 W ) C O = 4.7 mF (CSR = 1 W ) C O = 100 mF (CSR = 1 W ) f – Frequency – Hz OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.1 0.01 TA = 25°C No Input Capacitance Added VI = VO + 1 V Output Spectral Noise Density –V/ Hzm

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The design of the TPS72xx family of low-dropout (LDO) regulators is based on the higher-current TPS71xx family. These new families of regulators have been optimized for use in battery-operated equipment and feature extremely low dropout voltages, low supply currents that remain constant over the full-output-current range of the device, and an enable input to reduce supply currents to less than 0.5 mA when the regulator is turned off. device operation The TPS72xx uses a PMOS pass element to dramatically reduce both dropout voltage and supply current over more conventional PNP-pass-element LDO designs. The PMOS transistor is a voltage-controlled device that, unlike a PNP transistor, does not require increased drive current as output current increases. Supply current in the TPS72xx is essentially constant from no-load to maximum. Current limiting and thermal protection prevent damage by excessive output current and/or power dissipation. The device switches into a constant-current mode at approximately 1 A; further load increases reduce the output voltage instead of increasing the output current. The thermal protection shuts the regulator off if the junction temperature rises above 165°C. Recovery is automatic when the junction temperature drops approximately 5°C below the high temperature trip point. The PMOS pass element includes a back diode that safely conducts reverse current when the input voltage level drops below the output voltage level. A logic high on the enable input, EN , shuts off the output and reduces the supply current to less than 0.5 mA. EN should be grounded in applications where the shutdown feature is not used. Power good (PG) is an open-drain output signal used to indicate output-voltage status. A comparator circuit continuously monitors the output voltage. When the output drops to approximately 95% of its nominal regulated value, the comparator turns on and pulls PG low. Transient loads or line pulses can also cause activation of PG if proper care is not taken in selecting the input and output capacitors. Load transients that are faster than 5 ms can cause a signal on PG if high-ESR output capacitors (greater than approximately 7 W ) are used. A 1-ms transient causes a PG signal when using an output capacitor with greater than 3.5 W of ESR. It is interesting to note that the output-voltage spike during the transient can drop well below the reset threshold and still not trip if the transient duration is short. A 1-ms transient must drop at least 500 mV below the threshold before tripping the PG circuit. A 2-ms transient trips PG at just 400 mV below the threshold. Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used when fast transients are expected. A typical application circuit is shown in Figure 31.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.1 mF NOTE A: TPS7225, TPS7230, TPS7233, TPS7248, TPS7250 (fixed-voltage options). SENSE PG OUT OUT IN IN EN GND VI PG CSR = 1 W VO 10 mF TPS72xx (see Note A) 250 kW Figure 31. Typical Application Circuit and the device is located several inches from the power source. transient response of a 5-mA to 85-mA load using a 10-mF output capacitor with a total ESR of 1.7 W .

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IO = 5 mA Ch1 50 mV 50 mA 100 ms/div VI = VO + 1 V IO = 85 mA Figure 32. Load Transient Response (CSR total = 1.7 W ), TPS7248Q † Size is in mm. ESR is maximum resistance in ohms at 100 kHz and TA = 25°C. Listings are sorted by height. a resistor-divider network, and any noise pickup on the PCB trace will feed through to the regulator output. because of the possibility of inducing regulator instability.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 output voltage programming The output voltage of the TPS7201 adjustable regulator is programmed using an external resistor divider as shown in Figure 33. The output voltage is calculated using: V O /C0043V ref/C0064/C04661 /C0041R1 R2 /C0467 (1) Where: Vref = 1.188 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 7-mA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 169 kW to set the divider current at 7 mA and then calculate R1 using: R1 /C0043 /C0466 V O V ref /C00421/C0467/C0064R2 (2) VO VI PG OUT FB GND EN IN <0.4 V >2.7 V TPS7201 Power-Good Indicator 0.1 mF 250 kW OUTPUT VOLTAGE (V) R1 R2 2.5 3.3 3.6 6.4 191 309 348 402 549 750 169 169 169 169 169 169 OUTPUT VOLTAGE PROGRAMMING GUIDE DIVIDER RESISTANCE (kW )† † 1% values shown. 10 mF CSR = 1 W IN5 OUT Figure 33. TPS7201 Adjustable LDO Regulator Programming

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature allowable to avoid damaging the device is 150°C. These restrictions limit the power dissipation that the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max), and the actual dissipation, PD , which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) /C0043 TJmax /C0042TA R /C0113JA Where: TJmax is the maximum allowable junction temperature, i.e.,150°C absolute maximum and 125°C recommended operating temperature. R qJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal SOIC and 238°C/W for the 8-terminal TSSOP. TA is the ambient temperature. The regulator dissipation is calculated using: P D /C0043/C0466V I/C0042V O /C0467/C0064IO Power dissipation resulting from quiescent current is negligible. regulator protection The TPS72xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be appropriate. The TPS72xx also features internal current limiting and thermal protection. During normal operation, the TPS72xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes.

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE 4040082/B 03/95 0.310 (7,87) 0.290 (7,37) 0.010 (0,25) NOM 0.400 (10,60) 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS SLVS102G – MARCH 1995 – REVISED JUNE 2000 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040064/E 08/96 1,20 MAX A 0,19 4,50 4,30 6,20 6,60 0,30 0,75 0,50 0,25 Gage Plane 0,15 NOM 0,65 M0,10 0°–8° 0,10 PINS ** A MIN A MAX DIM 2,90 3,10 4,90 5,10 6,60 6,404,90 5,10 7,70 7,90 9,60 9,80 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS7201QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7201QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7201QPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS7201QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7201QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7225QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7225QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7225QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7225QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7225QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7225QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7225QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7225QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7230QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7230QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7230QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7230QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7230QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7230QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS7230QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7233QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7233QPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS7233QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7233QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7248QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7248QPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS7248QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7248QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7250QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7250QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7250QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7250QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 Addendum-Page 2

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) no Sb/Br) TPS7250QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7250QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TPS7250QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS7250QPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS7250QPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 Addendum-Page 3

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