68HC805K3

68HC805K3 NXP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 119

Technical content

REV. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED 68HC805K3 General Release Specification April 19, 1996 CSIC System Design Group Austin, Texas Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification

MC68HC805K3 — Rev. 1.0 List of Sections 3 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC805K3 List of Sections Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC805K3 — Rev. 1.0

4 List of Sections

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC805K3 Table of Contents Section 1. General Description Section 2. Memory Map Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC805K3 — Rev. 1.0

2.5 User Electronically Erasable Programmable

Section 3. Central Processing Unit Core Section 4. Interrupts Section 5. Resets Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED Section 6. Operational Modes Section 7. Parallel Input/Output Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC805K3 — Rev. 1.0 Section 8. 8-Bit Timer Section 9. Personality EEPROM Section 10. User Program EEPROM Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED Section 11. Instruction Set Section 12. Electrical Specifications Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC805K3 — Rev. 1.0 Section 13. Mechnical Specifications Section 14. Ordering Information Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC805K3 List of Figures Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC805K3 — Rev. 1.0 Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC805K3 List of Tables Table Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC805K3 — Rev. 1.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 General Description 15 General Release Specification — MC68HC805K3 Section 1. General Description

1.1 Contents

1.2 Introduction

The low-cost MC68HC805K3 microcontroller is a member of the M68HC805 Family of microprocessors. This device has 64 bytes of user RAM, 128 bits of personality electronically erasable programmable ROM (PEEPROM), and 928 bytes of user EEPROM. This device is available in the 16-pin plastic dual in-line package (PDIP) and 16-pin small outline integrated circuit (SOIC) package. A functional block diagram of the MC68HC805K3 is shown inFigure 1-2. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Features MC68HC805K3 — Rev. 1.0

16 General Description

1.3 Features

• Low-Cost HC05 Core
• 16-Pin PDIP or SOIC Package
• 928 Bytes of User EEPROM (Including Eight Bytes of User Vectors)
• 64 Bytes of User RAM
• 128 Bits of Personality EEPROM (Not Memory Mapped) Programmed using User Software or during User EEPROM Programming
• On-Chip Charge Pump for In-Circuit Programming of the Personality EEPROM at 3.0 to 5.5 Vdc.
• 8-Bit Free-Running Timer
• 4-Stage Selectable Real-Time Interrupt Generator
• 10 Bidirectional Input/Output (I/O) Lines Including: – 8 mA Sink Capability on Four I/O Pins (PA7–PA4) – Mask Option Register Bit for Software Programmable Pulldowns on All I/O Pins – Mask Option Register Bit for Port Interrupts on Four I/O Pins (PA3–PA0) (Keyboard Scan Feature)
• IRQ Interrupt Hardware Mask, Flag Bit, and Request Bit
• Mask Option Register Bit for Sensitivity on IRQ Interrupt (Edge- and Level-Sensitive or Edge-Sensitive Only)
• On-Chip Oscillator (Mask Option Register Bits for Crystal/Ceramic Resonator Oscillator with Internal 2 MΩ Resistor, and 2-Pin or 3- Pin Resistor Capacitor (RC) Oscillator)
• Mask Option Register Bit for Reduced Startup Delay Time with RC Oscillator Options
• Mask Option Register Bit for Computer Operating Properly (COP) Watchdog System
• Power-Saving Stop and Wait Mode Instructions Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Mask Option Register MC68HC805K3 — Rev. 1.0 General Description 17

• Mask Option Register Bit to Convert STOP Instruction to Halt Mode
• Illegal Address Reset
• Internal Steering Diode and Pullup Resistor onRESET Pin to VDD
• InternalRESET Pin Pulldown from COP Watchdog and ILADR NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high andRESET is active low. Any reference to voltage, current, or frequency specified in the following sections refers to the nominal values. The exact values and their tolerance or limits are specified inSection 12. Electrical Specifications.

1.4 Mask Option Register

The MC68HC805K3 contains these nine programmable options: 1. COP Watchdog Timer (Enable or Disable) 2. IRQ Triggering (Edge-Sensitive or Edge- and Level-Sensitive) 3. Port A Interrupts (Enable or Disable) 4. Port Software Programmable Pulldowns (Enable or Disable) 5. STOP Instruction (Enable or Disable) 6. Oscillator Type (Crystal/Ceramic Resonator or RC) 7. RC Oscillator Type (2-Pin or 3-Pin) 8. RC Oscillator Startup Delay (4064 or 16 fOP Cycles) 9. User EEPROM and PEEP Security (Enable or Disable) NOTE: The startup delay of 16 fOP cycles and the crystal/ceramic resonator oscillator should not be selected together. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Pin Assignments MC68HC805K3 — Rev. 1.0

18 General Description

1.5 Pin Assignments

The MC68HC805K3 is available in 16-pin SOIC and PDIP packages. The pin assignments for these packages are shown inFigure 1-1. Figure 1-1. MC68HC805K3 Pin Assignments 16-PIN SOIC PACKAGE OSC116 OSC215 VSS14 VDD13 PA712 PA611 PA510 PA49 RESET 1 PB1/OCS3 2 PB0 3 IRQ 4 PA0 5 PA1 6 PA2 7 PA3 8 16-PIN PDIP PACKAGE RESET 1 PB1/OSC3 2 PB0 3 IRQ 4 PA0 5 PA1 6 PA2 7 PA3 8 OSC116 OSC215 VSS14 VDD13 PA712 PA611 PA510 PA49 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MCU Structure MC68HC805K3 — Rev. 1.0 General Description 19

1.6 MCU Structure

The overall block diagram of the MC68HC805K3 is shown inFigure 1-2. Figure 1-2. MC68HC805K3 Block Diagram STK PTR DATA DIRECTION REG PORT B WATCHDOG & ILLEGAL ADDRESS DETECT 8-BIT TIMER SYSTEM SELECTABLE OSCILLATOR COND CODE REGISTER 1 1 1 I N Z CH INDEX REGISTER CPU CONTROL 000 1 100000 RESET OSC 1 OSC 2 SRAM — 64 BYTES USER EEPROM — 928 BYTES MASK OPTION REGISTER (MOR) — 10 BITS IRQ ALU 68HC05 CPU ACCUM PROGRAM COUNTER CPU REGISTERS PA7 * PA0 PA1 PA2 PA3 PA4 * PA5 * PA6 * DATA DIRECTION REGISTER PORT A VDD VSS PB0 PB1/OSC3 * 8 mA Sink Capability ** IRQ Interrupt Capability PERSONALITY EEPROM — 128 BITS ON-CHIP CHARGE PUMP ON-CHIP CHARGE PUMP Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Functional Pin Description MC68HC805K3 — Rev. 1.0

20 General Description

1.7 Functional Pin Description

The following paragraphs give a description of the general function of each pin.

1.7.1 V DD and VSS

Power is supplied to the MCU through VDD and VSS . VDD is the positive supply and VSS is ground. The MCU operates from a single power supply. Rapid signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with high-frequency characteristics that are positioned as close to the MCU as possible.

1.7.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the connections for the 2-pin on-chip oscillator. The OSC1 and OSC2 pins also can be used in conjunction with the PB1/OSC3 pin to create a more stable 3-pin RC oscillator. The OSC1, OSC2, and PB1/OSC3 pins can accept these sets of components: 1. A crystal, as shown inFigure 1-3(a) 2. A ceramic resonator, as shown inFigure 1-3(a) 3. An external resistor and capacitor using two pins, as shown in Figure 1-3(b) 4. An external resistor and capacitor using three pins, as shown in Figure 1-3(c) 5. An external clock signal, as shown inFigure 1-3(d) The frequency, fosc, of the oscillator or external clock source is divided by two to produce the internal operating frequency fop. The oscillator type is selected by two mask option register bits. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Functional Pin Description MC68HC805K3 — Rev. 1.0 General Description 21 1.7.2.1 2-Pin Crystal Oscillator The circuit inFigure 1-3(a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, since the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 MΩ is provided between OSC1 and OSC2 when the crystal/ceramic resonator oscillator option is used. Figure 1-3. Oscillator Connections MCU 36 pF* (a) 2-Pin Crystal or Ceramic Resonator Connections OSC1 OSC2 36 pF*

2 MΩ (MASK OPTION)

R UNCONNECTED EXTERNAL CLOCK R C (b) 2-Pin RC Oscillator Connections (d) External Clock Source Connection (c) 3-Pin RC Oscillator Connections C OSC1 OSC2 MCU OSC1 OSC2 MCU OSC1 OSC2 MCU PB1/OSC3 *Starting value only. Follow crystal supplier’s recommendations regarding component values that will provide reliable startup and maximum stability. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Functional Pin Description MC68HC805K3 — Rev. 1.0

22 General Description

1.7.2.2 2-Pin Ceramic Resonator Oscillator In cost-sensitive applications, a ceramic resonator can be used instead of the crystal. The circuit inFigure 1-3(a) is for a ceramic resonator also. The resonator manufacturer’s recommendations should be followed, since the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately

2 MΩ is provided between OSC1 and OSC2 for the crystal/ceramic

resonator oscillator mask option register bit. 1.7.2.3 2-Pin RC Oscillators The 2-pin RC oscillator configuration can be used for very low-cost applications. With this option, a resistor must be connected between the two oscillator pins and a capacitor must be connected from the OSC1 pin to VSS , as shown inFigure 1-3(b). The signal on the OSC2 pin is a square wave and the signal on the OSC1 pin approximates a triangular wave. The 2-pin RC oscillator is selected by programming bit 5 ("RC") of the mask option register located at $0012. Bit 6 ("Pin 3") should NOT be programmed when using the 2-pin oscillator. The 2-pin RC oscillator is optimized for operation at 500 kHz. This oscillator can be used at higher or lower frequencies with degraded accuracy over temperature, supply voltage, and/or device processing variations. The internal startup resistor of approximately 2 MΩ isnot connected between OSC1 and OSC2 when the 2-pin RC oscillator mask option register bit is selected. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Functional Pin Description MC68HC805K3 — Rev. 1.0 General Description 23 1.7.2.4 3-Pin RC Oscillator Another low cost, but more accurate, type of RC oscillator is the 3-pin configuration utilizing the PB1/OSC3 pin. With this option, a resistor must be connected between the OSC1 and OSC2 pins and a capacitor must be connected between the OSC1 and PB1/OSC3 pins, as shown inFigure 1-3(c). This 3-pin RC oscillator is more accurate than the 2-pin RC oscillator with respect to temperature, supply voltage, and/or device processing variations. The signal on the OSC2 and PB1/OSC3 pins is a square wave and the signal on the OSC1 pin approximates a triangular wave. Selection of the 3-bit RC oscillator requires programming two bits in the mask option register located at $0012. Bit 5 ("RC"), when programmed, enables the RC oscillator. Bit 6 ("Pin 3"), when programmed along with bit 5, selects the 3-pin oscillator configuration. The 3-pin RC oscillator is optimized for operation at 500 kHz. This oscillator can be used at higher or lower frequencies with degraded accuracy over temperature, supply voltage, and/or device processing variations. The internal startup resistor of approximately 2 MΩ isnot connected between OSC1 and OSC2 when the 3-pin RC oscillator mask option register bit is selected. The typical external components for a 500- kHz oscillator are a 20-kΩ resistor and a 25- to 30-pF capacitor. NOTE: Capacitors used with the RC oscillators should have minimal leakage. Electrolytic or tantalum capacitors should not be used because they degrade the temperature performance of the oscillator due to excessive variation in their leakage.

1.7.2.5 External Clock

An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown inFigure 1-3(d). This configuration is possible regardless of whether the oscillator is set up for crystal/ceramic resonator, 2-pin RC, or 3-pin RC operation. However, if the 3-pin RC oscillator is selected, the PB1/OSC3 pin also must be left unconnected. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Functional Pin Description MC68HC805K3 — Rev. 1.0

24 General Description

1.7.3 Reset ( RESET)

This pin can be used as an input to reset the MCU to a known startup state by pulling the pin to the low state. TheRESET pin contains a steering diode to discharge any voltage on the pin to VDD when the power is removed. TheRESET pin contains an internal pullup resistor to VDD of approximately 100 kΩ to allow theRESET pin to be left unconnected for low-power applications. TheRESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. The RESET pin has an internal pulldown device that pulls theRESET pin low when there is an internal COP watchdog or an illegal address reset. Refer toSection 5. Resets.

1.7.4 Maskable Interrupt Request ( IRQ)

The IRQ input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a mask option register bit to select either negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the option is selected to include level-sensitive triggering, theIRQ pin requires an external resistor to VDD if “wired-OR” operation is desired. If theIRQ pin is not used, it must be tied to the VDD supply. NOTE: Each of the PA0 through PA3 I/O pins can be connected through an OR gate to the IRQ interrupt function by a common mask option. This capability allows keyboard scan applications where the transitions or levels on the I/O pins behave the same as theIRQ pin, except that the logic level is inverted. The edge or level sensitivity selected by the mask option register bit for theIRQ pin also applies to the I/O pins ORed to create an IRQ signal. The IRQ pin contains an internal Schmitt trigger to improve noise immunity. For more details, seeSection 4. Interrupts. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Functional Pin Description MC68HC805K3 — Rev. 1.0 General Description 25

1.7.5 PA0 through PA7

These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. The four upper-order I/O pins (PA4 through PA7) are capable of sinking higher currents. The four lower-order I/O pins (PA0 through PA3) can be connected via an internal OR gate to the IRQ interrupt function by a mask option register bit. All the port A pins can have software programmable pulldown devices provided by another mask option bit. SeeSection 7. Parallel Input/Output for more details on the I/O ports.

1.7.6 PB0

The state of the PB0 pin is software programmable and is configured as an input during power-on or reset. This pin can have a software programmable pulldown device provided by a mask option register bit. See Section 7. Parallel Input/Output for more details on the I/O ports.

1.7.7 PB1/OSC3

The state of the PB1/OSC3 pin is software programmable and is configured as an input during power-on or reset except when the 3-pin RC oscillator configuration is selected by a pair of mask option register bits. This pin can have a software programmable pulldown device provided by a mask option. SeeSection 7. Parallel Input/Output for more details on the I/O ports. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

26 General Description

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Memory Map 27 General Release Specification — MC68HC805K3 Section 2. Memory Map

2.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Introduction MC68HC805K3 — Rev. 1.0

28 Memory Map

2.2 Introduction

The MC68HC805K3 has several input/output (I/O) features, 64 bytes of user read-only memory (RAM), 128 bits of personality user electronically erasable programmable read-only memory (PEEPROM), and 928 bytes of user EEPROM, which are all active in the single-chip mode as shown inFigure 2-1. Figure 2-1. MC68HC805K3 Single-Chip Mode Memory Map USER VECTORS EEPROM 8 BYTES USER EEPROM

160 BYTES

32 BYTES

64 BYTES

RESET VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) IRQ VECTOR (LOW BYTE) IRQ VECTOR (HIGH BYTE) TIMER VECTOR (LOW BYTE) TIMER VECTOR (HIGH BYTE) $03F8 $03F9 $03FA $03FB $03FC $03FD $03FE $03FF * $0100 TO $03F7 INCLUDES COP RESET ADDRESS $0100 $00FF 0255 0256 I/O $03FF $03F8 $03F7 $00E0 $00DF $0020 $001F $0000 USER EEPROM

760 BYTES *

$00C0 $00BF 1008 $03F0 COP WATCHDOG TIMER Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O and Control Registers MC68HC805K3 — Rev. 1.0 Memory Map 29

2.3 I/O and Control Registers

The I/O and status/control registers reside in locations $0000–$001F. The overall organization of these registers is shown inFigure 2-2. The bit assignments for each register are shown inFigure 2-3 and Figure 2-4. Reading unimplemented bits returns unknown states, and writing to unimplemented bits has no effect. Figure 2-2. MC68HC805K3 I/O Registers Memory Map PORT A DATA REGISTER PORT B DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER TIMER STATUS & CONTROL REGISTER TIMER COUNTER REGISTER PEEPROM STATUS & CONTROL REGISTER RESERVED UNIMPLEMENTED (2) UNIMPLEMENTED (2) UNIMPLEMENTED (3) UNIMPLEMENTED (10) IRQ STATUS & CONTROL REGISTER PORT A PULLDOWN REGISTER PORT B PULLDOWN REGISTER $0000 $0001 $0004 $0005 $0008 $0009 $001F $000A $0010 $0011 $000F$000F PEEPROM BIT SELECT REGISTER $000E MOR REGISTER 1 $0012 $0014 $0013MOR REGISTER 2 RESERVED Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O and Control Registers MC68HC805K3 — Rev. 1.0

30 Memory Map

Addr Name R/W Bit 7 654321 Bit 0 $0000 Port A Data, PORTA R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0W $0001 Port B Data, PORTB R 000000 PB1 PB0W $0002 Unimplemented R W $0003 Unimplemented R W $0004 Port A Data Direction, DDRA R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0W $0005 Port B Data Direction, DDRB R 000000 DDRB1 DDRB0W $0006 Unimplemented R W $0007 Unimplemented R W $0008 Timer Status/Control, TSCR R TOF RTIF TOIE RTIE 00 RT1 RT0W TOFR RTIFR $0009 Timer Counter, TCNTR R TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 W $000A IRQ Status/Control, ISCR R IRQE 0 0 0 IRFQ 0 0 0 W R IRQR $000B Unimplemented R W $000C Unimplemented R W $000D Unimplemented R W $000E Personality EEPROM Bit Select, PEBSR R PEB7 PEB6 PEB5 PEB4 PEB3 PEB2 PDB1 PDB0W $000F Personality EEPROM Status/Control, PESCR R PEDATA PEBULK PEPGM PEBYTE CPEN CPCLK 0 PEPCZF W = Unimplemented R = Reserved Figure 2-3. MC68HC805K3 I/O Registers $0000–$000F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O and Control Registers MC68HC805K3 — Rev. 1.0 Memory Map 31 Addr Name R/W Bit 7 654321 Bit 0 $0010 Port A Pulldown Inhibit, PDRA R W PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 $0011 Port B Pulldown Inhibit, PDRB R W PDIB1 PDIB0 $0012 MOR1 Register R RCSTD PIN3 RC SWAIT SWPDI PIRQ LEVIRQ COPEN W $0013 MOR2 Register R SBIT1 SBIT0 W $0014 Reserved R RRRRRRRRW $0015 Unimplemented R W $0016 Unimplemented R W $0017 Unimplemented R W $0018 Unimplemented R W $0019 Unimplemented R W $001A Unimplemented R W $001B Unimplemented R W $001C Unimplemented R W $001D Unimplemented R W $001E Unimplemented R W $001F Reserved R RRRRRRRRW = Unimplemented R = Reserved Figure 2-4. MC68HC805K3 I/O Registers $0010–$001F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Random-Access Memory (RAM) MC68HC805K3 — Rev. 1.0

32 Memory Map

2.4 Random-Access Memory (RAM)

The total RAM consists of 64 bytes (including the stack) at locations $00C0 through $00FF. The stack pointer can access 32 locations from $00E0 to $00FF. The stack begins at address $00FF and proceeds down to $00E0. Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.

2.5 User Electronically Erasable Programmable Read-Only Memory

A total of 928 bytes of user EEPROM is on chip. This includes 160 bytes in page zero from locations $0020 through $00BF, 760 bytes of user EEPROM with locations $0100 through $03F7 for user program storage, and 8 bytes for user vectors at locations $03F8 through $03FF.

2.6 Mask Option Registers (MOR) $0012 and $0013

The mask option registers consist of 10 EEPROM bits located at $0012 and $0013. These registers hold the option bits for the interrupt sensitivity, COP enable/disable, enable pulldowns/interrupt on port A and port B, interrupts via the lower four bits of port A, STOP instruction as HALT, oscillator type, and security. When in the erased state, the EEPROM cells will read as logic zeros. These registers are refreshed at a rate of 1 ms (typical) using an internal ring oscillator. During STOP and MOR programming, the MOR1 and MOR2 will not be refreshed. $0012 Bit 7 654321 Bit 0 Read: RCSTD PIN3 RC HALT SWPDI PIRQ LEVIRQ COPEN Write: $0013 Bit 7 654321 Bit 0 Read: SBIT1 SBIT0 Write: = Unimplemented Figure 2-5. Mask Option Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Mask Option Registers (MOR) $0012 and $0013 MC68HC805K3 — Rev. 1.0 Memory Map 33 COPEN — COP Enable/Disable READ: Any time WRITE: In user mode, writing has no effect. 1 = The COP is enabled 0 = The COP is disabled (erased state) LEVIRQ — Interrupt Request Option READ: Any time WRITE: In user mode, writing has no effect. 1 = TheIRQ pin is edge and level sensitive 0 = TheIRQ pin is edge sensitive (erased state) PIRQ — Port A IRQ Enable READ: Any time. WRITE: In user mode, writing has no effect. 1 = PA3 through PA0 enabled as external interrupt sources 0 = PA3 through PA0 not enabled as external interrupt sources (erased state) SWPDI — Software Pulldown Inhibit READ: Any time WRITE: In user mode, writing has no effect. 1 = The software pulldown is disabled 0 = The software pulldown is enabled (erased state) HALT — STOP Conversion to Halt Mode READ: Any time WRITE: In user mode, writing has no effect. 1 = The STOP instruction is converted to HALT instruction 0 = STOP instruction is not converted to HALT instruction (erased state) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Mask Option Registers (MOR) $0012 and $0013 MC68HC805K3 — Rev. 1.0

34 Memory Map

RC — RC Oscillator READ: Any time WRITE: In user mode, writing has no effect. 0 = Oscillator configured for external crystal, ceramic resonator, or clock source (erased state) 1 = Oscillator configured for external RC network PIN 3 — Three-Pin RC Oscillator READ: Any time. WRITE: In user mode, writing has no effect. 0 = Two-pin oscillator configured (erased state) 1 = Three-pin oscillator configured RCSTD — RC Oscillator Startup Delay READ: Any time. WRITE: In user mode, writing has no effect. 0 = POR and STOP recovery are 4064 fOP cycles. (erased state) 1 = POR and STOP recovery are 16 fOP cycles. SBIT1 and SBIT0 — Security Bits for User EEPROM and PEEP READ: Any time. WRITE: In user mode, writing has no effect. 01 = EEPROM and PEEP security enabled 11 = EEPROM and PEEP security disabled Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Central Processing Unit Core 35 General Release Specification — MC68HC805K3 Section 3. Central Processing Unit Core

3.1 Contents

3.2 Introduction

The MC68HC805K3 has a 1024-byte memory map. Therefore, it uses only the lower 10 bits of the address bus. In the following discussion, the upper six bits of the address bus can be ignored. Also, by using a mask option register bit, the STOP instruction can be converted from acting as the normal STOP instruction. The stack area also is reduced to 32 bytes due to the limited amount of RAM. Therefore, the stack pointer is reduced to only five bits, only decrements down to $00E0, and then wraps around to $00FF. All other instructions and registers behave as described in M6805 HMOS/M146805 CMOS Family User’s Manual (M6805UM/AD3). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Registers MC68HC805K3 — Rev. 1.0

36 Central Processing Unit Core

3.3 Registers

The MCU contains five registers that are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1. Figure 3-1. M68HC05 Programming Model For a more complete description of the M68HC05 CPU functions, refer toM6805 HMOS, M146805 CMOS Family User’s Manual (M6805UM(AD3), HC05 Applications Guide(M68HC05AG/AD), or Understanding Small Microcontrollers (M68HC05TB/D). Any specific differences in the operation of all CPU registers or bits is described in the following sections. CONDITION CODE REGISTER I A X 452 3 STACK POINTER SP 14 815 9 1213 10 11 PC CC111 1100000000 HN Z C HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT PROGRAM COUNTER INDEX REGISTER ACCUMULATOR 000000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Registers MC68HC805K3 — Rev. 1.0 Central Processing Unit Core 37

3.3.1 Stack Pointer (SP)

The stack pointer shown inFigure 3-1 is a 16-bit register internally. In devices with memory maps less than 64 Kbytes, the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. When accessing memory, the 11 most significant bits are permanently set to 00000000111. The five least significant register bits are appended to these 11 fixed bits to produce an address within the range of $00FF to $00E0. Subroutines and interrupts may use up to 32 ($20) locations. If 32 locations are exceeded, the stack pointer wraps around to $00FF and writes over the previously stored information.

3.3.2 Program Counter (PC)

The program counter shown inFigure 3-1is a 16-bit register internally. The program counter contains the address of the next instruction or operand to be fetched. The six most significant bits of the program counter are ignored internally and appear as 000000 when stacked onto the RAM. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

38 Central Processing Unit Core

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Interrupts 39 General Release Specification — MC68HC805K3 Section 4. Interrupts

4.1 Contents

4.2 Introduction

The MCU can be interrupted four different ways: 1. Non-maskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ) 3. External interrupt via IRQ on PA0-PA3 (enabled by a mask option register bit) 4. Internal timer interrupt (TIMER) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification CPU Interrupt Processing MC68HC805K3 — Rev. 1.0

40 Interrupts

4.3 CPU Interrupt Processing

Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, stacks the current CPU register states, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location, shown inTable 4-1,is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $03F8 through $03FF as defined inTable 4-1. Table 4-1. Vector Addresses for Interrupts and Reset Register Flag Name Interrupts CPU Interrupts Vector Addresses N/A N/A Reset RESET $03FE-$03FF N/A N/A Software SWI $03FC-$03FD ISCR IRQF External Interrupt IRQ $03FA-$03FB TSCR TOF Timer Overflow TIMER $03F8-$03F9 TSCR RTIF Real Time Interrupt TIMER $03F8-$03F9 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Reset Interrupt Sequence MC68HC805K3 — Rev. 1.0

42 Interrupts

Figure 4-2. Interrupt Stacking Order

4.4 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner. A low-level input on theRESET pin or an internally generated RST signal causes the program to vector to its starting address, which is specified by the contents of memory locations $03FE and $03FF. The I bit in the condition code register also is set. The MCU is configured to a known state during this type of reset, as described inSection 5. Resets.

4.5 Software Interrupt (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $03FC and $03FD. CONDITION CODE REGISTER1 1 1 PCH0 0 ACCUMULATOR INDEX REGISTER PCL R E T U R N DECREASING MEMORY ADDRESSES INCREASING MEMORY ADDRESSES UNSTACK STACK I N T E R R U P T 00 0 0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Hardware Interrupts MC68HC805K3 — Rev. 1.0 Interrupts 43

4.6 Hardware Interrupts

All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The two types of hardware interrupts are explained in the following sections.

4.6.1 External Interrupt ( IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown inFigure 4-3. The IRQ pin is one source of an IRQ interrupt, and a mask option register bit is available to enable the four lower order port A pins (PA0 through PA3) to act as other IRQ interrupt sources. All of these sources are combined into a single ORing function that is latched by the IRQ latch. The IRQ latch is set on the falling edge of theIRQ pin or on the rising edge of a PA0 through PA3 pin, if port A interrupts have been enabled by the mask option register bit. Figure 4-3. IRQ Function Block Diagram LATCH R VDD IRQ PIN IRQE IRQ SENSITIVITY MASK OPTION REGISTER BIT IRQF TO IRQ PROCESSING IN CPU IRQ VECTOR FETCH TO BIH & BIL INSTRUCTION SENSING RST PORT A IRQ MASK OPTION REGISTER BIT PA0 PA1 PA2 PA3 IRQR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Hardware Interrupts MC68HC805K3 — Rev. 1.0

44 Interrupts

If the mask option foredge-sensitive only IRQ is used, only the IRQ latch output can activate an IRQF flag which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to these cases:

• If the port A interrupts aredisabled by a mask option register bit, only a falling edge on theIRQ pin initiates an IRQ interrupt.
• If the port A interrupts areenabled by a mask option register bit, these conditions initiate an IRQ interrupt: – A falling edge on theIRQ pin with all the PA0 through PA3 pins at a low level – A rising edge on one PA0 through PA3 pin with all other PA0 through PA3 pins at a low level and theIRQ pin at a high level If the mask option register bit foredge- and level-sensitive IRQ is used, the active high state of the IRQ latch input also can activate an IRQF flag, which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to these cases:
• If the port A Interrupts aredisabled by a mask option register bit, only these conditions initiate an IRQ interrupt: – A low level on theIRQ pin – Falling edge on theIRQ pin
• If the port A interrupts areenabled by a mask option register bit, these conditions initiate an IRQ interrupt: – A low level on theIRQ pin with all the PA0 through PA3 pins at a low level. – Falling edge on theIRQ pin with all the PA0 through PA3 pins at a low level. – High level on any one of the PA0 through PA3 pins with the IRQ pin at a high level. – Rising edge on any PA0 through PA3 pin with all other PA0 through PA3 pins at a low level and theIRQ pin at a high level. The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $03FA and $03FB. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Hardware Interrupts MC68HC805K3 — Rev. 1.0 Interrupts 45 Entering the interrupt service routine automatically clears the IRQ latch. The IRQ interrupt service routine also may clear the IRQ latch by writing a logic one to the IRQR acknowledge bit in the ISCR. As long as the output state of the IRQF flag bit is active, the CPU continuously re-enters the IRQ interrupt sequence following an RTI instruction until the active state is removed or the IRQE enable bit is cleared.

4.6.2 IRQ Status/Control Register (ISCR)

The IRQ interrupt function is controlled by the ISCR located at $000A as shown inFigure 4-4. All unused bits in the ISCR read as logic zeros. A reset clears the IRQF bit and sets the IRQE bit. IRQR — IRQ Interrupt Acknowledge The IRQR acknowledge bit clears an IRQ interrupt request by clearing the IRQ latch. If the IRQ latch is set again while in the IRQ service routine (before an RTI instruction is executed), the CPU re- enters the IRQ interrupt service routine unless the IRQ latch is cleared. Writing a logic one to the IRQR acknowledge bit clears the IRQ latch. Writing a logic zero to the IRQR acknowledge bit has no effect on the IRQ latch. The IRQR acknowledge bit always reads as a logic zero. IRQF — IRQ Interrupt Request The IRQF flag bit indicates that an IRQ request is pending. Writing to the IRQF flag bit has no effect on it. The IRQF flag bit is cleared automatically when the IRQ vector is fetched and the service routine is entered. The IRQF flag bit also can be cleared by writing a logic one to the IRQR acknowledge bit to clear the IRQ latch and also condition $000A Bit 7 654321 Bit 0 Read: IRQE 0 0 0 IRQF 0 0 0 Write: R IRQR Reset: 10000000 = Unimplemented R = Reserved Figure 4-4. IRQ Status/Control Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Hardware Interrupts MC68HC805K3 — Rev. 1.0

46 Interrupts

the external IRQ sources to be inactive if the edge- and level-sensitive mask option register bit is selected. In this way, any additional setting of the IRQF flag bit while in the service routine can be ignored by clearing the IRQF flag bit just before exiting the service routine. If the IRQF flag bit is set again while in the IRQ service routine, the CPU re- enters the IRQ interrupt sequence unless the IRQF flag bit is cleared. The IRQF flag bit is cleared by reset. IRQE — IRQ Interrupt Enable The IRQE bit enables or disables the IRQF flag bit to initiate an IRQ interrupt sequence. If the IRQE enable bit is set, the IRQF flag bit can generate an interrupt sequence. If the IRQE enable bit is cleared, the IRQF flag bit cannot generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I bit is cleared. Execution of the STOP or WAIT instructions causes the IRQE bit to be set to allow the external IRQ to exit these modes. In addition, reset also sets the I bit, which masks all interrupt sources. NOTE: If the I bit is cleared, any instruction that sets the IRQE enable bit when the IRQF flag bit is already set initiates an IRQ interrupt sequence immediately after that instruction.

4.6.3 Port Interrupts (PA0–PA3)

The IRQ interrupt also can be triggered by inputs to PA0 through PA3 port pins as described in4.6.1 External Interrupt (IRQ) if the port interrupts mask option register bit is used. If enabled, the lower four bits of port A can activate the IRQ interrupt function and the interrupt operation is the same as the input to theIRQ pin. The mask option register bit allows all of these input pins to be ORed with the input present on theIRQ pin. All PA0 through PA3 pins must be selected as a group and as an additional IRQ interrupt source. All the port A interrupt sources also are controlled by the IRQE enable bit. NOTE: The BIH and BIL instructions apply only to the level on theIRQ pin itself and not to the output of the logic OR gate with PA0 through PA3 pins. The state of the individual port A pins can be checked by reading the appropriate port A pins as inputs. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Hardware Interrupts MC68HC805K3 — Rev. 1.0 Interrupts 47 NOTE: If port A interrupts are enabled, the state of PA0 through PA3 pins may cause an IRQ interrupt regardless of whether these pins are configured as inputs or outputs. (SeeSection 7. Parallel Input/Output.)

4.6.4 Timer Interrupt (TIMER)

The timer interrupt is generated by the 8-bit timer when either a timer overflow or a real-time interrupt has occurred, as described in Section 8. 8-Bit Timer. The interrupt flags and enable bits for the timer interrupts are in the timer status/control register (TSCR) located at $0008. The I bit in the CCR must be clear for the timer interrupt to be enabled. Either of these two interrupts vector to the same interrupt service routine located at the address specified by the contents of memory locations $03F8 and $03F9. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

48 Interrupts

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Resets 49 General Release Specification — MC68HC805K3 Section 5. Resets

5.1 Contents

5.2 Introduction

The MCU can be reset from four sources: one external input and three internal restart conditions. TheRESET pin is an input with a Schmitt trigger, as shown inFigure 5-1. All the internal peripheral modules that drive external pins are reset by the synchronous reset signal (RST) coming from a latch, which is synchronized to the PH2 bus clock and set by any of the four reset sources. NOTE: Activation of the RST signal generally is referred to as a reset of the device, unless otherwise specified. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Resets MC68HC805K3 — Rev. 1.0

50 Resets

Figure 5-1. Reset Block Diagram

5.3 External Reset (RESET)

The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide noise immunity. This external reset occurs whenever theRESET pin is pulled low and remains in reset until theRESET pin rises to a logic one. This active low input generates the RST signal and resets the CPU and peripherals.

5.4 Internal Resets

The three internally generated resets are the initial power-on reset function, the COP watchdog timer reset, and the illegal address detector reset.

5.4.1 Power-On Reset (POR)

The internal POR is generated on power-up of the internal CPU to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (a “brown-out” condition). After the oscillator becomes active, a mask VDD RST ILLEGAL ADDRESS (ILADR) CPU LATCH RESET COP WATCHDOG (COPR) OSC DATA ADDRESS PH2 TO OTHER PERIPHERALS S POWER-ON RESET (POR)VDD ADDRESS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Resets MC68HC805K3 — Rev. 1.0 Resets 51 option register bit selects an oscillator stabilization delay of 16 or 4064 cycles of the internal processor bus clock (PH2). The POR generates the RST signal that resets the CPU. If any other reset function is active at the end of this stabilization delay, the RST signal remains in the reset condition until the other reset condition(s) end(s).

5.4.2 Computer Operating Properly Reset (COPR)

A COP watchdog timer can be enabled by a mask option register bit. The internal COP reset (COPR) is generated automatically by a timeout of the COP watchdog timer. This timeout occurs if the counter in the COP watchdog timer is not reset (cleared) within a specific time by a user program reset sequence. Refer to8.4 COP Watchdog Timer for more information on this timeout feature. The COPR generates the RST signal that resets the CPU and other peripherals. If any other reset function is active at the end of the COPR reset signal, the RST signal remains in the reset condition until the other reset condition(s) end(s). The COP Watchdog reset activates the internal pulldown device connected to theRESET pin for one cycle of the internal processor bus clock, PH2.

5.4.3 Illegal Address Reset (ILADR)

The internal ILADR reset is generated when an instruction opcode fetch occurs from an address in the I/O address area ($0000 through $001F). The ILADR generates the RST signal that resets the CPU and other peripherals. If any other reset function is active at the end of the ILADR reset signal, the RST signal remains in the reset condition until the other reset condition(s) end(s). The ILADR reset activates the internal pulldown device connected to theRESET pin forone cycle of the internal processor bus clock, PH2. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

52 Resets

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Operational Modes 53 General Release Specification — MC68HC805K3 Section 6. Operational Modes

6.1 Contents

6.2 Introduction

The MC68HC805K3 is capable of running in one of several operational modes to reduce power consumption.

6.3 Low-Power Modes

The WAIT and STOP/HALT instructions provide two low-power operational modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The flow of the stop, halt and wait modes is shown inFigure 6-1.

6.3.1 Stop Mode

The STOP instruction can result in one of two modes of operation depending on its mask option register bit. The mask option register bit can make the STOP instruction operate the same as the STOP instruction in other M68HC05 Family members and place the device in stop mode. Or the mask option register bit can make the STOP instruction behave like a WAIT instruction (except that the restart time involves a delay) and place the device in halt mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Low-Power Modes MC68HC805K3 — Rev. 1.0

54 Operational Modes

The mask option register bit enabling the execution of the STOP instruction places the MCU in its lowest power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including the COP watchdog timer. When the CPU enters stop mode, the interrupt flags (TOF and RTIF) and the interrupt enable bits (TOFE and RTIE) in the TSCR are cleared by internal hardware to remove any pending timer interrupt requests and to disable any further timer interrupts. Execution of the STOP instruction automatically clears the I bit in the condition code register and sets the IRQE enable bit in the IRQ status/control register so that the IRQ external interrupt is enabled. All other memory and registers, including the other bits in the TSCR, remain unaltered. The MCU can be brought out of stop mode only by an IRQ external interrupt, an IRQ from port A (if mask option register bit is enabled), or an externally generated RESET. When exiting stop mode, the internal oscillator resumes after an oscillator stabilization delay of either 16 or 4064 cycles (depending on mask option register bit state) of the internal processor clock. NOTE: If enabled by a mask option register bit, the STOP instruction causes the oscillator to stop and, therefore, disable the COP watchdog timer. If the COP watchdog timer is used and the part is never intended to enter stop mode, the mask option register bit that should be used is the one that disables the STOP instruction and changes the stop mode to the halt mode. See6.3.4 COP Watchdog Timer Considerations for more details. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Low-Power Modes MC68HC805K3 — Rev. 1.0 Operational Modes 55 Figure 6-1. Stop/Halt/Wait Flowcharts 1.FETCH RESET VECTOR OR 2.SERVICE INTERRUPT a.STACK CPU STATE b.SET I BIT C. VECTOR TO INTERRUPT ROUTINE WAIT EXTERNAL RESET? Y N IRQ EXTERNAL INTERRUPT? Y N STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, AND RESET STARTUP DELAY RESTART EXTERNAL OSCILLATOR AND BEGIN STABILIZATION DELAY STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR, AND SET IRQE IN ISCR END OF STARTUP DELAY Y N IRQ EXTERNAL INTERRUPT? Y N EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE RESTART INTERNAL PROCESSOR CLOCK STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR, AND SET IIRQE IN ISCR TIMER INTERNAL INTERRUPT? Y N EXTERNAL RESET? Y N STOP HALT EXTERNAL RESET? Y N IRQ EXTERNAL INTERRUPT? Y N STOP INTERNAL PROCESSOR CLOCK, CLEAR I BIT IN CCR, AND SET IRQE IN ISCR EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE TIMER INTERNAL INTERRUPT? Y N MASK OPTION TO HALT? Y = 1 N = 0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Low-Power Modes MC68HC805K3 — Rev. 1.0

56 Operational Modes

6.3.2 Halt Mode

Execution of the STOP instruction with a mask option register bit to disable the stop mode places the MCU in a low-power halt mode, which consumes more power than stop mode. In halt mode, the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP watchdog timer. Execution of the STOP instruction in the halt mode automatically clears the I bit in the condition code register and sets the IRQE enable bit in the IRQ status/control register so that the IRQ external interrupt is enabled. All other registers, memory, and input/output lines remain in their previous states. If timer interrupts are enabled, a timer interrupt causes the processor to exit halt mode and resume normal operation. Halt mode also can be exited when an external IRQ or external RESET occurs. When exiting halt mode, the internal processor clock resumes after a variable delay. Depending on the mask option register bit state, the maximum oscillator stabilization delay is 16 or 4064 cycles of the internal processor clock. Using the mask option register bit to disable the STOP instruction prevents the STOP instruction from halting the oscillator or affecting the COP watchdog timer similar to wait mode. However, the recovery method introduces some startup delay in the processor clock. NOTE: Halt mode is not intended for normal use, but is provided to keep the COP watchdog timer active if the STOP instruction opcode is executed inadvertently. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Low-Power Modes MC68HC805K3 — Rev. 1.0 Operational Modes 57

6.3.3 Wait Mode

The WAIT instruction places the MCU in a low-power wait mode, which consumes more power than stop mode. In wait mode, the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register and sets the IRQE enable bit in the IRQ status/control register so that the IRQ external interrupt is enabled. All other registers, memory, and input/output lines remain in their previous states. If timer interrupts are enabled, a timer interrupt causes the processor to exit wait mode and resume normal operation. Thus, the timer can be used to generate a periodic exit from wait mode. Wait mode also is exited when an external IRQ or RESET occurs.

6.3.4 COP Watchdog Timer Considerations

If the COP watchdog timer is enabled by the mask option register bit, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) causes the oscillator to halt and prevent the COP watchdog timer from timing out unless the STOP instruction is disabled by a mask option register bit. If the mask option register bit is selected to enable the COP watchdog timer, the COP resets the MCU when it times out. Therefore, it is recommended that the mask option register bit be selected to disable the COP watchdog for a system that must have intentional uses of the wait mode for periods longer than the COP timeout period. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

58 Operational Modes

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Parallel Input/Output 59 General Release Specification — MC68HC805K3 Section 7. Parallel Input/Output

7.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Introduction MC68HC805K3 — Rev. 1.0

60 Parallel Input/Output

7.2 Introduction

In single-chip mode, 10 bidirectional input/output (I/O) lines are arranged as one 8-bit I/O port (port A) and one 2-bit I/O port (port B). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). All port A and port B I/O pins have individual software programmable pulldown devices enabled by a mask option register bit. Some port A pins also have the additional properties of sinking higher current or acting as additional IRQ interrupt input sources. One of the port B pins also may be used as an output for a 3-pin resistor capacitor (RC) oscillator option.

7.3 Port A

Port A is an 8-bit bidirectional port that shares four of its pins with the IRQ interrupt system, as shown inFigure 7-1. Each port A pin is controlled by the corresponding bits in a data direction register, a data register, and a pulldown register. Figure 7-1. Port A I/O Circuitry WRITE $0010 READ $0000 WRITE $0000 READ $0004 DATA REGISTER BIT TO IRQ INTERRUPT SYSTEM (BITS 0-3 ONLY) I/O PINOUTPUT MASK OPTION TO INHIBIT SOFTWARE PULLDOWNS INTERNAL HC05 DATA BUS RESET (RST) WRITE $0004 DATA DIRECTION REGISTER BIT PULLDOWN REGISTER BIT VDD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Port A MC68HC805K3 — Rev. 1.0 Parallel Input/Output 61 The port A DATA register is located at address $0000. The port A data direction register (DDRA) is located at address $0004. The port A pulldown register (PDRA) is located at address $0010. Reset clears both the DDRA and the PDRA. The port A data register is unaffected by reset.

7.3.1 Port A Data Register

Each port A I/O pin has a corresponding bit in the port A data register. When a port A pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port A pin is programmed as an input, any read of the port A data register returns the logic state of the corresponding I/O pin, and any write to the port A data register is saved in the data register, but is not applied to the corresponding I/O pin. The port A data register is unaffected by reset. The port A data register is indeterminant after initial power-up.

7.3.2 Port A Data Direction Register

Each port A I/O pin may be programmed as an input by clearing the corresponding bit in the DDRA or programmed as an output by setting the corresponding bit in the DDRA. When a DDRA bit is set, the corresponding pulldown device is disabled. The DDRA can be accessed at address $0004. The DDRA is cleared by reset.

7.3.3 Port A Pulldown Inhibit Register

All port A I/O pins have software programmable pulldown devices which may be enabled by a mask option register bit. If enabled by mask option register bit, the software programmable pulldowns are activated by clearing their corresponding bit in the PDRA or disabled by setting the corresponding bit in the PDRA. If disabled by a mask option register bit, all pulldowns are disabled. A pulldown on an I/O pin can be activated only if the I/O pin is programmed as an input. Any activated pulldowns on the port A pins are not affected by the VDD supply source to the drivers. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Port A MC68HC805K3 — Rev. 1.0

62 Parallel Input/Output

The PDRA is a write-only register and any reads of location $0010 return undefined results. Since reset clears both the DDRA and the PDRA, all pins initialize as inputs with the pulldown devices active (if enabled by mask option register bit).

7.3.4 Port A LED Drive Capability

The outputs of port A pins 4 through 7 are capable of sinking high current for LED drive capability.

7.3.5 Port A I/O Pin Interrupts

The inputs for the lower four bits of port A can be connected through an OR gate to the IRQ latched input to the CPU by a mask option register bit. When connected as an alternate source of an IRQ interrupt, the port A input pins behave the same as theIRQ pin itself, except that their active state is a logical one or a rising edge. The normalIRQ pin has an active state that is a logical zero or a falling edge depending on the mask option register bit. If the mask option register bit for edge- and level-sensitive interrupts and the mask option register bit for port A interrupts are both used, the presence of a logic one on any one of the lower four port A pins causes an IRQ interrupt request. If the mask option register bit for edge- sensitive-only interrupts and the mask option register bit for port A interrupts are both used, the occurrence of a rising edge on any one of the PA0–PA3 pins causes an IRQ interrupt request, as long as the other PA0–PA3 pins are at a low level. As long as any one of the PA0 through PA3 IRQ inputs remains at a logic one level, or theIRQ remains at a $0010 Bit 7 654321 Bit 0 Read: Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 Reset: 0 0000000 = Unimplemented Figure 7-2. Port A Pulldown Inhibit Register (PDRA) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Port B MC68HC805K3 — Rev. 1.0 Parallel Input/Output 63 logic zero level, the other PA0–PA3 IRQ inputs are effectively ignored. Port interrupts will be generated with the above PA0–PA3 I/O state regardless of whether the port is configured as an input or output. NOTE: The BIH and BIL instructions apply only to the level on theIRQ pin itself, and not to the internal IRQ input to the CPU. Therefore, BIH and BIL cannot be used to test the state of the lower four port A input pins as a group. Each port A interrupt pin can be tested by reading the port A data register at $0000.

7.4 Port B

Port B is a 2-bit bidirectional port that shares one of its pins with the RC oscillator as shown inFigure 7-3. Each port B pin is controlled by the corresponding bits in a data direction register, a data register, and a pulldown register. The port B data register is located at address $0001. The port B data direction register (DDRB) is located at address $0005, and the port B pulldown register (PDRB) is located at address $0011. Reset clears both the DDRB and the PDRB. The port B data register is unaffected by reset.

7.4.1 Port B Data Register

Each port B I/O pin has a corresponding bit in the port B data register. When a port B pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port B pin is programmed as an input, any read of the port B data register returns the logic state of the corresponding I/O pin, and any write to the port B data register is saved in the data register, but not applied to the corresponding I/O pin. Unused bits 2 through 7 are always read as logic zeros, and any write to these bits is ignored. The port B data register is unaffected by reset. The port B data register is indeterminant after initial power-up. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Port B MC68HC805K3 — Rev. 1.0

64 Parallel Input/Output

Figure 7-3. Port B I/O Circuitry WRITE $0011 READ $0001 WRITE $0001 READ $0005 WRITE $0005 WRITE $0001 READ $0001 READ $0005 WRITE $0005 MASK OPTION FOR RC OSCILLATOR FROM 3-PIN RC OSCILLATOR INTERNAL HC05 DATA BUS PB1 OSC3 I/O PINDATA REGISTER BIT OUTPUT DATA DIRECTION REGISTER B MASK OPTION FOR 3-PIN RC OSCILLATOR) DATA REGISTER BIT PB0 PINOUTPUT MASK OPTION TO INHIBIT SOFTWARE PULLDOWNS RESET (RST) DATA DIRECTION REGISTER BIT PULLDOWN REGISTER BIT WRITE $0011 PULLDOWN REGISTER BIT VDD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Port B MC68HC805K3 — Rev. 1.0 Parallel Input/Output 65

7.4.2 Port B Data Direction Register

Each port B I/O pin may be programmed as an input by clearing the corresponding bit in the DDRB or programmed as an output by setting the corresponding bit in the DDRB. When a DDRB bit is set, the corresponding pulldown device is disabled. The DDRB can be accessed at address $0005. Unused bits 2 through 7 are always read as logic zeros, and any write to these bits is ignored. The DDRB is cleared by reset.

7.4.3 Port B Pulldown Inhibit Register

Each port B I/O pin has a software programmable pulldown device which can be enabled by a mask option register bit. If enabled by a mask option register bit, the software programmable pulldowns are activated by clearing the corresponding bit in the PDRB or disabled by setting the corresponding bit in the PDRB. If disabled by a mask option register bit, all pulldowns are disabled. A pulldown on an I/O pin can be activated only if the I/O pin is programmed as an input. The PDRB is a write-only register and any reads of location $0011 return undefined results. Since reset clears both the DDRB and the PDRB, all pins initialize as inputs with the pulldown devices active (if enabled by mask option register bit). $0011 Bit 7 654321 Bit 0 Read: Write: PDIB1 PDIB0 Reset: 0 0 = Unimplemented Figure 7-4. Port B Pulldown Inhibit Register (PDRB) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O Port Programming MC68HC805K3 — Rev. 1.0

66 Parallel Input/Output

7.4.4 Port B with 3-Pin RC Oscillator

The PB1/OSC3 pin may be used as an output from a 3-pin RC oscillator when the mask option register bit for a 3-pin RC oscillator is used. In this case, the following conditions apply:

• The PB1 data register bit can be used as a read/write storage location without affecting the oscillator. PB1 is unaffected by reset.
• The DDRB1 data direction bit can be used as a read/write storage location without affecting the oscillator. DDRB1 is cleared by reset.
• The software programmable pulldown on PB1/OSC3 is disabled, regardless of the mask option register bit selection for the software programmable pulldowns or the state of PDRB1.

7.5 I/O Port Programming

All I/O pins can be programmed as inputs or outputs, with or without pulldown devices.

7.5.1 Pin Data Direction

The direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. The data direction bits DDRB0, DDRB1, and DDRA0 through DDRA7 are read/write bits that can be manipulated with read-modify-write instructions. At power-on or reset, all DDRs are cleared, which configures all port pins as inputs. If the mask option register bit for software programmable pulldowns is selected, all pins initially power-up with their software programmable pulldowns enabled. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O Port Programming MC68HC805K3 — Rev. 1.0 Parallel Input/Output 67

7.5.2 Output Pin

When an I/O pin is programmed as an output pin, the state of the corresponding data register bit determines the state of the pin. The state of the data register bits can be altered by writing to address $0000 for port A and address $0001 for port B. Reads of the corresponding data register bit at address $0000 or $0001 return the state of the data register bit, not the state of the I/O pin itself. Therefore, bit manipulation is possible on all pins programmed as outputs. All pins programmed as outputs have their pulldown devices disabled regardless of the selected mask option register bit for software programmable pulldowns or the state of their PDR bits.

7.5.3 Input Pin

When an I/O pin is programmed as an input pin, the state of the pin can be determined by reading the corresponding data register bit. Any writes to the corresponding data register bit for an input pin is saved by the register bit, but not applied to the corresponding I/O pin until the pin is later programmed to be an output. If the corresponding bit in the pulldown register is clear (and the mask option register bit for software programmable pulldowns is selected), the input pin also has an activated pulldown device. Read-modify-write instructions, such as bit manipulation, should not be used on the pulldown registers, since they are write-only.

7.5.4 I/O Pin Transitions

A “glitch” can be generated on an I/O pin when changing it from an input to an output unless the data register is first pre-conditioned to the desired state before changing the corresponding DDR bit from a zero to a one. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O Port Programming MC68HC805K3 — Rev. 1.0

68 Parallel Input/Output

If the mask option register bit for software programmable pulldowns is selected, a floating input can be avoided by first clearing the pulldown register bit before changing the corresponding DDR from a one to a zero. This ensures that the pulldown device is activated on the pin as the I/O pin changes from a driven output to a pulled low input.

7.5.5 I/O Pin Truth Tables

Every pin on port A and PB0 on port B may be programmed as an input or an output under software control, as shown inTable 7-1 and Table 7-2. All port I/O pins also may have software programmable pulldown devices selected by a mask option register bit. The PB1/OSC3 pin on port B also can be programmed as an input or an output under software control, but it has special considerations when selected by a mask option register bit as an output for the 3-pin RC oscillator, as shown inTable 7-3. Otherwise, PB1/OSC3 behaves the same as PB0. Table 7-1. Port A Pin Functions Software Prog. Pulldown Mask Option Register Bit* PDIAx DDRAx I/O Pin Mode Access to PDRA at $0010 Access to DDRA at $0004 Access to Data Register at $0000 Read Write Read/Write Read Write

1 X 0 IN, Hi-Z U PDIA0–7 DDRA0–7 I/O Pin X

1 X 1 OUT U PDIA0–7 DDRA0–7 PA0–7 PA0–7

0 0 0 IN, Pulldown U PDIA0–7 DDRA0–7 I/O Pin X 0 0 1 OUT U PDIA0–7 DDRA0–7 PA0–7 PA0–7 0 1 0 IN, Hi-Z U PDIA0–7 DDRA0–7 I/O Pin X 0 1 1 OUT U PDIA0–7 DDRA0–7 PA0–7 PA0–7 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification I/O Port Programming MC68HC805K3 — Rev. 1.0 Parallel Input/Output 69 Table 7-2. PB0 Pin Functions Software Prog. Pulldown Mask Option Register Bit* PDIB0 DDRB0 I/O Pin Mode Access to PDRB at $0011 Access to DDRB at $0005 Access to Data Register at $0001 Read Write Read/Write Read Write

1 X 0 IN, Hi-Z U PDIB0 DDRB0 I/O Pin X

1 X 1 OUT U PDIB0 DDRB0 PB0 PB0

0 0 0 IN, Pulldown U PDIB0 DDRB0 I/O Pin X 0 0 1 OUT U PDIB0 DDRB0 PB0 PB0 0 1 0 IN, Hi-Z U PDIB0 DDRB0 I/O Pin X 0 1 1 OUT U PDIB0 DDRB0 PB0 PB0 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled Table 7-3. PB1/OSC3 Pin Functions Mask Option (3-Pin) Software Prog. Pulldown Mask Option Register Bit* PDIB1 DDRB1 I/O Pin Mode Access to PDRB at $0011 Access to DDRB at $0005 Access to Data Register at $0001 Read Write Read/Write Read Write 0 0 1 0 IN, Hi-Z U PDIB1 DDRB1 I/O Pin X 0 0 1 1 OUT U PDIB1 DDRB1 PB1 PB1 000 0 IN, Pulldown U PDIB1 DDRB1 I/O Pin X 0 0 0 1 OUT U PDIB1 DDRB1 PB1 PB1 0 0 0 0 IN, Hi-Z U PDIB1 DDRB1 I/O Pin X 0 0 0 1 OUT U PDIB1 DDRB1 PB1 PB1 1X X X RC OSCOUT U PDIB1 DDRB1 PB1 PB1 NOTES: X is don’t care state U is an undefined state * 1 = pulldowns disabled 2 = pulldowns enabled Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

70 Parallel Input/Output

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 8-Bit Timer 71 General Release Specification — MC68HC805K3 Section 8. 8-Bit Timer

8.1 Contents

8.2 Introduction

The timer for this device is an 8-bit ripple counter. The features include timer overflow, power-on reset (POR), real time interrupt, and COP watchdog timer. This timer is powered down in the stop mode to reduce STOP IDD . As shown inFigure 8-1, the timer is driven by the timer clock, NTF1, divided by four (4). NTF1 has the same phase and frequency as the processor bus clock, PH2, but is not stopped by the wait or halt modes. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the timer counter register (TCNTR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fOP /1024. Two additional stages produce the POR function at fOP /4064 or fOP /16, followed by two more stages, with the resulting clock (fOP /16,384) driving the real time interrupt (RTI) circuit. The RTI circuit consists of three divider stages with a one-of-four selector. The output of the RTI circuit is further divided by eight to drive the optional COP watchdog timer circuit, which can be enabled by a mask option register bit. The RTI rate selector bits, and the RTI and TOF enable bits and flags are located in the timer control and status register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification 8.6 Operating During Wait Mode MC68HC805K3 — Rev. 1.0 72 8-Bit Timer at location $08. The clock frequency that drives the RTI circuit is fOP /214 (or fOP /16384) with three additional divider stages giving a maximum interrupt period of fOP /217 (or fOP /131072). The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 or 16 cycles (depending on mask option register bit), the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. IfRESET is asserted at any time during operation, the counter chain is cleared. Figure 8-1. Timer Block Diagram COPR CLEAR MC68HC05 INTERNAL BUS $09 TCNTR 7-BIT COUNTER INTERRUPT CIRCUIT $08 TSCR RTI SELECT CIRCUITOVERFLOW CIRCUIT DETECT COP WATCHDOG TIMER TO RESET LOGIC TO INTERRUPT LOGIC 8 8 fOP/22 fOP/210 POR TCBP TSCR TCNTR NTF1 INTERNAL TIMER CLOCK (fOP) TOF RTIF TOFE RTIE RT1 RT0 RTIFRTOFR TIMER STATUS/CONTROL REGISTER TIMER COUNTER REGISTER (TCNTR) RESET MOR1,2 REFRESH Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Timer Registers MC68HC805K3 — Rev. 1.0 8-Bit Timer 73

8.3 Timer Registers

The 8-bit timer contains two registers: a timer counter register and a timer status/control register.

8.3.1 Timer Counter Register (TCNTR) $09

The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP divided by 4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The value of each bit of the TCNTR is shown below. This register is cleared by reset. $09 Bit 7 654321 Bit 0 Read: TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Write: Reset: 00000000 = Unimplemented Figure 8-2. Timer Counter Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Timer Registers MC68HC805K3 — Rev. 1.0 74 8-Bit Timer

8.3.2 Timer Status/Control Register (TSCR) $08

The TSCR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. Bit 2 and bit 3 are write- only bits that read as logical zeros.Figure 8-3shows the value of each bit in the TSCR following reset. TOF — Timer Overflow The TOF is a read-only flag bit that is set when the 8-bit ripple counter rolls over from $FF to $00. A timer interrupt request is generated if TOF is set when TOIE is also set. The TOF flag bit is reset by writing a logical one to the TOFR acknowledge bit. Writing to the TOF flag bit has no effect on its value. This bit is cleared by reset. RTIF — Real Time Interrupt Flag The RTIF is a read-only flag bit that is set when the output of the chosen (one-of-four selection) real time interrupt stage goes active. A timer interrupt request is generated if RTIF is set when RTIE is also set. The RTIF flag bit is reset by writing a logical one to the RTIFR acknowledge bit. Writing to the RTIF flag bit has no effect on its value. This bit is cleared by reset. TOIE — Timer Overflow Interrupt Enable The TOIE is an enable bit that allows generation of a timer interrupt. When the TOIE enable bit is set, the TIMER Interrupt is generated when the TOF flag bit is set. This bit is cleared by reset. $08 Bit 7 654321 Bit 0 Read: TOF RTIF TOIE RTIE RT1 RT0 Write: TOFR RTIFR Reset: 00000011 = Unimplemented Figure 8-3. Timer Status/Control Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Timer Registers MC68HC805K3 — Rev. 1.0 8-Bit Timer 75 RTIE — Real Time Interrupt Enable The RTIE is an enable bit that allows the generation of a timer interrupt. When the RTIE enable bit is set and the RTIF flag bit is set, the timer interrupt is generated. The RTIE bit is cleared by reset. TOFR — Timer Overflow Acknowledge The TOFR is an acknowledge bit that resets the TOF flag bit. Writing a logical one to the TOFR clears the TOF flag bit. Reading the TOFR always returns a logical zero. This bit is unaffected by reset. RTIFR — Real Time Interrupt Acknowledge The RTIFR is an acknowledge bit that resets the RTIF flag bit. Writing a logical one to the RTIFR clears the RTIF flag bit. Reading the RTIFR always returns a logical zero. This bit is unaffected by reset. RT1:RT0 — Real Time Interrupt Rate Select The RT0 and RT1 control bits select one-of-four taps for the real time interrupt circuit.Table 8-1shows the available interrupt rates with several fOP values. Both the RT0 and RT1 control bits are set by reset, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF can be missed or an additional RTIF can be generated. To avoid problems, the COP should be cleared just prior to changing RTI taps. Table 8-1. RTI Rates and COP Reset Times RT1:RT0 RTI Rate RTI Period (fOP = 2 MHz) COP Timeout Period (± 1 RTI Period) Minimum COP Timeout Period fOP = 2 MHz) 00 f OP ÷ 214 8.2 ms 8 x RTI Period 57.3 ms 01 f OP ÷ 215 16.4 ms 8 x RTI Period 114.7 ms 10 f OP ÷ 216 32.8 ms 8 x RTI Period 229.4 ms 11 f OP ÷ 217 65.5 ms 8 x RTI Period 458.8 ms Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification COP Watchdog Timer MC68HC805K3 — Rev. 1.0 76 8-Bit Timer

8.4 COP Watchdog Timer

The computer operating properly (COP) watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset times are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the reset vector is fetched. Preventing a COP time out is done by writing a logical zero to the COPC bit at address $03F0 as shown below. The COPR register is shared with a user EEPROM byte. This address location is not affected by any reset signals. Reading this location returns the user EEPROM byte. When the COPC is cleared, only the final four bits used to count eight RTI cycles are cleared. The COP watchdog timer can be enabled/disabled by a mask option register bit.

8.5 Operating During Stop Mode

The timer system is cleared when going into stop mode. When STOP is exited by an external interrupt or an external RESET, the internal oscillator resumes, followed by a 16 or 4064 cycle internal processor oscillator stabilization delay. The timer system counter is then cleared and operation resumes. If the STOP instruction is disabled by mask option register bit to create the halt mode, the effects on the timer are as described in8.6 Operating During Wait Mode. $03F0 Bit 7 654321 Bit 0 Read: Reading $03F0 returns the contents of User EEPROM Write: COPC = Unimplemented Figure 8-4. COPR Watchdog Timer Location Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Operating During Wait Mode MC68HC805K3 — Rev. 1.0 8-Bit Timer 77

8.6 Operating During Wait Mode

The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt or custom periodic interrupt causes the processor to exit the wait mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0 78 8-Bit Timer Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Personality EEPROM 79 General Release Specification — MC68HC805K3 Section 9. Personality EEPROM

9.1 Contents

9.2 Introduction

The MC68HC805K3 contains a 128-bit personality EEPROM (PEEPROM) for storage of variables or user data. These 128 bits are provided as a simple EEPROM array and control logic that requires serial reading of the data. The PEEPROM may be accessed via software programmed into the user EEPROM through two registers that directly interface with the PEEPROM array. The actual implementation of the software varies depending on customer requirements. The PEEPROM array is arranged as 16 bytes (rows) with a separate column select for each bit (column) in a byte. The column select connects the bit to a single sense amplifier as shown in the block diagram of the PEEPROM module inFigure 9-1. An on-chip charge pump is provided to allow programming and erasure of the Personality EEPROM if the supply voltage to the VDD pin is at least 3.0 Vdc. NOTE: Programming and erasure of the personality EEPROM may only be performed if VDD > 3.0 Vdc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification 9.5 PEEPROM Read Access 86Introduction MC68HC805K3 — Rev. 1.0

80 Personality EEPROM

Figure 9-1. Personality EEPROM Block Diagram INTERNAL RING OSCILLATOR VDD 16-TO-1 DECODE & MUX 8-TO-1 DECODE & MUX VPP SWITCH SINGLE SENSE AMP PERSONALITY EEPROM BIT SELECT REGISTER PERSONALITY EEPROM STATUS/CONTROL REGISTER PEDATA PEPGM/PEBYTE/PEBULK 0-2 HC05 DATA BUS 16 x 8 EEPROM ARRAY VPP SWITCH 3-6 ON-CHIP CHARGE PUMP CPEN PEPCZF EACH ROW IS A BYTE CPCLK MUX BUS CLOCK (PH2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Registers MC68HC805K3 — Rev. 1.0 Personality EEPROM 81

9.3 PEEPROM Registers

Two register locations are used to support the EEPROM array. These are the bit select and status/control registers.

9.3.1 PEEPROM Bit Select Register (PEBSR)

The PEEPROM bit select register is located at $000E and contains the enable signals for the rows and columns to access the bits in the EEPROM array. The placement of these bits is shown below. The output of this register is connected to two decoders, one for the array column and one for the array row. A byte in the PEEPROM is defined by the upper four bits in the 7-bit address in the PEBSR (PEB3 through PEB6) and the bit within that byte is defined by the lower three bits in the 7-bit address in the PEBSR (PEB0 through PEB2). The upper bit in the PEBSR (PEB7) may be used as a storage location. All of the bits in the PEBSR register are cleared by reset. Byte (Row) of PEEPROM Bit (Column in Byte (Row) of PEEPROM 3210210 $0E Bit 7 654321 Bit 0 Read: PEB7 PEB6 PEB5 PEB4 PEB3 PEB2 PEB1 PEB0 Write: Reset: 00000000 Figure 9-2. PEBSR Select Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Registers MC68HC805K3 — Rev. 1.0

82 Personality EEPROM

9.3.2 PEEPROM Status/Control Register (PESCR)

The PEEPROM Status/Control Register is located at $000F and contains 5 user bits, as shown inFigure 9-3. Bit 1 is unimplemented and always reads as a logic zero. The states of all bits except PEPCZF and PEDATA are cleared by reset. The PEPCZF is set by reset; and the state of the PEDATA bit following reset is dependent on the stored data in bit 0 of the PEEPROM array. PEPCZF — PEEPROM Column Zero Flag The PEPCZF is a flag bit that is set to a logical one when the first column (COL0) of the EEPROM array is selected. If any other column is selected, the PEPCZF flag bit is cleared. This flag bit can be used to reduce the software code required to access one byte of the PEEPROM. The PEPCZF is set following a reset, since the first column is selected by the reset of the PEBSR. The software code given inTable 9-1is suggested for reading one byte from the PEEPROM. $0F Bit 7 6 5 4 3 2 1 Bit 0 Read: PEDATA PEBULK PEPGM (DATA IN) PEBYTE CPEN CPCLK

0 PEPCZF

Write: Reset: 1 0 0 0 0 0 0 1 = Unimplemented Figure 9-3. PESCR Status/Control Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Registers MC68HC805K3 — Rev. 1.0 Personality EEPROM 83 Table 9-1. Software to Read PEEPROM pebsr equ $000e pescr equ $000f ram equ $000c lda #$xy ; xy is base addresses and should start on sta pebsr ; a first column (i.e., $00, $08, $10, $18, etc). clr ram ; clear ram location used for final result peep_rd rol pescr ; c = pedata (c = carry bit) ror ram ; ram = c inc pebsr ; go to next bit in array. brclr 0,pescr,peep_rd ; care data here, loop until all bytes read ; peep_rd loop ends when PEPCZF = 1. ; At end of loop, ram contains one row of PEEP data. CPCLK — Charge Pump Clock Source The CPCLK bit is a read/write bit that controls the source of the clock for the charge pump. When the CPCLK bit is set, the charge pump is driven by the PH2 bus clock. When the CPCLK bit is cleared, the charge pump is driven from an internal ring oscillator. The CPCLK bit is cleared when the device is in reset. In systems where the desired PH2 clock rate is below 1 MHz, the CPCLK bit should be cleared to enable the internal ring oscillator. Otherwise, the charge pump does not attain sufficient program/erase voltage because the clock source is too slow. CPEN — Charge Pump Enable The CPEN bit is a read/write bit to control the on-chip charge pump for programming and erasure of the Personality EEPROM.This charge pump is only intended for use at VDD supply voltages above 3.0 Vdc. The charge pump is activated when both the CPEN bit is set and one of the program or erase bits is also set (PEPGM, PEBYTE, or PBULK). The charge pump supplies the required programming voltage to the Personality EEPROM array. Once activated, and after startup time tCP , the charge pump continues to operate until all the program and erase bits are cleared. NOTE: If the personality EEPROM is read while the CPEN bit is set, the data is unknown. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Registers MC68HC805K3 — Rev. 1.0

84 Personality EEPROM

The charge pump must always be used to program or erase bits in the Personality EEPROM. The CPEN bit is cleared when the device is in reset. NOTE: Setting the CPEN bit can activate the charge pump. However, all the PEPGM, PEBYTE, PEBULK, and CPEN bits must be cleared to de- activate the charge pump. If the charge pump is left running, the overall device IDD current increases. PEBYTE — PEEPROM Byte Erase The PEBYTE bit is a read/write bit to control the switches that apply the internally provided charge pump programming voltage to a row in the PEEPROM array that is to be erased. When the PEBYTE bit is set to a logical one, a logical zero is stored to all bits in the same row of the PEEPROM array, as specified by the upper four bits of the 7-bit address in the PEBSR. The PEBYTE bit should only be set if the PEPGM and PEBULK bits are cleared. If both the PEBYTE and PEBULK bits are set, the PEEPROM is bulk erased. The PEBYTE bit is cleared when the device is reset. PEPGM — PEEPROM Program Control The PEPGM bit is a read/write bit to control the switches that apply the internally provided charge pump programming voltage to the device in the PEEPROM array that is to be programmed. When the PEPGM bit is set to a logical one, a logical one is stored to the PEEPROM array element specified by the address in the PEBSR. Since the state of the PEPGM bit determines the state of the programmed bit in the PEEPROM array, the PEPGM bit is similar to a DATA IN bit. The PEPGM bit should be set only if the PEBYTE and PEBULK bits are cleared. The PEPGM bit is cleared when the device is reset. NOTE: Only one of the PEPGM, PEBYTE, or PEBULK bits should be set at any one time. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Registers MC68HC805K3 — Rev. 1.0 Personality EEPROM 85 NOTE: Always clear the PEPGM bit before altering the addressing bits in the PEBSR. Otherwise, intermediate locations may be affected if the programming voltage is present. PEBULK — PEEPROM Bulk Erase The PEBULK bit is a read/write bit to control the switches that apply an internally provided programming voltage to all the bits in the PEEPROM array that are to be erased. When the PEBULK bit is set to a logical one, a logical zero is stored to all bits of the PEEPROM array regardless of the bit address specified in the PEBSR. The PEBULK bit should only be set if the PEBYTE and PEPGM bits are cleared. If both the PEBYTE and PEBULK bits are set, the personality EEPROM is bulk erased. The PEBULK bit is cleared when the device is reset. PEDATA — PEEPROM DATA The PEDATA bit is a read-only bit that reflects the state of the PEEPROM sense amplifier. The state of the PEDATA bit is only meaningful when the PEBYTE, PEPGM, PEBULK, and CPEN control bits are all zero. The state of the PEDATA bit following a reset is dependent on the stored data in bit 0 of the PEEPROM array. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Programming MC68HC805K3 — Rev. 1.0

86 Personality EEPROM

9.4 PEEPROM Programming

The PEEPROM can be programmed using a Motorola programmer or in the user application if the VDD supply source is at least 3.0 Vdc. In the latter case, the programming software must be provided in the user EEPROM and use some external pins in either a serial or parallel method for data transfer and/or access. Each bit of the PEEPROM can be programmed as follows: 1. Write the desired bit location to be programmed into the PEBSR located at $000E. 2. Set the PEPGM and CPEN bits in the PESCR located at $000F. 3. Wait for a tEPGM time delay. 4. Clear the PEPGM and CPEN bits. The PEEPROM is then ready to be set up for another bit of data for programming. The programming of a PEEPROM bit only requires access of that bit through the PEBSR followed by setting the PEPGM and CPEN bits in the PESCR. Do not access any bits that are to be left unprogrammed (erased) until all the PEPGM, PEBYTE, PEBULK, and CPEN bits in the PESCR are cleared. Always clear the PEPGM, PEBYTE, PEBULK, and CPEN bits before altering the PEBSR register.

9.5 PEEPROM Read Access

The contents of the PEEPROM are read by the following sequence: 1. Write the desired bit location to be read into the PEBSR located at $000E. 2. Read the state of the PEDATA bit in the PESCR located at $000F. 3. Store the state of the PEDATA bit into RAM or a register. 4. Select another bit by changing the PEBSR. 5. Continue reading and storing the PEDATA bit states until all the required PEEPROM data has been accessed. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification PEEPROM Read Access MC68HC805K3 — Rev. 1.0 Personality EEPROM 87 Reading the PEEPROM is easiest when each row in the PEEPROM array is mapped to contain one byte of data. Selecting a column zero bit selects the first bit in the row; and incrementing the PEEPROM bit select register (PEBSR) selects the next (column 1) bit from the same row. Incrementing the PEBSR seven more times selects the remaining bits of the row and carries over to select column zero of the next row, thereby setting the column zero flag, PEPCZF in the PESCR. The number of increments per row can be controlled by looping on a test of the PEPCZF flag bit. The complete array can be easily accessed by starting with $7F for the PEBSR and decrementing the PEBSR after each access of the PEDATA bit. The decrement sequence can end when the contents of the PEBSR are zero. NOTE: One byte of data from the PEEPROM can be re-created in the PEBSR itself. This can be done if the read routine builds the 8-bit data byte in the index register or the accumulator and then transfers that result to the PEBSR when completed. Subsequent reads of the PEBSR quickly yield that retrieved data byte. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

88 Personality EEPROM

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 User Program EEPROM 89 General Release Specification — MC68HC805K3 Section 10. User Program EEPROM

10.1 Contents

10.2 Introduction

The user EEPROM consists of 920 bytes of user EEPROM from $0020 to $00BF and $0100 to $03F7, and 8 bytes of user vector EEPROM from $03F8 to $03FF. The COP reset address is located within the main EEPROM address space at $03F0. It may be used as a user EEPROM location and is included in the available user EEPROM space previously disclosed.

10.3 EEPROM Programming

The MC68HC805K3 user EEPROM and MOR can only be programmed using the appropriate programming board available from Motorola.

10.4 EEPROM Security

The MC68HC805K3 programmer allows the user to optionally select EEPROM security such that an attempt to enter any non-user operating mode will initiate an automatic bulk erasure of all EEPROM locations including the PEEP. Prior to programming the device, the array is also bulk erased automatically. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0

90 User Program EEPROM

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Instruction Set 91 General Release Specification — MC68HC805K3 Section 11. Instruction Set

11.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Introduction MC68HC805K3 — Rev. 1.0

92 Instruction Set

11.2 Introduction

The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.

11.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Addressing Modes MC68HC805K3 — Rev. 1.0 Instruction Set 93

11.3.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.

11.3.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.

11.3.3 Direct

Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.

11.3.4 Extended

Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Addressing Modes MC68HC805K3 — Rev. 1.0

94 Instruction Set

11.3.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

11.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.

11.3.7 Indexed,16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0 Instruction Set 95

11.3.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.

11.4 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0

96 Instruction Set

11.4.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0 Instruction Set 97

11.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence be- cause it does not write a replacement value. Table 11-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left (Same as LSL) ASL Arithmetic Shift Right ASR Bit Clear BCLR (1) Bit Set BSET (1) Clear Register CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left (Same as ASL) LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST (2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0

98 Instruction Set

11.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0 Instruction Set 99 Table 11-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch ifIRQ Pin High BIH Branch ifIRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0

100 Instruction Set

11.4.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions Instruction Mnemonic Bit Clear BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Bit Set BSET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Types MC68HC805K3 — Rev. 1.0 Instruction Set 101

11.4.5 Control Instructions

These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and EnableIRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable InterruptsWAIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Set Summary MC68HC805K3 — Rev. 1.0

102 Instruction Set

11.5 Instruction Set Summary

Table 11-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ← (A) + (M) ↕×— ↕× ↕↕ IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left (Same as LSL) — — ↕× ↕↕ DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ↕× ↕↕ DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ← 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ← (PC) + 2 +rel ? Z = 1 ————— R E L 2 7 r r 3 BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 +rel ? H = 0 ————— R E L 2 8 r r 3 BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 +rel ? H = 1 ————— R E L 2 9 r r 3 BHI rel Branch if Higher PC ← (PC) + 2 +rel ? C∨ Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Set Summary MC68HC805K3 — Rev. 1.0 Instruction Set 103 BIH rel Branch if IRQ Pin High PC ← (PC) + 2 +rel ? IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 +rel ? IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte (A) ∧ (M) — — ↕× ↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch if Lower orSame PC ← (PC) + 2 +rel ? C∨ Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 +rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ← (PC) + 2 +rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ← (PC) + 2 +rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ← (PC) + 2 +rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ← (PC) + 2 +rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr relBranch if Bit n Clear PC ← (PC) + 2 +rel ? M n = 0 ———— ↕× DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ← (PC) + 2 +rel ? 1 = 0 ————— R E L 2 1 r r 3 BRSET n opr relBranch if Bit n Set PC ← (PC) + 2 +rel ? M n = 1 ———— × ↕ DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BSET n opr Set Bit n Mn ← 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) +rel CLC Clear Carry Bit C ← 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2 Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Set Summary MC68HC805K3 — Rev. 1.0

104 Instruction Set

CLR opr,X CLR ,X Clear Byte M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte (A) – (M) — — ↕× ↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (A) X ← (X) = $FF – (X) M ← (M) = $FF – (M) M ← (M) = $FF – (M) DIR INH INH IX1 IX dd ff CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte (X) – (M) — — ↕××↕ ×↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff INC opr INCA INCX INC opr,X INC ,X Increment Byte M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ← Jump Address ————— DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Set Summary MC68HC805K3 — Rev. 1.0 Instruction Set 105 JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP← (SP) – 1 Push (PCH); SP← (SP) – 1 PC ← Effective Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ← (M) — — ↕× ↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ← (M) — — ↕× ↕×— IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left (Same as ASL) — — ↕× ↕↕ DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 ↕↕ DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ← (X)× (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) DIR INH INH IX1 IX dd ff NOP No Operation ————— I N H 9 D 2 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory A ← (A)∨ (M) — — ↕× ↕ — IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left through Carry Bit — — ↕× ↕↕ DIR INH INH IX1 IX dd ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 C b0b7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Set Summary MC68HC805K3 — Rev. 1.0

106 Instruction Set

ROR opr,X ROR ,X Rotate Byte Right through Carry Bit — — ↕× ↕↕ DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ← $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL)————— I N H 8 1 6 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ← 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in Memory M ← (A) — — ↕× ↕ — DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ← (X) — — ↕× ↕ — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator A ← (A) – (M) — — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register X ← ( A ) ————— I N H 9 7 2 Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Instruction Set Summary MC68HC805K3 — Rev. 1.0 Instruction Set 107 TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 — — ↕↕ — DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator A ← ( X ) ————— I N H 9 F 2 WAIT Stop CPU Clock and Enable Interrupts — 0× — — — INH 8F 2 A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask ∧ Logical AND ii Immediate operand byte ∨ Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag ↕ Set or cleared n Any bit — Not affected Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Instruction Set Summary MC68HC805K3 — Rev. 1.0

108 Instruction Set

Table 11-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

0123456789 ABCDEF

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Electrical Specifications 109 General Release Specification — MC68HC805K3 Section 12. Electrical Specifications

12.1 Contents

12.2 Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS ≤ (VIN or VOUT )≤ VDD . Connect unused inputs to the appropriate voltage level, either VSS or VDD NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to12.5 5.0 Volt DC Electrical Characteristics1 and12.6

3.0 Volt DC Electrical Characteristics1 for guaranteed operating

conditions. Rating Symbol Value Unit Supply Voltage V DD –0.3 to + 7.0 V Input Voltage V IN VSS –0.3 to VDD + –0.3 V Storage Temperature Range T STG –65 to + 150 °C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Operating Range MC68HC805K3 — Rev. 1.0

12.3 Operating Range

12.4 Thermal Characteristics

Characteristic Symbol Value Unit Operating Temperature Range MC68HC805K3 (Standard) MC68HC805K3 (Extended) TA TL to TH 0 to +70 –40 to +85 Supply Voltage Range for Internal Charge Pump Operation VDDCP 3.0 to 5.5 V Characteristic Symbol Value Unit Thermal Resistance PDIP SOIC θJA 100 140 °C/W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification

5.0 Volt DC Electrical Characteristics1

MC68HC805K3 — Rev. 1.0 Electrical Specifications 111 12.5 5.0 Volt DC Electrical Characteristics1 Characteristic Symbol Min Typ Max Unit Output High Voltage (ILOAD = –0.8 mA) PA7–PA0, PB1/OSC3, PB0 VOH VDD –0.8 — — V Output Low Voltage PA3–PA0, PB1/OSC3, PB0 (ILOAD = 1.6 mA) PA7–PA4 (ILOAD = 8.0 mA) VOL — 0.4 0.4 V Input High Voltage PA0–PA7, PB0, PB1/OSC3,IRQ,RESET, OSC1 VIH 0.7 x VDD —V DD V Input Low Voltage PA0–PA7, PB0, PB1/OSC3,IRQ,RESET, OSC1 VIL VSS — 0.2 x V DD V Supply Current (fOP = 2 MHz, see Notes 4–8) Run Wait Stop 25 °C 0 °C to +70°C (Standard) –40 °C to +85°C (Extended) IDD 100 5.0 3.0 300 500 600 mA mA nA nA nA I/O Ports Hi-Z Leakage Current PA0–PA7, PB0–PB1 (Without Pulldowns Activated) IIL —— 1 µA Input Pulldown Current PA0–PA7, PB0–PB1 IIL 50 100 200 µA Input Current IRQ, OSC1 RESET (V IN = VIH) RESET (V IN = VIL) IIN µA RESET, Internal Pulldown Device I IN 1.0 4.0 8.0 mA Capacitance Ports (As Input or Output) RESET, IRQ, OSC1, OSC2 C OUT C IN pF Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 R OSC 1.0 2.0 3.0 M Ω NOTES: 1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25°C only. 4. Wait IDD : Only timer system active 5. Run (Operating) IDD , Wait IDD : Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 6. Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 7. Stop IDD measured with OSC1 = VDD ,RESET open 8. Wait IDD is affected linearly by the OSC2 capacitance. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification 3.0 Volt DC Electrical Characteristics1 MC68HC805K3 — Rev. 1.0 12.6 3.0 Volt DC Electrical Characteristics1 Characteristic Symbol Min Typ Max Unit Output High Voltage (ILOAD = –0.4 mA) PA7–PA0, PB1/OSC3, PB0 VOH VDD –0.3 — — V Output Low Voltage PA3–PA0, PB1/OSC3, PB0 (ILOAD = 0.4 mA) PA7–PA4 (ILOAD = 3.0 mA) VOL — 0.3 0.3 V Input High Voltage PA0–PA7, PB0, PB1/OSC3,IRQ,RESET, OSC1 VIH 0.7 x VDD —V DD V Input Low Voltage PA0–PA7, PB0, PB1/OSC3,IRQ,RESET, OSC1 VIL VSS — 0.2 x V DD V Supply Current (fOP = 1 MHz, see Notes 4–8) Run Wait Stop 25 °C 0 °C to +70°C (Standard) –40 °C to +85 °C (Extended) IDD 2.0 0.75 200 275 300 mA mA nA nA nA I/O Ports Hi-Z Leakage Current PA0–PA7, PB0–PB1 (Without Individual Pulldown Activated) IIL —— 1 µA Input Pulldown Current PA0–PA7, PB0–PB1 IIL 25 50 100 µA Input Current IRQ, OSC1 RESET (V IN = VIH) RESET (V IN = VIL) IIN µA RESET, Internal Pulldown Device I IN 0.2 2.0 4.0 mA Capacitance Ports (As Input or Output) RESET, IRQ, OSC1, OSC2 C OUT C IN pF Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 R OSC 1.0 2.0 3.0 M Ω NOTES: 1. VDD = 3.0 Vdc ± 0.5 Vdc, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise note 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25°C only. 4. Wait IDD : Only timer system active 5. Run (Operating) IDD , Wait IDD : Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 6. Wait, Stop IDD : All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 7. Stop IDD measured with OSC1 = VDD ,RESET open 8. Wait IDD is affected linearly by the OSC2 capacitance. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification

5.0 Volt Control Timing1

MC68HC805K3 — Rev. 1.0 Electrical Specifications 113 12.7 5.0 Volt Control Timing1 Characteristic Symbol Min Max Unit Frequency of Operation 3-Pin RC Oscillator Option 2-Pin RC Oscillator Option Crystal Oscillator Option External Clock Source fOSC 0.1 0.1 0.5 DC 1.25 2.7 4.0 4.0 MHz Internal Operating Frequency RC Oscillator (fOSC ÷ 2) Crystal Oscillator (fOSC ÷ 2) External Clock (fOSC ÷ 2) fOP 0.5 1.0 DC 1.0 2.0 2.0 MHz Cycle Time (1÷ fOP )t CYC 500 — ns RC Oscillator Stabilization Time t RCON —1 m s Crystal Oscillator Startup Time (Crystal Oscillator Option) tOXON — 100 ms Stop Recovery Startup Time (Crystal Oscillator Option) t ILCH — 100 ms RESET Pulse Width Low t RL 1.5 — t CYC Timer Resolution (see Note 2) t RESL 4.0 — t CYC IRQ Interrupt Pulse Width Low (Edge-Triggered) t ILIH 125 — ns IRQ Interrupt Pulse Period t ILIL Note 3 — t CYC PA0 through PA3 Interrupt Pulse Width High (Edge-Triggered) tIHIL 125 — ns PA0 through PA3 Interrupt Pulse Period t IHIH Note 3 — t CYC OSC1 Pulse Width t 90 — ns 2-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz ΔfOSC — ±35 % 3-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz ΔfOSC — ±25 % PEEPROM Bit Programming Time t EPGM —1 0 m s PEEPROM Byte Erase Time t ERBT —1 0 m s PEEPROM Bulk Erase Time t ERBK —3 0 m s PEEPROM Charge Pump Startup Time t CP —1 m s NOTES: 1.VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise note 2.The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3.The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC . 4.Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification 3.0 Volt Control Timing1 MC68HC805K3 — Rev. 1.0 12.8 3.0 Volt Control Timing1 Characteristic Symbol Min Max Unit Frequency of Operation 3-Pin RC Oscillator Option 2-Pin RC Oscillator Option Crystal Oscillator Option External Clock Source fOSC 0.1 0.1 0.4 DC 0.6 0.7 1.0 1.0 MHz Internal Operating Frequency RC Oscillator (fOSC ÷ 2) Crystal Oscillator (fOSC ÷ 2) External Clock (fOSC ÷ 2) fOP DC 350 500 500 kHz Cycle Time (1÷ fOP )t CYC 2.0 — µs RC Oscillator Stabilization Time t RCON —1 m s Crystal Oscillator Startup Time (Crystal Oscillator Option) tOXON — 100 ms Stop Recovery Startup Time (Crystal Oscillator Option) t ILCH — 100 ms RESET Pulse Width Low t RL 1.5 — t CYC Timer Resolution (see Note 2) t RESL 4.0 — t CYC IRQ Interrupt Pulse Width Low (Edge-Triggered) t ILIH 125 — ns IRQ Interrupt Pulse Period t ILIL Note 3 — t CYC PA0 through PA3 Interrupt Pulse Width High (Edge-Triggered) tIHIL 125 — ns PA0 through PA3 Interrupt Pulse Period t IHIH Note 3 — t CYC OSC1 Pulse Width t 90 — ns 2-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz ΔfOSC — ±35 % 3-Pin RC Oscillator Frequency Combined Stability (see Note 4) fOSC = 500 kHz ΔfOSC — ±15 % NOTES: 1. VDD = 3.0 Vdc ± 0.5 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted 2. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC . 4. Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Mechnical Specifications 115 General Release Specification — MC68HC805K3 Section 13. Mechnical Specifications

13.1 Contents

13.2 Introduction

The MC68HC805K3 is available in the following packages:

• 648 — Plastic dual in-line package (PDIP)
• 751 — Small outline integrated circuit (SOIC) The following figures show the latest packages at the time of this publication. To make sure that you have the latest package specifications, contact one of the following:
• Local Motorola Sales Office
• Motorola Mfax – Phone 602-244-6609 – EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://design-net.com Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification Dual-In-Line Package (Case 648) MC68HC805K3 — Rev. 1.0

116 Mechnical Specifications

13.3 Dual-In-Line Package (Case 648)

13.4 Small Outline Integrated Circuit (Case 751)

-A- B F C S H G D 16 PL J L M SEATING PLANE 916 K -T- MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0° 10° 0° 10° S 0.020 0.040 0.51 1.01 F J DIM MIN MAX MIN MAX INCHESMILLIMETERS A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0° 7° 0° 7° P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MBM0.010 (0.25) -A- -B- P8X G 14X D 16X SEATING PLANE -T- SAM0.010 (0.25) B ST 16 9 R X 45 M C K Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC805K3 — Rev. 1.0 Ordering Information 117 General Release Specification — MC68HC805K3 Section 14. Ordering Information

14.1 Contents

14.2 Introduction

This section contains instructions for ordering custom-masked ROM MCUs.

14.3 MC Order Numbers

The following table shows the MC order numbers for the available package types. MC Order Number Operating Temperature Range MC68HC805K3P (Standard) –0 ° to 70°C MC68HC805K3CP (Extended) –40 ° to 85°C MC68HC805K3DW (Standard) –0 ° to 70 °C MC68HC805K3CDW (Extended) –40 ° to 85 °C NOTES: P = Plastic Dual In-Line Package DW = Small Outline Integrated Circuit (SOIC) Package Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

General Release Specification MC68HC805K3 — Rev. 1.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...