MC68HC811E2 FREESCALE | Alldatasheet
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ELECTRICAL CHARACTERISTICS
Table A-1. Maximum Ratings | Rating | Symbol | Value | unit [Supp Voage [Yoo | -03e+70| v__| f Input Vokage Vin | ~030+70 | OV | Operating Temperature Range Ts TL to Ty c MC68HC(7)1 TEx Oto+70 , MC68HC(7)11Exc — 40 to + 85 | MC8BHC(7)11Exv — 40 to + 105 | MC68HC(7)11ExM =40 10 + 125 | MO68HC811E2 Oto +70 MCO68HC811E2C —40 to + 85 | MCS8HC811E2V —40 to + 105 MC68HC811E2M —40 10 + 125 MCBBL11E9 —20to +70 Stooge Temporaure Range [te | Sermo | © | Excluding Vop. Vss. AVop. Vax. and Var *One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Extended operation at the maximum ratings can adversely affect device reliability. Tying unused inputs to an appropriate logic voltage level (either GND or Vpp) enhances reliability of operation. Table A-2. Thermal Characteristics [| Characteristic | Symbol [Value | Unit Average Junction Temperature Ty Ta+ (Pp x Qua) c Ambient Temperature Ta User-determined c Package Thermal Resistance (Junction-to-Ambient) “CME 48-Pin Plastic DIP (MC68HC811E2 only) 50 56-Pin Plastic SDIP 50 52-Pin Plastic Leaded Chip Carrier 50 52-Pin Plastic Thin Quad Flat Pack (TOFP) 85 64-Pin Quad Flat Pack 85 Total Power Dissipation (Note 1) Pint + Puo. Ki (Ty + 273°C) [Deve ntl PowerDasowion Pat | tooo |W ‘| [Worn PowerOiespaion = Nate2) | to |—Userdetomned |W A Constant (Note 3) K Pp x (Ta + 273°C) + wee yp x Po® = — A 1. This is an approximate value, neglecting Pyo. 2. Formost applications Py « Piyt and can be neglected. 3. Kis a constant pertaining to the device. Solve for K with a known T, and a measured Pp (at equilibrium), Use this value of K to solve for Pp and Ty iteratively for any value of Ta. M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-1
Table A-3. DC Electrical Characteristics Von = 5.0 Vde + 10%, Ves = 0 Vdc, Ta = Ti to TH, unless otherwise noted Characteristics Symbol Min’ | Max | Unit | ‘Output Voltage (Note 1) All Outputs except XTAL Vi = Vv All Outputs Except XTAL, RESET, and MODA Vou Yoo - 0.1 hroad = + 10.0 pA Output High Voltage (Note 1) All Oulputs Except XTAL, Vpo- 0.8 v RESET, and MODA lLoad = - 0.8 MA, Vpp = 4.5V — Output Low Voltage All Outputs Except XTAL Vou _- Vv lLoad = 1.6 mA = a Input High Voltage All Inputs Except RESET Vin 0.7*Vpo | Voo + 0.3 v RESET 0.8xVpp | Yoo + 9.3 inp ow Votge arouse | Ve __| Vss~09 | 02xvoo| ¥ _| UO Ports, Three-State Leakage PAT, PA3, +10 HA PC{7:0}, PD[5:0], AS/STRA, Vin = Vig Or Via MODAUR, RESET Input Leakage Current (Note 2) —_ ___ Vin= Vop 0 Vss PAf2:0], IRQ, XIRQ uA Vin = Vop oF Vs MODE stay HA RAM Standby Voltage Powerdown | Vea | 40 | Yoo | Vv | RAM Standby Current Powerdown | isa | — | 10 || A Input Capacitance —-PA(2:0), PE[7:0], 1A, XIRQ, EXTAL PA7, PAS, PC[7:0], PD{5:0}, . AS/STRA, MODA/LIR, RESET canoes Nowe ST Te | a PD[4:1 _ 100 p Maximum Total Supply Current (Note 3) RUN: 'bo Single-Chip Mode 2 MHz ‘ _ 15 m/ SMHz { _- 27 m Expanded Multiplexed Mode 2MHz | _ 27 mA 3MHz = 35 mm! WAIT: (All Peripheral Functions Shut Down) ' Wipe Single-Chip Mode 2MHz - 6 mA 3MHz | _ 16 mA Expanded Multiplexed Mode 2MHz _ 10 m 3MHz _ 20 mA STOP: Siop Single-Chip Mode, No Clocks = 40 to + 85 - 25 pA > +106 to + 125 od 100 Maximum Power Dissipation Po Single-Chip Mode 2MHz | 85 3MHz | 150 Expanded Multiplexed Mode 2MHz | 150 3MHz 195 NOTES: 1. Voy specification for RESET and MODA is not applicable because they are open-drain pins. Vow Specification not applicable to ports C and D jin wired-OR mode, 2. Refer to A/D specification for leakage current for port E. 3. EXTAL is driven with a square wave, and eye = 500 ne for 2 MHz rating: teye = 333 ns for 3 MHz rating; Va < 0.2 V; Vin 2 Vop - 0.2 V; No de loads. MOTOROLA APPENDIX A M68HC11 E SERIES A-2 ELECTRICAL CHARACTERISTICS TECHNICAL DATA
Table A-3a. DC Electrical Characteristics (MC68L11E9) . Voo = 3.0 Vde to 5.5 Vde, Vsg = 0 Vie, Ta = TL to TH, unless otherwise noted Characteristic Symbol | Min | Max | Unit | Output Voltage (Note 1) All Outputs except XTAL Vou vo All Outputs Except XTAL, RESET, and MODA VoH v | load = + 10.0 pA Output High Voltage (Note 1) All Outputs Except XTAL, Vou Vop ~ 0.8 Vv RESET, and MODA | \\Loag = - 0.5 MA, Vpp = 3.0 V | lLoag =~ 0.8 MA, Vop = 4.5 V Output Low Voltage All Outputs Except XTAL Vou v | hLoad * 1.6 MA, Vpp «5.0 V | __ oad = 1.0 MA, Vpp # 3.0V | Input High Voltage All Inputs Except RESET Vi 0.7xVpp | Vpp +03 vo} RESET 08x Vpp | Voo+0.3 Vv Input Low Voltag - Allinputs | Ve | Vss-03 | 02xVpp | __V VO Ports, Three-State Leakage PA7, PA3, +10 pA | PC[7:0), PD{S:0], AS/STRA. | Vin = Vin oF Vib ___MODA/LIR, RESET i input Leakage Current (Note 2) __ Vin = Voo of Vgs PA{2:0), IRQ, XIRQ wa Vin = Vo or Vs MODBVstey vA RAM Standby Voltage Power down Yop. | Vs RAM Standby Current Powerdown | _igp _| 10 BA Input Capacitance PA[2:0), PE[7:0], IRQ, XIRQ, EXTAL Cn pF | PA7, PAS, PC[7:0], PD[5:0), pF AS/STRA, MOOA/LIR, RESET | Output Load Capacitance All Outputs Except PD(4:1] 90 pe PD[4:1 100 pF | [Characteristic | Symbol | tmz | 2 MHz | unit | Maximurn Total Supply Current (Note 3) RUN: lop Single-Chip Mode Voo =5.5V 8 15 ma Voo =3.0V 4 8 m Expanded Multiplexed Mode Vpoo = 5.5V 14 27 m Vpo = 3.0V 7 14 mm WAIT: (All Peripheral Functions Shut Down) Wipp Single-Chip Mode Voo = 5.5V 3 6 m Vop =3.0V 15 3 mA Expanded Multiplexed Mode Vop = 5.5V 5 10 ma Voo =3.0V 25 5 mA STOP: Sipp Single-Chip Mode, No Clocks Voo = 5.5V 50 50 HA Vpoo = 3.0V 25 25 Maximum Power Dissipation Single-Chip Mode Vop =5.5V 44 85 Vpo = 3.0V 12 24 Expanded Multiplexed Mode Vop = 5.5V 7 160 Vpp =3.0V 21 42 NOTES: 1. Vo specification for RESET and MODA is not applicable because they are open-drain pins. Voy Specification not applicable to ports C and D in wired-OR mode. 2. Refer to A/D specification for leakage current for port E. 3. EXTALis crven with @ square wave, and = 1000 ns for 1 MHz rating; (= 500 ne tor 2 Miz rang Ve s02V; Vin 2 Vpp ~ 0.2 V; No de loads. M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-3
STROBES 0.4 Vos 4 Voks ~Vgg NOM. NOM. INPUTS yr otNoo = 20% of Voo NOMINAL TIMING — v0 j Vpp~ 08 Vols | ounrurs 04 Voks — vss DC TESTING | exocxs, ~¥oo 70% ot pp STROBES 2% ot 20% oF Vino -*5S sree SPEC qoTe a vrs {mame __} = 0.4 Vos SPEC TIMING / — v0 70% of Yop OUTPUTS 20% ol Vop — is AC TESTING | NOTES: 1. Full test loads are applied during all DC electrical tests and AC timing measurements. 2. Ouning AC timing maasurements, inputs are driven to 0.4 volts and Vp, — 0.8 volts while timing measurements are taken at the 20% and 70% Of Vpp points, ‘FEST EROS Figure A-1. Test Methods MOTOROLA APPENDIX A M68HC11 E SERIES A-4 ELECTRICAL CHARACTERISTICS TECHNICAL DATA
Table A-4. Control Timing Vp = 5.0 Vde + 10%, Veg = 0 Vie, Ta = TL 0TH Characteristic Symbol! 1.0 MHz | 2.0 MHz | 3.0 MHz Unit Frequency of Operation [to | ae | 1.0] ac | 20] ac | 3.0] Mite | Crystal Frequency | tra. | — | 40] — [80] — [120 Extemal Oscillator Frequency | 4to | ae | 40] oc | 80 | ac | 120 | Processor Control Setup Time tecsu 175 | tpogu = 1/4 ye + 50 ne | Reset input Pulse Width PWastL teye { To Guarantee External Reset Vector Minimum Input Time (Can Be Preempted by Internal Reset), { Mode Programming Hold Time | men | 10 | | = | rs | | Interrupt Pulse Width, IRQ Edge-Sensitive Mode « PWirna= +20ns [Wak Recovery Samp Ten wns [—Ta t= ya ee Timer Pulse Width input Capture Pulse Accumulator Input Prey 520 | PW = eye + 20108 NOTES: 1, ESET Is recognized during the first clock cycle it is held low. intemal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to SECTION 5 RESETS AND INTERRUPTS for further detail, 2. All timing is shown with respect to 20% Vpp and 70% Vop, unless otherwise noted. M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-5
Table A-4a. Control Timing (MC68L11E9) Vpp = 3.0 Vdc to 5.5 Ve, Veg = 0 Vde, Ta = T. to TH _ | Characteristic 1.0 MHz | 2.0 MHz | Unit | _ Max Frequency of Operation __ [| [1.0 | 2.0 | MHz | E-Clock Period teye — | 500| — | ns | Crystal Frequency AxTAL 40 | — | 8.0 | Mrz | External Oscillator Frequency Alo 4.0 dc | 8.0 MHz Processor Control Setup Time — | 200) — | ns teosu = 1/4 loyc + 75 ns Reset Input Pulse Width PWastL | To Guarantee External Reset Vector - 8 | — | tee Minimum Input Time (Can Be Preempted by internal Reset) -— {| 1 | = | tye Node Programing Setup Time | twes | 2 | = | o2 | = | tex | Mode Programming Hold Time | wen | 10 | — [| = | as | Interrupt Pulse Width, IRQ Edge-Sensitive Mode PWira | 1020] — PINRO = toye + 20.05 Timer Pulse Width, Input Capture Pulse Accumulator Input | PWrm | 10205 — ns | PWrim = teye +20 ns NOTES: 1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to SECTION 5 RESETS AND INTERRUPTS for further detail. 2. Alltiming is shown with respect to 20% Vpp and 70% Vpp, unless otherwise noted. Paso)’ Paso par’ Pir par NOTES: 1. Rising edge sensitive input 2. Falling edge sensitive input 3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2. Figure A-2. Timer Inputs MOTOROLA APPENDIX A Mé8HC11 E SERIES A-6 ELECTRICAL CHARACTERISTICS TECHNICAL DATA we 6367248 O127440 284 a
N | & N ||| 8 N cry i N 1 Neo N N27 au Vy
\\ a: N a0) N Ff Z N : N EE E N ome 3 N 2 E) 3 N : : N 5 N E F 3 2 = 2 J grad ta MOTOROLA APPENDIX A M68HC11 E SERIES A-6 ELECTRICAL CHARACTERISTICS TECHNICAL DATA WM 6367248 O1e7442 T5?
1S = 8 5 a Ss 2 a F -e -_l¥ 2 E $ € 3 2 e ig $ ® 3 @ c a\\|§8 = De < SE Bi Ear) < 7] es 2 3] 25 2 5 * g § FS ee H Ef “|g 2 5 le xie & gee 3 5 Bz a MesHC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS © A-9 MH 6367248 0127443 9953
=| [ss a © , oa Ja i a Da E) © i é a a (i) © : 7) & = : § (3) © g s [5] © “ U as BS ° PS BE _Iy |é ga g 0 ee “ig (ge g os 8 3s @ Rig & 8 ofl eee 2 5eai MOTOROLA APPENDIX A M68HC11 E SERIES A-10 ELECTRICAL CHARACTERISTICS TECHNICAL DATA ME 6367248 0127444 62T
Table A-5. Peripheral Port Timing Vpp = §.0 Vde # 10%, Veg = 0 Vdc, Ta = TL to TH Freqaeyt Operation EGeaxFreqwnay | te | ae | 10 | ae | 20) de | a0 | we Peripheral Data Setup Time tposu | i MCU Read of Ports A, C, D, and E 100 100 ns | | Peripheral Data Hold Time tpoH | MCU Read of Ports A, C, D, and E ns Delay Time, Peripheral Data Write | MCU Write to Port A 200 | — | 200, — | 200 MCU Writes to Ports 8, C, and D 350 | — | 225 | — | 183 tewo = 1/4 teye + 100 ns input Data Hod Tne (Pon) re ee Delay Time, E Fall to STRB 225 | — | 183 toep = 1/4 toyc + 100 ns | Delay Time, STRA Asserted to Port C Data tpop 1oo | — | 100 Output Valid | NOTES: 1. I this setup time is met, STRB acknowledges in the next cycle. If itis not met, the response may be delayed one more cycle. 2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively). 3. All timing is shown with respect to 20% Vp and 70% Vpp, unless otherwise noted. Mé8HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-11 MMH 6367248 0127445 7bb me
Table A-5a. Peripheral Port Timing (MC68L11E9) Vpp = 8.0 Ve to 5:5 Vdc, Veg = 0 Vide, Ta= Ti to TH Characteristic [ Symbot 1.0 MHz | 2.0 MHz | Frequency of Operation (E-Clock Frequency) fo | de | 10 | de | 20 | Peripheral Data Setup Time tposu MCU Read of Ports A, C, D, and E 100 Peripheral Data Hold Time MCU Read of Ports A, C, D, and Delay Time, Peripheral Data Write MCU Write to Port A — | 250 250 MCU Writes to Ports B, C, and D ae | 400 275 | tpwp = 1/4 tey + 150 ns. { j__tpwo= WA teye+ 190ns _ Input Data Setup Time (Port C) | ts | 60 | _ [60 | [Input Data Hold Time (Port C) ln | 100 | — | Delay Time, E Fall to STRB toes | — | 400 275 (DEB = 1/4 toye + 150 ns Setup Time, STRA Asserted to E Fall (Note 1) tes | 0 [0 | — | ns | Delay Time, STRA Asserted to Port C Data Output Valid 100 Hold Time, STRA Negated to Port C Data | | — | | — | NOTES: 1. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle. 2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively). 3. All timing is shown with respect to 20% Vpp and 70% Vpp, unless otherwise noted. —— MCU READ OF PORT id) E teosu tppx ~ PORTS: AceD tosu teon PORTE ‘* FOR NON-LATCHED OPERATION OF PORT C [ESPORT READ TW Figure A-7. Port Read Timing Diagram MOTOROLA APPENDIX A M68HC11 E SERIES A-12 ELECTRICAL CHARACTERISTICS TECHNICAL DATA MM 6367248 0127446 bTe
—— MCU WRITE To PORT > tewo >| | rors PREVIOUS PORT DATA X X X X x | NEW DATA VALID. 1 tow >} PORTA PREVIOUS PORT DATA XXXXK NEW DATA VALID vreau Figure A-8. Port Write Timing Diagram STRAIN) i tis. <-ls PORT (IN) sunugnevt one nw Figure A-9. Simple Input Strobe Timing Diagram ~<—— MCU WRITE TO PORT B> I | E tewo PORTB PREVIOUS POAT DATA NEW DATA VALID toes >| STRB (OUT) / saeceoue sos rm Figure A-10. Simple Output Strobe Timing Diagram M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-13 MB 6367248 012744? 535 me
<— READ PORTCL' > tacaoy: | tose >} toes STRB (OUT) N be bees > . STRA(IN) / tot het PORT C (IN) NOTES. 1. After reading PIOC with STAF set 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). sont enout csr Figure A-11. Port C Input Handshake Timing Diagram E tewo romain —mevearenronn XYREK [womans "|| toes sero |< toes ‘STRB (OUT) thes. STRA (IN) / NOTES: 1. After reading PIOC with STAF set 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). ear cose moter Figure A-12. Port C Output Handshake Timing Diagram MOTOROLA APPENDIX A M68HC11 E SERIES A-14 ELECTRICAL CHARACTERISTICS TECHNICAL DATA mm 6367248 O127448 47S
<— READ PORTCL! > E tow (oo= XXX | h<toes: *READY" toes: ‘STRB (OUT) thes: 'STRA (IN) | VVY rV\\ PORT C (OUT) { orvoara i (oon axvowra XXX vewowravaw fT) a) STRA ACTIVE BEFORE PORTCL WRITE toca STRA(N) { eco trou seg (rene FD (00R =0) NEW DATA VALID CS b) STRA ACTIVE AFTER PORTCL WRITE tee NOTES: 1. After reading PIOC with STAF set 2. Figure shows rising edge STRA (EGA = 1) and high true STAB (INVB = 1). Figure A-13. Three-State Variation of Output Handshake Timing Diagram (STRA Enables Output Buffer) Mé8HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-15 MB 6367248 0127449 301
Table A-6. Analog-To-Digital Converter Characteristics Vpp = 5.0 Vde + 10%, Veg = 0 Ve, Ta = Ty to Ty, 750 kHz < E < 3.0 MHz, unless otherwise noted Characteristic Parameter Absolute | 2.0 MHz|3.0 MHz] Unit Max | Max | [Resolution Number of Bits Resolved by A/D Converter|_ — | 8 — | —_ | Bits’ |Non-Linearity | Maximum Deviation from the Ideal A/D — | £12 +1 | LSB | Transfer Characteristics | Zero Error Difference Between the Output of an Ideal — | 212 +1 | UsB and an Actual for Zero Input Voltage | Full Scale Error _| Difference Between the Output of an Ideal #1 | SB | and an Actual A/D for Full-Scale Input | Voltage | Total Unadjusted | Maximum Sum of Non-Linearity, Zero Error, £112 | LSB Error and Full-Scale Error | Quantization —_| Uncertainty Because of Converter t12 | 212 | tsB Error Resolution Absolute Difference Between the Actual Input iH #2 | LSB ‘Accuracy Voltage and the Full-Scale Weighted Equivalent of the Binary Output Code, All | Error Sources Included Conversion | Analog Input Voltage Range Vat = Vay | Van | V |__ Range i Van Maximum Analog Reference Voltage Van | — | Vpo+0.1]Vpp+0.1] Vv (Note 2) : ___ _ Vat Minimum Analog Reference Voltage Ves-0.1] — Vay | Van | V (Note 2) { AVA | Minimum Difference between Vay anda, | 3 — lv Conversion Time | Total Time to Perform a Single Analog-to-Digital Conversion: Echo | |e f= | = The Monotonicity | Conversion Result Never Decreases with — Guaranteed) — = [= an Increase in Input Voltage and has no Missing Codes ft Zero Input Conversion Resuit when Vin = VAL o | = Tex Reading | Full Scale Conversion Result when Vin = VaH Hex Reading Sample Analog Input Acquisition Sampling Time: ; | Acquisition E Clock teye Time Internal RC Oscitator | — | — | 2 | 2 | us| ‘Sample/Hold —_| Input Capacitance During Sample PE{7:0] 20 (Typ) PF |_ Capacitance | Input Leakage | Input Leakage on A/D Pins Pei7-o}| — | — | 400 | 400 | nal NOTES: 1. Source impedances greater than 10 k®. affect accuracy adversely because of input leakage. 2. Performance verified down to 2.5 V AVp, but accuracy is tested and guaranteed at AVp = 5 V = 10%. MOTOROLA APPENDIX A Mé8HC11 E SERIES A-16 ELECTRICAL CHARACTERISTICS TECHNICAL DATA wm 6367248 0127450 023 =
Table A-6a. Analog-To-Digital Converter Characteristics (MC68L11E9) Vpp = 3.0 Vde to 5.5 Vac, Vgg = 0 Vde, T= Ty to Tr, 750 kHz < E < 2.0 MHz, unless otherwise noted Characteristic __Parameter | Min_| Absolute | Max | Unit] Resolution Number of Bits Resolved by AD Convener | — | 8 | — | Bits | Non-Linearity Maximum Deviation from the Ideal A/D Transfer | = +1 LsB | Characteristics | 200 rot eee | an Actual for Zero Input Voltage ' aan Actual A/D for Full-Scale Input Voltage |_Error Full-Scale Error Quantization Error | Uncertainty Because of Converter Resolution | — | — | +12 | LSB Difference Between the Actual Input Voltage _ | #2 sB and the Full-Scale Weighted Equivalent of the Binary Output Code, Alll Error Sources Included Conversion Range | Analog input Voltage Range Va | — | Van | V_ VrH Maximum Analog Reference Voltage Tova [| — | voor+ot] v | a [ava Miran Dfoeresbeween viwandva | 30 | | = |v Conversion Time | Total Time to Perform a Single 2 ‘Analog-to-Digital Conversion: Internal RC Oscillator | — | — | tye + 32 | us | Monotonicity Conversion Result Never Decreases with an Guaranteed = Increase in Input Voltage and has no Missing a [rues Resing [Conerson FesitvienVa=Viw =| | Sample Analog Input Acquisition Sampling Time: Sep Internal RC Oscillator | = — =| S| t2 | us | Sample/Hold Input Capacitance During Sample PE{7:0] 20 (Typ) pF [Sous |ree were rere || ee Input Leakage —_| Input Leakage on A/D Pins Peo) | — | — | 400 | ma | pee ere amv [== ep] NOTES: 1. Source impedances greater than 10 k2. affect accuracy adversely because of input leakage. M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-17 WB 6367248 0127451 ThT
Table A-7. Expansion Bus Timing Vpp = 5.0 Vie + 10%, Vgg = 0 Vde, Ta = TL to TH [Nem] Characteristic Symbol 1.0 MHz eee eee [___ [Frequency of Operation (E-Clock Frequency) |" fp [de | 4.0 | de | 20 [ de | 3.0 | wre| [i oyeetime te | T000[ — | 800 — [35 | — | os | Pulse Width, E Low PWe, | 477 l= [el =| ns PWeEL = 1/2 tye - 23 ns (Note 1) | Pulse Width, E High 472 ns | PWeH = 172 teye - 28 ns. (Note 1) { (8 | Ese am BHBnaE | 4> | EandAS Fall Time -— | 5 | | taH= 1/8 teye-29.5ns (Note 1, 2a) | 142 |Nonmuttiplexed Address Valid Time to E Rise | tay 54 | — | ns} tay = PWet - (tasp + 80 ns) (Note 1, 2a) i 18 [Read Data Hold Time (Max = tap) [ tona | 0 [145s o | 3 | o | 51 | ns | re Sere cd a a |_|. tpow= 18 teye + 65.5ns__ (Note 1, 2a) 121 [Write Data Hold Time tDHW 26 | — | ns | |_| tonw= 18 teye-29.5ns (Note 1, 2a) { | 22 |Mutipiexed Address Valid Time to E Rise tavm | 277.5 — | ns |__| tavm= PWex - (tasp + 90 ns) (Note 1, 2a) || 24 | Multiplexed Address Valid Time to AS Fall tas — | ns tast = PWasH -70ns (Note 1) [™ | Multiplexed Address Hold Time TAHL =| ns] tAHL = 1/8 teyo- 29.51ns__(Note 1, 2b) Delay Time, E to AS Rise tasp= 1/8 teye-9.5ns__(Note 1, 2a) 27 [Pulse Width, AS High 221 PWasH = 1/4 teye - 29 ns. (Note 1) Delay Time, AS to E Rise taSED 53 taseD = 1/8 toyc-9.5ns__ (Note 1, 2b) = here ae cer P| [Tell 1ACCA = teyc — (PWeL- tava) ~ tosA—tt } a i Oe tacce = PWeH - tos. Pe we LT | (Previous Cycle MPU Read) tap =taso+30ns (Note 1, 2a) NOTES: 1. Formula only for de to 2 MHz. 2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 teyc in the above formulas, where applicable: (a) (1-DC) x 14 teye (b) DCx 14 tye Where: DC is the decimal value of duty cycle percentage (high time). 3. Allltiming is shown with respect to 20% Vpp and 70% Vpp, unless otherwise noted. MOTOROLA APPENDIX A M68HC11 E SERIES A-18 ELECTRICAL CHARACTERISTICS TECHNICAL DATA M™ 6367248 O1e7452 ITb
Table A-7a. Expansion Bus Timing (MC68L11E9) Vp = 3.0 Ve to 5.5 Ve, Vgg = 0 Vde, Ta = TL toTH Num Characteristic aed [win | Max_| [Frequency of Operation (-Cinck Frequeney) | fe | de | 40 | de | 20 | Wie] T]oeting ee] 000 f= 800 — |e | 2 | Pulse Width, E Low PWe | 475 | 3 | Pulse Width, E High [Pres |] | = | PWeH = 1/2 toyo - 30 ns 48 | Eand AS Fall Time 25 [9 [Address Hold Time a = 12. |Nonmultiplexed Address Valid Time to E Rise tav 275 88 7 [Read Daia Scipio | top| | | oe | 1B [Read Data Hold Time i= a) es
79 Write Data Delay Time [ew | | | — | 133
tpow = 1/8 toye + 70 ns (Note 1a) \\21 | Write Data Hold Time ~ pow] =| 33 = re | toHW = 1/8 toye - 30 ns (Note 1a) 22 | Multiplexed Address Valid Time to E Rise ae ae ee ee tav = PWeL ~ (tas + 90 ns) (Note 1a) | 24 [Multiplexed Address Valid Time to AS Fall TASL | tas. = PWasH ~70ns an ee ee ee 25 | Multiplexed Address Hold Time a a 3 f — tAHL = 1/8 toye - 30. ns. (Note 1b) { 26 | Delay Time, E to AS Rise 7 58 _ 27 | Pulse Width, AS High - | Pras = se | — | PWaSH = 1/4 toys - 30 ns | oasis te em | || taSED = 1/8 teyo - 5 ns (Note 1b) | 29 |MPU Address Access Time (Note 1a) [woo | 788 | | 298 | taCcA = teye — (PWet- tava) ~tose—tt _ 35. | MPU Access Time ao | — tacce = PWeH ~tosR i 36 | Multiplexed Address Delay ~ = 88 1” | (Previous Cycle MPU Read) tan = tasp + 30 ns (Note ta) NOTES: 1. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place of 1/8 teye in the above formulas, where applicable: (a) (1-00) x 1/4 teye (b) DCX 1/4 toe Where: DC is the decimal value of duty cycle percentage (high time). 2. _Alltiming is shown with respect to 20% Vpp and 70% Vpp, unless otherwise noted. M68HC11 E SERIES. APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-19 MB 6367248 O127453 632
~ 4 i * @) | ——® ito RAW, ADDRESS VYVYVV SV wowwn | XXX TY) hey 8 or | re a a 6&8 ADDRESS/DATA P (MULTIPLEXED) x) ay VVVVY VV iY VV | we TXXXXN —wooness KX wre XY) as NOTE: Measurement points shown are 20% and 70% of Vop. onan Figure A-14. Multiplexed Expansion Bus Timing Diagram MOTOROLA APPENDIX A M68HC11 E SERIES A-20 ELECTRICAL CHARACTERISTICS TECHNICAL DATA W™ 6367248 0227454 779
Table A-8. Serial Peripheral Interface Timing Vpp = 5.0 Ve + 10%, Vgg = 0 Vio, Ta = TL to TH Num Characteristic Symbol | 2.0 MHz | 3.0 MHz | Unit Operating Frequency | Master fopim) de | 05 | de fop | Slave fopis) | de | 2.0 | do MHz | 1 | Cycle Time Master teycim) | 2.0 | — | 20 eye Slave | teyets) | 500 | — | 333 ns 2 | Enable Lead Time Slave tiead(s) — | 240) — ns | 3 | Enable Lag Time i Master (Note 2) | Magi) -—|-|— ns | Slave tags) | 250 | — | 240 ns | Clock (SCK) High Time | | Master twisckHjm| 340 | — | 227 ns | Slave twSckH)s | 190 | — | 127 ns Clock (SCK) Low Time | Master twsckijm | 340 | — | 227 ns | Slave twscktjs | 190 | — | 127 ns Data Setup Time (Inputs) Master teu(m) 100 | — | 100 ns | Slave teyis)_ | 100} — | 100 ns | 7 | Data Hold Time (Inputs) Master | tum | 190) — | 100 ns | Slave this) 100 | — | 100 ns | ‘Access Time (Time to Data Active from | High-Impedance State) | Slave ta 120 | 0 ns Disable Time (Hold Time to High-Impedance State) Slave tis 240 — | 167 ns | 10 _| Data Valid (After Enable Edge) (Note 3) [wey | — | 20] — | 167 | ns | 11 | Data Hold Time (Outputs) (After Enable Edge) | tio ~—| 0 | — | 0 | — | ns 12 _| Rise Time (20% Vpp to 70% Vpp, CL = 200 pF) SPI Outputs (SCK, MOSI, and MISO) _ tem 100 | — | 100} ns SPI Inputs (SCK, MOSI, MISO, and SS) | ts 20 | — | 20) us | 13 | Fall Time (70% Vpp to 20% Vpp, C= 200 pF) | SPI Outputs (SCK, MOSI, and MISO) ttm too | — | 100 | ns | | SPI Inputs (SCK, MOSI, MISO, and SS) Ys 20 | — | 20] us NOTES 1. Alltiming is shown with respect to 20% Vpp and 70% Vpp, unless otherwise noted. 2. Signal production depends on software. 3. Assumes 200 pF load on SCK, MOSI, and MISO pins. M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-21 M@ 6367248 0127455 bOS me
Table A-8a. Serial Peripheral Interface Timing (MC68L11E9) Vpp = 3.0 Vde to 5.5 Vde, Vsg = 0 Vac, Ta = TL to TH Characteristic Symbol | 1.0 MHz | 2.0 MHz | Unit Operating Frequency | Master fop(m) de | 05 | do | 05 fop Slave fois) | oe | 1.0 | do | 20 | MHz | Cycle Time | | Master teyc(m) | 2.0 - =- teye | Slave leyois)_| 1000 | — = ns Enable Lead Time | | Master (Note 2) teagim) | — — | ns Slave tieadis) | 500 — | os 3 | Enable Lag Time —_ ] | Master (Note 2) tlaggm | — = ns Slave lagis) | 500 - ns Clock (SCK) High Time | Master twisckHjm| 680 | — | 340 Slave twisckH)s | 380 | — | 190 Clock (SCK) Low Time | | Master tw(sckLjm | 680 | — | 340 ns Slave twiSCkL)s | 980 _ 190 ns Data Setup Time (Inputs) | Master tsu(m) | 100 — | 100 - ns Slave teuis) | 100 | — | 100 | — | ns 7 _ | Data Hold Time (Inputs) | Master tym | too | — | 100 | — ns Slave tis) | 100 | — | 100 | — ns ‘Access Time i | (Time to Data Active from High-Imp. State) | Slave ta o | 120 | 0 | 1200) ns Disable Time (Hold Time to High-Impedance State) Slave Data Valid (After Enable Edge) (Note 3) ys) 240 | — | 240 | ns | 11 | Data Hold Time (Outputs) (After Enable Edge) tho — |e — ns 12. | Rise Time (20% Vp to 70% Vp, Cy = 200 pF) | i | SPI Outputs (SCK, MOSI, and MISO) _ 1o0 | — | 100 ns SPI Inputs (SCK, MOS!, MISO, and SS) 20 | — | 20 hs 13 | Fall Time (70% Vpp to 20% Vpp, C = 200 pF) | | ‘SPI Outputs (SCK, MOSI, and MISO)_ 100 | — | 100 | ns |__| _ SPI inputs (SCK, MOSI, MISO, and SS) 2.0 = 20, us | NOTES: 1, Alltiming is shown with respect to 20% Vpp and 70% Vpp, unless otherwise noted. 2. Signal production depends on software. 3. Assumes 100 pF load on all SPI pins. MOTOROLA APPENDIX A Me8HC11 E SERIES A-22 ELECTRICAL CHARACTERISTICS TECHNICAL DATA W™ 6367248 0127456 S41 a
<< oF wen _ 5S is held high on master. _ @ ©) @ wun OE oe Kx xO © Nos! | <@ ® NOTE: This first clock edge Is generated internally but is not seen at the SCK pin. cmunsrencons rs a) SPI Master Timing (CPHA = 0) s ——oSOOOOOO OO OOO (weun 5S is held high on master. _ ne en scx cate Los j se <e | ® © @ Miso wun TD oe Ne es OL oie) <@ o omen [waster use out (ares) MASTER LSB OUT ©) «& NOTE: This last clock edge is generated internally but is not seen at the SCK pin. spinster cena Tae b) SPI Master Timing (CPHA = 1) Figure A-15. SPI Timing Diagram (1 of 2) M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-23 M™@ 6367248 0127457? 488 mm
(INPUT) ‘SCK (CPOL = 0) \\ (INPUT) ® ©) @ ® ‘MOSI wen Oo LD oO, NOTE: Not defined but normally MSB of character just received. “SPLSLAVE CPHAD TIN a) SPI Slave Timing (CPHA = 0) (INPUT) D6 >AK® >HKO ‘SCK (CPOL = 0) } | ‘ neu) ma f i) 1 el © | o> ‘SCK (CPOL = 1 G 0 0) o> MOS! noun {son ae) NOTE: Not defined but normally LSB of character previously transmitted. ‘SLANE Chm) Te b) SPI Slave Timing (CPHA = 1) Figure A-15. SPI Timing Diagram (2 of 2) MOTOROLA APPENDIX A Mé68HC11 E SERIES A-24 ELECTRICAL CHARACTERISTICS TECHNICAL DATA ME 6367248 O127458 314 a
Table A-9. EEPROM Characteristics Vp = 5.0 Ve +: 10%, Vgg = 0 Vdc, Ta = TL to TH | Characteristic Temperature Range | unit [= 40 to 88° | - 40 to 108° Cc] - 40 to 125°C Programming Time __<1.0 MHz, RCO Enabled 15 20 | ms (Note 1) 1.0 to 2.0 MHz, RCO Enabled Must use RCO | Must use RCO 2 2,0 MHz (or Anytime RCO Enabled) 15 20 | Erase Time (Note 1) Byte,RowandBuk | 10 10 ms [wren nance We) NOTES: 1. The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM programming and erasure when the E-clock frequency is below 1.0 MHz. 2. Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information. Table A-9a. EEPROM Characteristics (MC68L11E9) _ Vpp = 3.0 Vde to 5.5 Vde, Vgs = 0 Vde, Ta =T_ to TH Characteristic Temperature Range | Unit = 20 to 70°C Programming Time 3V, E <2,0 MHz, RCO Enabled 25 ms | (Note 1) 5V, E<2.0 MHz, RCO Enabled 10 | ms | Erase Time (Byte, Row and Bulk) 3V, E $2.0 MHz, RCO Enabled 25 | oms | (Note 1) 5V, E<2.0 MHz, RCO Enabled 10 ms Write/Erase Endurance 10,000 | Cycles | (Note 2) _ - | Data Retention Years | | (Note 2) NOTES: 1. The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM programming and erasure. 2. Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information M68HC11 E SERIES APPENDIX A MOTOROLA TECHNICAL DATA ELECTRICAL CHARACTERISTICS A-25 mm 6367248 0127459 250