68HC705PL4

68HC05PL4 FREESCALE | Alldatasheet

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REV 2.0 68HC05PL4 68HC05PL4B 68HC705PL4 68HC705PL4B SPECIFICATION (General Release) April 30, 1998 Consumer Systems Group Semiconductor Products Sector Freescale Sem iconductor, I For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 i TABLE OF CONTENTS Section Page SECTION 1 GENERAL DESCRIPTION SECTION 2 MEMORY SECTION 3 CENTRAL PROCESSING UNIT SECTION 4 INTERRUPTS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 ii REV 2.0 TABLE OF CONTENTS Section Page SECTION 5 RESETS SECTION 6 OPERATING MODES SECTION 7 INPUT/OUTPUT PORTS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 iii TABLE OF CONTENTS Section Page SECTION 8 SYSTEM CLOCKS SECTION 9 16-BIT PROGRAMMABLE TIMER SECTION 10 8-BIT TIMER SECTION 11 DIGITAL TO ANALOG CONVERTER SECTION 12 INSTRUCTION SET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 iv REV 2.0 TABLE OF CONTENTS Section Page SECTION 13 ELECTRICAL SPECIFICATIONS SECTION 14 MECHANICAL SPECIFICATIONS APPENDIX A MC68HC705PL4 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 v LIST OF FIGURES Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 vi REV 2.0 LIST OF FIGURES Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 vii LIST OF TABLES Table Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 viii REV 2.0 LIST OF TABLES Table Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 GENERAL DESCRIPTION REV 2.0 1-1 SECTION 1 GENERAL DESCRIPTION The MC68HC05PL4 HCMOS microcontroller is a member of the M68HC05 Fam- ily of low-cost single-chip microcontroller units (MCUs). This MCU is designed speci cally f or the handset and base set of cost-sensitive CT0/1 analog cordless phones. References to MC68HC05PL4 apply to both MC68HC05PL4 and MC68HC05PL4B, unless otherwise stated.

1.1 FEATURES

• Industry standard 8-bit M68HC05 CPU core
• Bus frequency: 2.56MHz @ 4V and 1MHz @ 2V
• Built-in low-frequency RC oscillator (500kHz and 20kHz)
• OSC input pin (OSC output pin on MC68HC05PL4B)
• 256 bytes of user RAM
• 4k-bytes of user ROM
• ROM security
• 23 (22 for MC68HC05PL4B) bidirectional I/O lines with: – 4 keyboard interrupts with pull-up resistor – 6 high current sink pins
• Open-drain output for LED drive
• Multiplexed DTMF output with built-in 6-bit D/A
• 16-bit programmable timer with input capture and output compare functions
• Reloadable 8-bit event timer
• COP watchdog reset
• Power saving STOP and WAIT modes
• Available in 28-pin PDIP , SOIC, and SSOP packages Table 1-1. MC68HC05PL4 and MC68HC05PL4B Differences Device Pin 27 MC68HC05PL4 PA0 MC68HC05PL4B OSC2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 GENERAL DESCRIPTION MC68HC05PL4 1-2 REV 2.0

1.2 MCU BLOCK DIAGRAM

Figure 1-1. MC68HC05PL4 Block Diagram NOTE A line over a signal name indicates an active low signal. Any reference to voltage, current, or frequency speci ed in the following sections will refer to the nominal values. The exact values and their tolerance or limits are speci ed in Electrical Speci cations section. USER ROM - 4k BYTES USER RAM - 256 BYTES ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER M68HC05 CPU RESET 1H I NZC OSC POWER OSC1 VDD VSS DDR B PORT B PB4- PB7 1 1 100000 0415 DDR A PORT A KEYBOARD INTERRUPT WATCHDOG SYSTEM PA6 PA5 PA4 PA3/TCMP PA2/TCAP PA1/DTMF PA0† 16-BIT PROGRAMMABLE TIMER VERY LOW FREQUENCY OSC (RC: 500kHz or 20kHz)(‚ N OPTIONAL) DTMF MODULE LED/IRQLED DRIVE DDR C PORT C PC0 - PC7 8-BIT RELOADABLE EVENT TIMER PB0/KBI0 PB1/KBI1 PB2/KBI2 PB3/KBI3 OSC2†† ††Available on MC68HC05PL4B only. †Available on MC68HC05PL4 only. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 GENERAL DESCRIPTION REV 2.0 1-3

1.3 PIN ASSIGNMENTS

Figure 1-2. MC68HC05PL4 Pin Assignment Figure 1-3. MC68HC05PL4B Pin Assignment VSS VDD PC7 PC6 RESET PB7 PB6 PB5 PB4 PB3/KBI3 PC5 PC4 PB2/KBI2 PB1/KBI1 OSC1 PA0 PC0 PC1 PA1/DTMF PA2/TCAP PA3/TCMP PA4 PA5 PA6 PC2 PC3 LED/IRQ PB0/KBI0 VSS VDD PC7 PC6 RESET PB7 PB6 PB5 PB4 PB3/KBI3 PC5 PC4 PB2/KBI2 PB1/KBI1 OSC1 OSC2 PC0 PC1 PA1/DTMF PA2/TCAP PA3/TCMP PA4 PA5 PA6 PC2 PC3 LED/IRQ PB0/KBI0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 GENERAL DESCRIPTION MC68HC05PL4 1-4 REV 2.0

1.4 PIN DESCRIPTIONS

The following paragraphs give a description of each functional pin.

1.4.1 VDD, VSS

Power is supplied to the MCU using these pins. VDD is the positive supply and VSS is the ground pin.

1.4.2 OSC1, OSC2

OSC2 is only available on MC68HC05PL4B. The OSC1 and OSC2 pins are the connections for the on-chip oscillator — the following con gur ations are available: 1. A crystal or ceramic resonator as shown in Figure 1-4(a). 2. An external clock signal as shown in Figure 1-4(b). The external oscillator clock frequency, f OSC , is divided by two to produce the internal operating frequency, f OP Figure 1-4. Oscillator Connections

1.4.3 RESET

This active low input-only pin is used to reset the MCU to a known start-up state. The RESET pin has an Schmitt trigger circuit as part of its input to improve noise immunity.

1.4.4 LED/IRQ

This pin has two functions, con gured b y the IRQEN bit in the Miscellaneous Con- trol and Status Register, at $1C (MISCR). When this pin is IRQ , it drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function uses the IRQS bit in the MISCR to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the MISCR bit is set to enable level-sensitive MCU (a) Crystal or Ceramic Resonator Connections OSC1 OSC2 2 MW UNCONNECTED EXTERNAL CLOCK (c) External Clock Source Connection OSC1 OSC2 MCU Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 GENERAL DESCRIPTION REV 2.0 1-5 triggering, the LED/IRQ pin requires an external resistor to VDD for “wired-OR” operation. If the LED/IRQ is not used, it must be tied to the VDD supply. The contains an internal Schmitt trigger as part of its input to improve noise immunity. When this pin is LED, the LED bit in the MISCR controls the on/off function of the connected LED. This LED pin sinks current via an internal pulldown resistor. IRQEN — External Interrupt Request Enable 0 = LED/IRQ pin con gured as LED dr ive pin. 1 = LED/IRQ pin con gured as IRQ input pin, for external interrupts. LED — LED Drive Output Control 1 = Enable internal pulldown resistor, pin is logic low. 0 = Disable internal pulldown resistor, pin is in high impedance state.

1.4.5 PA0, PA1/DTMF, PA2/TCAP, PA3/TCMP, PA4-PA6

These eight I/O lines comprise port A, a general purpose bidirectional I/O port. The state of any pin is software programmable and all port B lines are con gured as inputs during power-on or reset. PA0 is only available on MC68HC05PL4. PA1 is shared with DTMF output of the DAC subsystem. This pin is con gured as an output pin for DTMF . PA2 is shared with TCAP input of the 16-bit timer. This pin is con gured as an input pin for TCAP . PA3 is shared with TCMP output of the 16-bit timer. This pin is con gured as an output pin for TCMP . PA5 and PA6 have high current sinking capability; see Electrical Speci cations section for values.

1.4.6 PB0/KBI0-PB3/KBI3, PB4-PB7

These eight I/O lines comprise port B, a general purpose bidirectional I/O port. The state of any pin is software programmable and all port B lines are con gured as inputs during power-on or reset. All port B pins have internal pullups which can be individually enabled by software. PB0-PB3 also have keyboard interrupt capability, which can be individually enabled. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MICSR R IRQEN IRQS TCMPEN TCAPEN LED COPON POR$001C W RESET 00000000 Figure 1-5. Miscellaneous Control and Status Register (MICSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 GENERAL DESCRIPTION MC68HC05PL4 1-6 REV 2.0

1.4.7 PC0-PC7

These eight I/O lines comprise port C, a general purpose bidirectional I/O port. The state of any pin is software programmable and all port C lines are con gured as inputs during power-on or reset. PC4-PC7 have high current sinking capability; see Electrical Speci cations sec- tion for values. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 MEMORY REV 2.0 2-1 SECTION 2 MEMORY This section describes the organization of the memory on the MC68HC05PL4.

2.1 MEMORY MAP

The CPU can address 8k-bytes of memory space as shown in Figure 2-1 . The ROM portion of the memory holds the program instructions, xed data, user de ned v ectors, and interrupt service routines. The RAM portion of memory holds variable data. I/O registers are memory mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. Figure 2-1. MC68HC05PL4 Memory Map I/O REGISTERS

32 BYTES

256 BYTES

4096 BYTES

496 BYTES

$0000 $001F $0020 $011F $0120 $0DFF $0E00 $1DFF $1E00 $1FEF $1FFF $1FF0 $00C0 $00FF STACK

64 BYTES

16 BYTES

$1FF0-$1FF1 $1FF2-$1FF3 $1FF4-$1FF5 $1FF6-$1FF7 $1FF8-$1FF9 $1FFA-$1FFB $1FFC-$1FFD $1FFE-$1FFF Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MEMORY MC68HC05PL4 2-2 REV 2.0

2.2 I/O REGISTERS

The rst 32 addresses of the memor y space, $0000-$001F , are the I/O section. One I/O register is located outside the 32-byte I/O section, which is the Computer Operating Properly (COP) register mapped at $1FF0. The bit assignment of each I/O register is described in the respective sections and summarized in Figure 2-3 and Figure 2-4

2.3 RAM

The 256 addresses from $0020 to $01FF serve as both user RAM and the stack RAM. The CPU uses v e RAM bytes to save all CPU register contents before pro- cessing an interrupt. During a subroutine call, the CPU uses two bytes to store the return address. The stack pointer decrements during pushes and increments dur- ing pulls. NOTE Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.

2.4 ROM

The 4096 bytes of user ROM is located from address $0E00 to $1DFF . Addresses $1FF0 to $1FFF contain 16 bytes of ROM reserved for user vectors.

2.5 COP WATCHDOG REGISTER (COPR)

Writing “0” to the COPC bit in the COP watchdog register ($1FF0) resets the COP watchdog timer. This is a write only register; writing a “1” to COPC has no effect. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COPR R $1FF0 W COPC RESET UUUUUUUU Figure 2-2. COP Watchdog Register (COPR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 MEMORY REV 2.0 2-3 ADDR REGISTER ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0000 Port A Data R PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA W $0001 Port B Data R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB W $0002 Port C Data R PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTC W $0003 RESERVED R W $0004 RESERVED R W $0005 Port A Data Direction R DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRA W $0006 Port B Data Direction R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 DDRB W $0007 Port C Data Direction R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 DDRC W $0008 RESERVED R W $0009 RESERVED R W $000A Pull-up Enable R PUL7 PUL6 PUL5 PUL4 PUL3 PUL2 PUL1 PUL0 PUER W $000B Keyboard Int. Enable R KIE3 KIE2 KIE1 KIE0 KIER W $000C Keyboard Int. Flag R KIF3 KIF2 KIF1 KIF0 KIFR W $000D Timer 8 Ctrl/Status R T8IF 0 T8IE T8EN PS2 PS1 PS0 T8CSR W T8IFR $000E Timer 8 Counter R T8CNT7 T8CNT6 T8CNT5 T8CNT4 T8CNT3 T8CNT2 T8CNT1 T8CNT0 T8CNTR W $000F DAC Ctrl and Data R DACEN DA5 DA4 DA3 DA2 DA1 DA0 DACDR W Figure 2-3. I/O Registers $0000-$000F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MEMORY MC68HC05PL4 2-4 REV 2.0 ADDR REGISTER ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 $0010 RESERVED R W $0011 RESERVED R W $0012 Timer Control R ICIE OCIE TOIE IEDG OLVL TCR W $0013 Timer Status R ICF OCF TOF TSR W $0014 Input Capture High R ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0 ICRH W $0015 Input Capture Low R ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0 ICRL W $0016 Output Compare High R OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0 OCRH W $0017 Output Compare Low R OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0 OCRL W $0018 Timer Counter High R TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0 TMRH W $0019 Timer Counter Low R TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0 TMRL W $001A Alt. Counter High R ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0 ACRH W $001B Alt. Counter Low R ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0 ACRL W $001C Misc. Control/Status R IRQEN IRQS TCMPEN TCAPEN LED COPON POR MICSR W $001D System Clock Control R SYSDIV1 SYSDIV2 CKSEL1 CKSEL2 FMODE OSCF RCF CKOSCSYSCR W $001E RESERVED R W $001F RESERVED R W Figure 2-4. I/O Registers $0010-$001F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 CENTRAL PROCESSING UNIT REV 2.0 3-1 SECTION 3 CENTRAL PROCESSING UNIT The MC68HC05PL4 has an 8k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF . All other instructions and registers behave as described in this chapter.

3.1 REGISTERS

The MCU contains v e registers which are hard-wired within the CPU and are not part of the memory map. These ve registers are shown in Figure 3-1 and are described in the following paragraphs. Figure 3-1. MC68HC05 Programming Model CONDITION CODE REGISTER I ACCUMULATOR A INDEX REGISTER X 452 3 STACK POINTER SP 14 815 9 1213 10 11 PC CC111 1100000000 PROGRAM COUNTER H NZC HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 CENTRAL PROCESSING UNIT MC68HC05PL4 3-2 REV 2.0

3.2 ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device.

3.3 INDEX REGISTER (X)

The index register shown in Figure 3-1 is an 8-bit register that can perform two functions:

• Indexed addressing
• Temporary storage In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU nds the oper and address by adding the index register content to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU nds the operand address by adding the index register content to a 16-bit immediate value. The index register can also serve as an auxiliary accumulator for temporary storage. The index register is not affected by a reset of the device.

3.4 STACK POINTER (SP)

The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF . The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. When accessing memory, the ten most signi cant bits are permanently set to 0000000011. The six least signi cant register bits are appended to these ten x ed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses ve locations.

3.5 PROGRAM COUNTER (PC)

The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 CENTRAL PROCESSING UNIT REV 2.0 3-3 Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

3.6 CONDITION CODE REGISTER (CCR)

The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fth bit is the interrupt mask. These bits can be individually tested by a program, and speci c actions can be taken as a result of their states. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower v e bits of the condition code register.

3.6.1 Half Carry Bit (H-Bit)

When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.

3.6.2 Interrupt Mask (I-Bit)

When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions.

3.6.3 Negative Bit (N-Bit)

The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.) The negative bit can also be used to check an often tested ag b y assigning the ag to bit 7 of a register or memor y location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ag.

3.6.4 Zero Bit (Z-Bit)

The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 CENTRAL PROCESSING UNIT MC68HC05PL4 3-4 REV 2.0

3.6.5 Carry/Borrow Bit (C-Bit)

The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INTERRUPTS REV 2.0 4-1 SECTION 4 INTERRUPTS The CPU can be interrupted by ve different sources – one software and four hardware:

• Non-maskable Software Interrupt Instruction (SWI)
• External Asynchronous Interrupt (IRQ )
• 16-Bit Timer
• 8-Bit Timer
• Keyboard Interrupt

4.1 INTERRUPT VECTORS

Table 4-1 summarizes the reset and interrupt sources and vector assignments Table 4-1. Vector Address for Interrupts and Reset Function Source Local Mask Global Mask Priority (1=Highest) Vector Address Reset Power-On Logic None None 1 $1FFE-$1FFFRESET Pin None COP Watchdog COPON 1 SWI User Code None None Same Priority As Instruction $1FFC-$1FFD External IRQ IRQ Pin IRQEN I Bit 2 $1FFA-$1FFB 16-Bit Timer ICF Bit ICIE I Bit 3 $1FF8-$1FF9TCF Bit TCIE OCF Bit OCIE 8-Bit Timer T8IF Bit T8IE I Bit 4 $1FF6-$1FF7 Keyboard KIF3 Bit KIE3 I Bit 5 $1FF4-$1FF5KIF2 Bit KIE2 KIF1 Bit KIE1 KIF0 Bit KIE0 NOTES: 1. COPON enables/disables the COP watchdog timer. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INTERRUPTS MC68HC05PL4 4-2 REV 2.0 NOTE If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt rst. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit.

4.2 INTERRUPT PROCESSING

The CPU does the following actions to begin servicing an interrupt:

• Stores the CPU registers on the stack in the order shown in Figure 4-1
• Sets the I bit in the condition code register to prevent further interrupts
• Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1 The return from interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt is shown in the o w chart in Figure 4-2 $0020 (Bottom of RAM) $0021 $00BE $00BF $00C0 (Bottom of Stack) $00C1 $00C2 Unstacking Order ß n Condition Code Register 5 1 n+1 Accumulator 4 2 n+2 Index Register 3 3 n+3 Program Counter (High Byte) 2 4 n+4 Program Counter (Low Byte) 1 5 Ý Stacking $00FD Order $00FE $00FF Top of Stack (RAM) Figure 4-1. Interrupt Stacking Order Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INTERRUPTS REV 2.0 4-3 Figure 4-2. Interrupt Flowchart NO EXTERNAL INTERRUPT? I BIT SET? FROM RESET YES YES CLEAR IRQ LATCH. NO EXECUTE INSTRUCTION. UNSTACK CCR, A, X, PCH, PCL. FETCH NEXT INSTRUCTION. STACK PCL, PCH, X, A, CCR. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. 16-BIT TIMER INTERRUPT? YES NO 8-BIT TIMER INTERRUPT? YES NO KEYBOARD INTERRUPT? YES NO SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES NO Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INTERRUPTS MC68HC05PL4 4-4 REV 2.0

4.3 SOFTWARE INTERRUPT

The software interrupt (SWI) instruction causes a non-maskable interrupt.

4.4 EXTERNAL INTERRUPT

The LED/IRQ pin is the source that generates external interrupt. Setting the I bit in the condition code register or clearing the IRQEN bit in the miscellaneous control/ status register disables this external interrupt.

4.4.1 LED/IRQ Pin

This pin is an open drain pin and setting the IRQEN bit in Miscellaneous Control/ Status Register (MICSR) will set this pin for external interrupt input pin. An interrupt signal on the LED/IRQ pin latches an external interrupt request. To help clean up slow edges, the input from the LED/IRQ pin is processed by a Schmitt trigger gate. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQEN bit in the MICSR. If the I bit is clear and the IRQEN bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared dur- ing the return from interrupt, the CPU can recognize the new interrupt request. Figure 4-3 shows the logic for external interrupts. The LED/IRQ pin can be negative edge-triggered only or negative edge- and low- level-triggered. External interrupt sensitivity is programmed with the IRQS bit. With the edge- and level-sensitive trigger option, a falling edge or a low level on the LED/IRQ pin latches an external interrupt request. The edge- and level-sensi- tive trigger option allows connection to the LED/IRQ pin of multiple wired-OR interrupt sources. As long as any source is holding the LED/IRQ low, an external interrupt request is present, and the CPU continues to execute the interrupt ser- vice routine. With the edge-sensitive-only trigger option, a falling edge on the LED/IRQ pin latches an external interrupt request. A subsequent interrupt request can be latched only after the voltage level on the LED/IRQ pin returns to a logic one and then falls again to logic zero. NOTE To use the external interrupt function to exit from WAIT or STOP , it must be enabled prior entering either of the power saving modes. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INTERRUPTS REV 2.0 4-5 Figure 4-3. External Interrupt Logic

4.4.2 Miscellaneous Control and Status Register

IRQEN — External Interrupt Request Enable This read/write bit enables external interrupts. Reset clears the IRQEN bit. 0 = External interrupt processing disabled. LED/IRQ pin return to normal LED function 1 = External interrupt processing enabled. LED/IRQ pin set to IRQ function IRQS— External Interrupt Sensitivity This bit makes the external interrupt inputs level-triggered as well as edge-trig- gered. 0 = IRQ negative edge-triggered and low level-triggered. 1 = IRQ negative edge-triggered only. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MICSR R IRQEN IRQS TCMPEN TCAPEN LED COPON POR$001C W RESET 00000000 Figure 4-4. Miscellaneous Control and Status Register (MICSR) Edge and Level Sensitive IRQS VDD LED/IRQ Power On Reset PH2 BIH,BIL instruction External Reset External Interrupt Being Serviced (Read of Vectors) IRQENLED Q D R Q D INTERRUPT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INTERRUPTS MC68HC05PL4 4-6 REV 2.0 4.5 16-BIT TIMER INTERRUPTS The 16-bit programmable Timer can generate an interrupt whenever the following events occur:

• Input capture
• Output compare
• Timer counter over o w Setting the I bit in the condition code register disables Timer interrupts. The con- trols for these interrupts are in the Timer control register (TCR) located at $0012 and in the status bits are in the Timer status register (TSR) located at $0013. The 16-bit programmable Timer interrupts can wake up MCU from WAIT Mode.

4.5.1 Input Capture Interrupt

An input capture interrupt occurs if the input capture ag (ICF) becomes set while the input capture interrupt enable bit (ICIE) is also set. The ICF ag bit is in the TSR; and the ICIE enable bit is located in the MICSR. The ICF ag bit is cleared by a read of the TSR with the ICF ag bit is set; and then followed by a read of the LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaf- fected by reset.

4.5.2 Output Compare Interrupt

An output compare interrupt occurs if the output compare ag (OCF) becomes set while the output compare interrupt enable bit (OCIE) is also set. The OCF ag bit is in the TSR and the OCIE enable bit is in the MICSR. The OCF ag bit is cleared by a read of the TSR with the OCF ag bit set; and then followed by an access to the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is unaffected by reset.

4.5.3 Timer Overflow Interrupt

A Timer over ow interrupt occurs if the Timer over ow ag (TOF) becomes set while the Timer over o w interrupt enable bit (TOIE) is also set. The TOF ag bit is in the TSR and the TOIE enable bit is in the TCR. The TOF ag bit is cleared b y a read of the TSR with the TOF ag bit set; and then followed by an access to the LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected by reset. 4.6 8-BIT TIMER INTERRUPT The 8-bit Timer can generate an interrupt when the Timer8 Counter Register (T8CNTR) decrements from preset value to zero and the interrupt enable bit is set. Setting the I bit in the condition code register disables this Timer interrupts. The control bit for this interrupt and status bit are in the Timer 8 control register (T8CSR) located at $000D. The 8-Bit timer interrupt can wake up MCU from WAIT Mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INTERRUPTS REV 2.0 4-7

4.7 KEYBOARD INTERRUPT

Port B has internal pull-up resistors (typically 100KW ) and are enabled individually by setting the corresponding bit in the Pull-Up Enable Register (PUER). PB0 to PB3 have keyboard interrupt functions, with individual enable and ag bits in registers $000B and $000C. A falling edge on any one of the keyboard interrupt pins sets the corresponding KIF ag in the Keyboard Interrupt Flag Register (KIFR) located at $000C. If the associated KIE bit in the Keyboard Interrupt Enable Register (KIER) located at $000B is also set, a keyboard interrupt is generated to the processor. KIFx can be cleared by writing “1” to the bit. Resets clear both KIFR and KIER. Keyboard Interrupt can wake up the MCU from WAIT mode or STOP mode. NOTE Since the Keyboard Interrupt function is associated with PB0-PB3, any falling edge on these pins sets the corresponding KIF ag in the K eyboard Interrupt Flag Register. Therefore, PB0-PB3 should be connected to internal or external pull- ups, and KIFR cleared before these port pins switch from I/O to keyboard application. To use the keyboard interrupt function to exit from WAIT or STOP , it must be enabled prior entering either of the power saving modes. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PUER R PUL7 PUL6 PUL5 PUL4 PUL3 PUL2 PUL1 PUL0$000A W RESET 00000000 Figure 4-5. Pull-Up Enable Register (PUER) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 KIER R KIE3 KIE2 KIE1 KIE0$000B W RESET 00000000 Figure 4-6. Keyboard Interrupt Enable Register (KIER) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 KIFR R KIF3 KIF2 KIF1 KIF0$000C W RESET 00000000 Figure 4-7. Keyboard Interrupt Flag Register (KIFR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INTERRUPTS MC68HC05PL4 4-8 REV 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 RESETS REV 2.0 5-1 SECTION 5 RESETS This section describes the four reset sources and how they initialize the MCU. A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user de ned reset v ec- tor address. The following conditions produce a reset:

• Initial power-up of device (power-on reset)
• A logic zero applied to the RESET pin (external reset)
• Time-out of the COP watchdog (COP reset)
• Fetch of an opcode from an address not in the memory map (illegal address reset) Figure 5-1. Reset Sources

5.1 POWER-ON RESET

A positive transition on the V DD pin generates a power on reset. The power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. RESET RESET LATCH R COPON COP WATCHDOG POWER-ON RESET ILLEGAL ADDRESS RESET INTERNAL D INTERNAL CLOCK S RST TO CPU AND VDD 4-CYCLE COUNTER SUBSYSTEMS ADDRESS BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 RESETS MC68HC05PL4 5-2 REV 2.0 A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic zero at the end of the multiple tCYC time, the MCU remains in the reset condition until the signal on the RESET pin goes to a logic one. POR - Power on Reset Flag The POR bit is set each time the device is powered on. It allows the user to make a software distinction between a power-on and an external reset. POR can be cleared by software by writing a ‘0’ to the bit. It cannot be set by soft- ware.

5.2 EXTERNAL RESET

A logic zero applied to the RESET pin for 1.5t CYC generates an external reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the internal RST signal that resets the CPU and peripher- als. The RESET pin can also act as an open drain output. It will be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. This RESET pulldown device will only be asserted for 3-4 cycles of the internal clock, f OP, or as long as the internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will not be turned on. NOTE Do not connect the RESET pin directly to VDD, as this may overload some power supply designs when the internal pulldown on the RESET pin activates.

5.3 INTERNAL RESETS

The four internally generated resets are the initial power-on reset function, the COP Watchdog timer reset, the low voltage reset, and the illegal address detector. Only the COP Watchdog timer reset, low voltage reset and illegal address detec- tor will also assert the pulldown device on the RESET pin for the duration of the reset function or 3-4 internal clock cycles, whichever is longer. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MICSR R IRQEN IRQS TCMPEN TCAPEN LED COPON POR$001C W RESET 00000000 Figure 5-2. Miscellaneous Control and Status Register (MICSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 RESETS REV 2.0 5-3

5.3.1 Power-On Reset (POR)

The internal POR is generated on power-up to allow the clock oscillator to stabi- lize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 4096 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. V DD must drop below VPOR in order for the internal POR circuit to detect the next rise of VDD.

5.3.2 Computer Operating Properly (COP) Reset

The COP watchdog system consist of a divide by 8 counter with clock source from the 8-bit Timer (Timer8). Hence, a COP watchdog time-out occurs on the 8th Timer8 clock pulse. A COP watchdog time-out generates a COP reset to the CPU. Figure 5-3 shows a block diagram of the COP watchdog logic. Figure 5-3. COP Watchdog Block Diagram The COP watchdog is part of a software error detection system and must be cleared periodically to start a new time-out period. To clear the COP watchdog and prevent a COP reset, write a logic “1” to the COPC bit in the COP register at location $1FF0. The COP register, shown in Figure 5-4, is a write-only register that returns the content of a ROM location when read. COPC — COP Clear COPC is a write-only bit. Periodically writing a logic one to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = Reset COP watchdog timer. 0 = No effect on COP watchdog timer. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COPR R $1FF0 W COPC RESET UUUUUUUU Figure 5-4. COP Watchdog Register (COPR) S Latch R COPON From Timer8 Counter ‚ 8 Counter COP Reset To Reset Logic Write “1” to COPC R Logic From Reset Logic Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 RESETS MC68HC05PL4 5-4 REV 2.0 Use the following formula to calculate the COP time-out period: COP Time-out Period = (prescaler x 256 x 8) ‚ fBUS where prescaler is the Timer8 prescaler value The clock input to the watchdog system is derived from the output of the Timer8, therefore a reset or preset of Timer8 may affect the COP watchdog time-out period. The COP Watchdog reset will assert the pulldown device to pull the RESET pin low for 3-4 cycles of the internal bus clock. The COP reset can be enable or disable by the COPON bit in MISCR. The MISCR is in Figure 5-5. COPON — COP On Since the COP Watchdog system is derived from the 8-bit Timer system, the T8EN bit in the Timer8 Control and Status register (bit3 of $0D) must be set for COPON bit to have any affect. COPON can be set to enable the COP watchdog system. Once set, the watch- dog system cannot be disabled other than by a power-on reset or external reset. After a reset the COPON bit is cleared and the COP watchdog system is disabled. 1 = COP Watchdog enabled. 0 = COP Watchdog disabled. NOTE The COP Watchdog system is not designed to operate in STOP mode, therefore it should be disabled before entering STOP mode by clearing the COPON bit. Entering STOP mode with COP watchdog enabled will cause an internal reset of the MCU.

5.3.3 Illegal Address Reset

An opcode fetch from an address that is not in the ROM (locations $0E00–$1DFF and $1FF0-$1FFF) or the RAM (locations $0020–$011F) generates an illegal address reset. The illegal address reset will assert the pulldown device to pull the RESET pin low for 3-4 cycles of the internal bus clock. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MICSR R IRQEN IRQS TCMPEN TCAPEN LED COPON POR$001C W RESET 00000000 Figure 5-5. Miscellaneous Control and Status Register (MICSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 RESETS REV 2.0 5-5

5.4 RESET STATES OF SUBSYSTEM IN MCU

The following paragraphs describe how a reset initializes various sub-systems.

5.4.1 CPU

A reset has the following effects on the CPU:

• Loads the stack pointer with $FF .
• Sets the I bit in the condition code register, inhibiting interrupts.
• Loads the program counter with the user de ned reset vector from locations $1FFE and $1FFF .
• Clears the stop latch, enabling the CPU clock.
• Clears the wait latch, bringing the CPU out of the wait mode.

5.4.2 I/O Registers

A reset has the following effects on I/O registers:

• Clears bits in data direction registers con gur ing pins as inputs: – DDRA6–DDRA0 in DDRA for port A. – DDRB7–DDRB0 in DDRB for port B. – DDRC7–DDRC0 in DDRC for port C.
• Has no effect on port A, B, C data registers. 5.4.3 8-Bit Timer A reset has the following effects on the 8-Bit Timer:
• Timer 8 system disabled (T8EN bit cleared)
• Timer 8 interrupt request disabled
• Timer 8 Pre-scalar preset to divide the internal bus clock by ratio 16
• Timer 8 Counter register preset to $FF Therefore disables the timer 8 interrupt and preset the counter for POR cycle delay. 5.4.4 16-Bit Programmable Timer A reset has the following effects on the 16-bit programmable Timer:
• Initializes the timer counter registers (TMRH, TMRL) to a value of $FFFC.
• Initializes the alternate timer counter registers (ACRH, ACRL) to a value of $FFFC.
• Clears all the interrupt enables and the output level bit (OLVL) in the timer control register (TCR). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 RESETS MC68HC05PL4 5-6 REV 2.0

• Does not affect the input capture edge bit (IEDG) in the TCR.
• Does not affect the interrupt ags in the timer status register (TSR).
• Does not affect the input capture registers (ICRH, ICRL).
• Does not affect the output compare registers (OCRH, OCRL). Therefore con gure the por t A pins PA2,PA3 as general I/O function. However the timer is free running for interrupt process.

5.4.5 Keyboard Interrupt Interface

A reset has the following effects on the Keyboard Interrupt interface:

• Clears all bits in Keyboard interrupt enable register (KIER) and Keyboard interrupt disable
• Clears all bits in Keyboard interrupt ag register (KIFR)
• Clears all bits in Pull-Up enable register (PUER) Therefore disables the Keyboard interrupt and leaves the shared port B pins as general I/O. Any pending interrupt ag is cleared and the K eyboard interrupt is dis- abled. 5.4.6 6-bit DAC Subsystem A reset has the following effects on the DAC subsystem:
• Clears all bits in DAC control Register, hence DAC subsystem is disabled. Therefore con gure the por t A pin PA1 as general I/O function.

5.4.7 System Clock Option Subsystem

At reset has the following effects on OSC clock subsystem

• The internal RC is enabled and oscillating at around 500kHz
• Internal clock divider selected to divide by 2 for bus frequency

5.4.8 Miscellaneous Subsystem

A P reset has the following effects on IRQ subsystem

• IRQ is disabled and reset the IRQ selection as negative edge-triggered and low level-triggered, hence the LED/IRQ pin function as LED output pin Therefore also disable the LED driver output, hence the LED/IRQ pin is in high impedance state. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 RESETS REV 2.0 5-7

5.5 RESET CHARACTERISTICS

Table 5-1. Reset Characteristics Figure 5-6. Stop Recovery Timing Diagram Characteristic Symbol Min Typ Max Unit POR Recovery Voltage2 VPOR 0 — 100 mV POR VDD Slew Rate2 Rising2 Falling2 SVDDR SVDDF 0.1 0.05 V/ms V/ms RESET Pulse Width (when bus clock active) t RL 1.5 — — t CYC RESET Pulldown Pulse Width (from internal reset) t RPD 3—4 t CYC Note: 1. +2.0 £ VDD £ +4.0 V, VSS = 0 V, TL £ TA £ TH, unless otherwise noted 2. By design, not tested. PCH NEW 1FFE tRL OSC11 RESET Internal Clock3 Internal Address Bus3 4096 NOTES: 1. Represents the internal gating of the OSC1 pin 2. Normal delay of 4064 t CYC 3. Internal timing signal and data information not available externally. Internal Data Bus3 1FFF NEW PCH NEW PCL PCL NEW code O p Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 RESETS MC68HC05PL4 5-8 REV 2.0 Figure 5-7. Internal Reset Timing Diagram PCH NEW 1FFE tRPD RESET Internal Clock3 Internal Address Bus3 4096 NOTES: 1. Represents the internal reset from low voltage reset, illegal opcode fetch or COP Watchdog timeout. 2. Normal delay of 4064 t CYC 3. Internal timing signal and data information not available externally. Internal Data Bus3 1FFF NEW PCH NEW PCL PCL NEW Internal Reset1 Pin Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 OPERATING MODES REV 2.0 6-1 SECTION 6 OPERATING MODES This section describes the various operating modes of the MC68HC05PL4.

6.1 OPERATING MODES

The MC68HC05PL4 has two operating modes: Single-Chip (Normal) Mode and Self-Check Mode. At the rising edge of the RESET , the device latches the states of LED/IRQ and PB0/KBI0 pins and places itself in the speci ed mode . RESET must be held low for the prede ned po wer-on reset cycles of the internal PH2 clock after POR, or for a time tRL for any other reset. The conditions required to enter each mode are shown in Table 6-1. The mode of operation is determined by the voltages on the LED/IRQ and PB0/KBI0 pins on the rising edge of the external RESET pin.

6.1.1 Single-chip (Normal) Mode

The Single-Chip Mode is the normal operating mode, and it allows the device to function as a self-contained microcontroller, with maximum use of the pins for on- chip peripheral functions. In the Single-Chip Mode all address and data activity occurs within the MCU and is not available externally. Single-Chip Mode is entered if the LED/IRQ pin is within the normal operating voltage range when the rising edge of a RESET occurs. In Single-Chip Mode, all I/O port pins are available.

6.1.2 Self-check Mode

The self-check program is mask at location $1E00 to $1FEF , and is used for checking device functionality under minimum hardware support. Table 6-1. Operation Mode Condition After Reset RESET Pin LED/IRQ PB0/KBI0 MODE VSS to VDD VSS to VDD Single-Chip (Normal) VTST VDD Self-Check VTST = 2 x VDD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 OPERATING MODES MC68HC05PL4 6-2 REV 2.0

6.2 LOW POWER MODES

In each of its con gur ation modes the MC68HC05PL4 is capable of running in one of two low-power operating modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the oscillator. The o w of the STOP , and WAIT modes are shown in Figure 6-1.

6.2.1 STOP Mode

Execution of the STOP instruction places the MCU in its lowest power consumption mode. The MCU can exit from the STOP by an IRQ or Keyboard interrupt (KBIx), or an externally generated RESET. When exiting the STOP mode the internal oscillator will resume after 4064 internal processor clock cycles oscillator stabilization delay.

6.2.2 WAIT Mode

The WAIT instruction places the MCU in a low-power mode, which consumes more power than the STOP Mode. The WAIT mode may be exited by an external IRQ , a keyboard interrupt, 16-bit timer interrupt, 8-bit timer interrupt, or by an external RESET. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 OPERATING MODES REV 2.0 6-3 Figure 6-1. STOP/WAIT Flowchart 1. Fetch Reset Vector or 2. Service Interrupt a. Stack b. Set I-Bit c. Vector to Interrupt Routine WAIT External RESET? Y N IRQ External Interrupt? Y N Stop External Oscillator, Stop Internal Timer Clock, Reset Start-up Delay Restart External Oscillator, start Stabilization Delay Stop Internal Processor Clock, Clear I-Bit in CCR, and set IRQEN in MICSR End of Stabilization Delay? Y N IRQ External Interrupt? Y N External Oscillator Active and Internal Timer Clock Active Restart Internal Processor Clock 8-bit Timer Interrupt? Y N External RESET? Y N STOP Stop Internal Processor Clock, Clear I-Bit in CCR, and set IRQEN in MICSR 16-bit Timer Interrupt? Y N Keyboard Interrupt? Y N Keyboard Interrupt? Y N Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 OPERATING MODES MC68HC05PL4 6-4 REV 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INPUT/OUTPUT PORTS REV 2.0 7-1 SECTION 7 INPUT/OUTPUT PORTS This section describes the general purpose I/O ports on the MC68HC05PL4 and MC68HC05PL4B MCUs. In the MC68HC05PL4, 23 bidirectional I/O lines are available, arranged as one 7-bit I/O port (Port A), one 8-bit I/O port (Port B), and one 8-bit I/O port (Port C). In the MC68HC05PL4B, 22 bidirectional I/O lines are available, arranged as one 6-bit I/O port (Port A), one 8-bit I/O port (Port B), and one 8-bit I/O port (Port C). NOTE To avoid generating a glitch on an I/O port pin, data should be written to the I/O port data register before writing a “1” (for output) to the corresponding data direction register.

7.1 PARALLEL PORTS

Port A, B, and C are bidirectional ports. Each port pin is controlled by the corresponding bits in a data direction register and a data register as shown in Figure 7-1. The functions of the I/O pins are summarized in Table 7-1. Figure 7-1. Port Input/Output Circuitry I/O PINOUTPUT RESET (RST) Read Data Write Data Read/Write DDR Internal Data Bus Data Direction Register Bit Data Register Bit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INPUT/OUTPUT PORTS MC68HC05PL4 7-2 REV 2.0 Table 7-1. I/O Pin Functions

7.1.1 Port Data Registers

Each port I/O pin has a corresponding bit in the Port Data Register. When a port I/O pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. When a port pin is programmed as an input, any read of the Port Data Register will return the logic state of the corresponding I/O pin. The locations of the Data Registers for Port A, B, and C are at $0000, $0001 and $0002. The Port Data Registers are unaffected by reset.

7.1.2 Port Data Direction Registers

Each port I/O pin may be programmed as an input by clearing the corresponding bit in the DDR, or programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, and C are located at $0005, $0006 and $0007. The DDRs are cleared by reset. NOTE A “glitch” can be generated on an I/O pin when changing it from an input to an output unless the data register is rst preconditioned to the desired state before changing the corresponding DDR bit from a zero to a one.

7.2 PORT A

Port A is an 7-bit bidirectional port, with pins shared with other modules. The Port A Data Register is at address $0000 and the Data Direction Register is at address $0005. Port pins PA5 and PA6 are high current sink pins; see Electrical Speci cations section f or values. Pin PA0 is only available on MC68HC05PL4. OSC2 replaces PA0 on MC68HC05PL4B. Pin PA1 becomes the DTMF output from the DAC when the DACEN bit is set in the DAC Control and Data Register ($000F). Pins PA2 and PA3 become the 16-bit timer TCAP and TCMP respectively, when TCAPEN and TCMPEN are set in the Miscellaneous Control/Status Register ($001C). R/W DDR I/O Pin Functions 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is in an output mode. The output data latch is read. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INPUT/OUTPUT PORTS REV 2.0 7-3

7.3 PORT B

Port B is an 8-bit bidirectional port, with pins PB0-PB3 shared with keyboard inter- rupt functions. The Port B Data Register is at address $0001 and the Data Direc- tion Register is at address $0006. Pins PB0 to PB3 keyboard interrupt functions have individual enable and ag bits in registers $000B and $000C.

7.4 PORT C

Port C is an 8-bit bidirectional port. The Port C Data Register is at address $0002 and the Data Direction Register is at address $0007. Port pins PC0 to PC3 are high current sink pins; see Electrical Speci cations section f or values.

7.5 SUMMARY OF PORT A AND PORT B SHARED PINS

Table 7-2 below shows a summary of port pins shared with other on-chip mod- ules. Table 7-2. Port A and Port B Shared Pins Port Port Pin Control Pin Name Shared Functions Port A PA0 — PA0 or OSC2 PA0 on MC68HC05PL4 OSC2 on MC68HC05PL4B PA1 DACEN PA1/DTMF DAC DTMF Output PA2 TCAPEN PA2/TCAP 16-bit Timer Input Capture PA3 TCMPEN PA3/TCMP 16-bit Timer Output Compare Port B PB3-PB0 KBIE3-KBIE0 PUL3-PUL0 PB3/KBI3-PB0/KBI0 Keyboard Interrupt Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INPUT/OUTPUT PORTS MC68HC05PL4 7-4 REV 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 SYSTEM CLOCKS REV 2.0 8-1 SECTION 8 SYSTEM CLOCKS This section describes the system clock options for the MC68HC05PL4.

8.1 SYSTEM CLOCK SOURCE AND FREQUENCY OPTION

The operating bus frequency of the MCU is dependent on the clock source (OSC1 or internal RC) and the clock divider ratio. These are selected in the System Clock Control Register (SYSCR). SYSDIV1,SYSDIV2 — System Clock Divider Select The SYSDIV1 and SYSDIV2 bits select the divide ratio for the clock source. After power-on-reset, the default setting is divide by 2. Table 8-1 shows the divide ratios. CKSEL1,CKSEL2 — System Clock Source Select The CKSEL1 and CKSEL2 bits select the system clock source for the MCU. After power-on-reset, the default setting is internal RC. Table 8-2 shows the system clock source options. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SYSCR R SYSDIV1 SYSDIV2 CKSEL1 CKSEL2 FMODE OSCF RCF CKOSC$001D W P O R 00101010 Figure 8-1. System Clock Control Register (SYSCR) Table 8-1. System Clock Divider Select SYSDIV1 SYSDIV2 DIV 00 2 01 4 10 8 11 1 6 Table 8-2. System Clock Source Select CKSEL1 CKSEL2 Select Option 0 0 External from OSC1 0 1 External from OSC1 1 0 Internal RC 1 1 External from OSC1 (with RC enabled) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 SYSTEM CLOCKS MC68HC05PL4 8-2 REV 2.0 FMODE — Fast Mode RC select FMODE selects the oscillating frequency of the internal RC. After power-on- reset, the default setting is 500kHz. 1 = Internal RC oscillates at 500kHz 0 = Internal RC oscillates at 20kHz OSCF — OSC running Flag This bit is set when the external clock (External/crystal) from OSC1 is on. See also CKOSC bit below. RCF — RC Running Flag This bit is set when the internal RC clock is on. CKOSC — ChecK OSC The CKOSC bit enables the internal logic for external clock selection. The pro- cedure below should be followed when switching from RC to external clock. 1. Set the CKSEL1 and CKSEL2 bits for external clock source. 2. If crystal option is used — set the 8-bit timer for counting crystal stabilization delay (typically 4064 clock cycles). 3. Write a “1” to the CKOSC bit and check for OSCF bit set. 4. If the OSCF bit is not set, no external clock is available, the internal RC clock will be used as the system clock, irrespective of the setting for CKSEL1 and CKSEL2. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 16-BIT PROGRAMMABLE TIMER REV 2.0 9-1 SECTION 9 16-BIT PROGRAMMABLE TIMER The MC68HC05PL4 MCU contains a 16-bit programmable Timer with an Input Capture function and an Output Compare function as shown by the block diagram in Figure 9-1. Figure 9-1. Programmable Timer Block Diagram IEDG OLVL ICIE OCIE TOIE TMRH ($0018) TMRL ($0019) 16-BIT COUNTER ‚ 4 INTERNAL (XTAL ‚ 2) TIMER CONTROL REGISTER TIMER REQUEST OVERFLOW (TOF) RESET CLOCK INTERRUPT ACRH ($001A) ACRL ($001B) 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) PA2 TCAP EDGE SELECT & DETECT ICF OCF TOF TIMER STATUS REGISTER IEDG ICF OCF OLVL $0012 $0013 INTERNAL DATA BUS LOGIC ICRH ($0014) ICRL ($0015) D C Q PA3 TCMP Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 16-BIT PROGRAMMABLE TIMER MC68HC05PL4 9-2 REV 2.0 The basis of the capture/compare Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing ref- erence for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers. Each register pair contains the high and low byte of that function. Generally, accessing the low byte of a spe- ci c timer function allows full control of that function; however, an access of the high byte inhibits that speci c timer function until the lo w byte is also accessed. Because the counter is 16 bits long and preceded by a x ed divide-by-four pres- caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4 MHz crystal oscillator is 2 microsecond/count. The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012 and the status of the interrupt ags can be read from the timer status register (TSR) located at $0013.

9.1 TIMER REGISTERS (TMRH, TMRL)

The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in Figure 9-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter. Figure 9-2. Timer Counter and Register Block Diagram TOIE TMRH ($0018) TMR LSB 16-BIT COUNTER ‚ 4 INTERNAL (XTAL ‚2) TIMER CONTROL REG. TIMER REQUEST OVERFLOW (TOF) RESET CLOCK INTERRUPT TMRL ($0019) TOF TIMER STATUS REG. $0012 $0013 INTERNAL ($FFFC) DATA READ TMRH READ TMRL READ LATCH BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 16-BIT PROGRAMMABLE TIMER REV 2.0 9-3 The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. The TMRL latch is a transparent read of the LSB until the a read of the TMRH takes place. A read of the TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains x ed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when reading the MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a xed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer over o w ag bit (T OF) is set in the TSR. When the TOF is set, it can generate an interrupt if the timer over o w interrupt enable bit (TOIE) is also set in the TCR. The TOF ag bit can only be reset by reading the TMRL after reading the TSR. Other than clearing any possible TOF ags , reading the TMRH and TMRL in any order or any number of times does not have any effect on the 16-bit free-running counter. NOTE To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TMRH R TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0 $0018 W reset: 11111111 TMRL R TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0 $0019 W reset: 11111100 Figure 9-3. Programmable Timer Registers (TMRH, TMRL) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 16-BIT PROGRAMMABLE TIMER MC68HC05PL4 9-4 REV 2.0

9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL)

The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 9-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF ag bit and Timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter. Figure 9-4. Alternate Counter Block Diagram The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC. The ACRL latch is a transparent read of the LSB until the a read of the ACRH takes place. A read of the ACRH latches the LSB into the ACRL location until the ACRL is again read. The latched value remains x ed even if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a xed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF ag bit. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACRH R ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0 $001A W reset: 11111111 ACRL R ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0 $001B W reset: 11111100 Figure 9-5. Alternate Counter Registers (ACRH, ACRL) ACRH ($001A) TMR LSB 16-BIT COUNTER ‚ 4 INTERNAL (XTAL ‚ 2) RESET CLOCK ACRL ($001B) INTERNAL ($FFFC) DATA READ ACRH READ ACRL READ LATCH BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 16-BIT PROGRAMMABLE TIMER REV 2.0 9-5 NOTE To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL.

9.3 INPUT CAPTURE REGISTERS

The input capture function is a technique whereby an external signal (connected to PA2/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi- ble to relate the timing of an external signal to the internal counter value, and hence to elapsed time. When the input capture circuitry detects an active edge on the selected source, it latches the contents of the free-running timer counter registers into the input cap- ture registers as shown in Figure 9-6. Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter val- ues at successive edges of opposite polarity measures the pulse width of the sig- nal. Figure 9-6. Timer Input Capture Block Diagram The input capture registers are made up of two 8-bit read-only registers (ICRH, ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The edge that triggers the counter transfer is de ned by the input edge bit (IEDG) in the TCR. Reset does not affect the con- tents of the input capture registers. ICIE ICRH ($0014) 16-BIT COUNTER ‚ 4 INTERNAL (XTAL ‚ 2) TIMER CONTROL REG. TIMER REQUEST INPUT CAPTURE (ICF) RESET CLOCK INTERRUPT ICRL ($0015)ICF TIMER STATUS REG. $0012 $0013 INTERNAL ($FFFC) DATA READ ICRH READ ICRLLATCH BUS IEDG EDGE SELECT & DETECT LOGIC IEDG TCAP INTERNAL DATA BUS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 16-BIT PROGRAMMABLE TIMER MC68HC05PL4 9-6 REV 2.0 The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). Reading the ICRH inhibits further captures until the ICRL is also read. Reading the ICRL after reading the timer status register (TSR) clears the ICF ag bit. does not inhibit transfer of the free-running counter. There is no con ict betw een read- ing the ICRL and transfers from the free-running timer counters. The input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. NOTE To prevent interrupts from occurring between readings of the ICRH and ICRL, set the I bit in the condition code register (CCR) before reading ICRH and clear the I bit after reading ICRL.

9.4 OUTPUT COMPARE REGISTERS

The Output Compare function is a means of generating an output signal when the 16-bit timer counter reaches a selected value as shown in Figure 9-8. Software writes the selected value into the output compare registers. On every fourth inter- nal clock cycle (every eight oscillator clock cycle) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. When a match occurs, the timer transfers the output level (OLVL) from the timer control register (TCR) to the TCMP . Software can use the output compare register to measure time periods, to gener- ate timing delays, or to generate a pulse of speci c duration or a pulse train of speci c frequency and duty cycle on the TCMP . BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ICRH R ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0 $0014 W reset: UUUUUUUU ICRL R ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0 $0015 W reset: UUUUUUUU U = UNAFFECTED BY RESET Figure 9-7. Input Capture Registers (ICRH, ICRL) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 16-BIT PROGRAMMABLE TIMER MC68HC05PL4 9-8 REV 2.0 3. Read the TSR to arm the OCF for clearing. 4. Enable the output compare registers by writing to the OCRL. This also clears the OCF ag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register. A software example of this procedure is shown in Table 9-1.

9.5 TIMER CONTROL REGISTER (TCR)

The timer control register shown in Figure 9-10 performs the following functions:

• Enables input capture interrupts.
• Enables output compare interrupts.
• Enables timer over o w interrupts.
• Con gure the I/O P ort Pin PA2 as input pin for TCAP signal
• Con gure the I/O P ort Pin PA3 as output pin for TCMP signal
• Control the active edge polarity of the TCAP signal.
• Controls the active level of the TCMP output. Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected. ICIE - INPUT CAPTURE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the PB1/ TCAP pin or from CPF2 ag bit of the analog subsystem v oltage comparator 2. Reset clears the ICIE bit. 1 = Input capture interrupts enabled. 0 = Input capture interrupts disabled. Table 9-1. Output Compare Initialization Example ... ... BF ... ... SEI ... ... STA LDA STX ... ... CLI OCRH TSR OCRL DISABLE INTERRUPTS INHIBIT OUTPUT COMPARE ARM OCF FLAG FOR CLEARING READY FOR NEXT COMPARE, OCF CLEARED ENABLE INTERRUPTS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCR R ICIE OCIE TOIE 000 IEDG OLVL$0012 W reset: 000000U0 Figure 9-10. Timer Control Register (TCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 16-BIT PROGRAMMABLE TIMER REV 2.0 9-9 OCIE - OUTPUT COMPARE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the TCMP pin. Reset clears the OCIE bit. 1 = Output compare interrupts enabled. 0 = Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer over o w. Reset clears the TOIE bit. 1 = Timer over o w interrupts enabled. 0 = Timer over o w interrupts disabled. IEDG - INPUT CAPTURE EDGE SELECT The state of this read/write bit determines whether a positive or negative transi- tion on the TCAP pin triggers a transfer of the contents of the timer register to the input capture register. Resets have no effect on the IEDG bit. 1 = Positive edge (low to high transition) triggers input capture. 0 = Negative edge (high to low transition) triggers input capture. OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT The state of this read/write bit determines whether a logic one or a logic zero appears on the TCMP when a successful output compare occurs. Resets clear the OLVL bit. 1 = TCMP goes high on output compare. 0 = TCMP goes low on output compare.

9.5.1 Miscellaneous Control and Status Register for Timer16

The Miscellaneous Control and Status Register shown in Figure 9-11 performs the following functions:

• Con gure the I/O por t pin PA2 as input pin for TCAP signal
• Con gure the I/O por t pin PA3 as output pin for TCMP signal TCAPEN - TIMER INPUT CAPTURE ENABLE The bit con gures por t pin PA2 for Timer16 input capture function (TCAP). At power-on-reset, this bit is cleared, PA2 is a standard I/O port pin, TCAP to the Timer16 is pulled high. 1 = PA2 pin con gured as TCAP for timer input capture 0 = PA2 pin as standard I/O port pin BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MICSR R IRQEN IRQS TCMPEN TCAPEN 0 LED COPON POR$001C W reset: 00000001 Figure 9-11. Miscellaneous Control and Status Register (MISCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 16-BIT PROGRAMMABLE TIMER MC68HC05PL4 9-10 REV 2.0 TCMPEN - TIMER OUTPUT COMPARE ENABLE The bit con gures por t pin PA3 for Timer16 output compare function (TCMP). At power-on-reset, this bit is cleared, PA3 is a standard I/O port pin, TCMP sig- nal to PA3 is disabled from Timer16. 1 = PA3 pin con gured as TCMP for timer output compare 0 = PA3 pin as standard I/O port pin

9.6 TIMER STATUS REGISTER (TSR)

The timer status register (TSR) shown in Figure 9-12 contains ags f or the follow- ing events:

• An active signal on the PA2/TCAP pin transferring the contents of the timer registers to the input capture registers.
• A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the TCMP .
• An over o w of the timer registers from $FFFF to $0000. Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the ag bits in the TSR. ICF - INPUT CAPTURE FLAG The ICF bit is automatically set when an edge of the selected polarity occurs on the PA2/TCAP pin. Clear the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL, $0015) of the input capture registers. Resets have no effect on ICF . OCF - OUTPUT COMPARE FLAG The OCF bit is automatically set when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with the OCF set, and then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on OCF . TOF - TIMER OVERFLOW FLAG The TOF bit is automatically set when the 16-bit timer counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with the TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers. Resets have no effect on TOF . BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T S R R I C F O C F T O F 00000 $0013 W reset: U U U 00000 U = UNAFFECTED BY RESET Figure 9-12. Timer Status Registers (TSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 16-BIT PROGRAMMABLE TIMER REV 2.0 9-11 9.7 16-BIT TIMER OPERATION DURING WAIT MODE During WAIT mode the 16-bit timer continues to operate normally and may gener- ate an interrupt to trigger the MCU out of the WAIT mode. 9.8 16-BIT TIMER OPERATION DURING STOP MODE When the MCU enters the STOP mode the free-running counter stops counting (the internal processor clock is stopped). It remains at that particular count value until the STOP mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If STOP mode is exited via an external reset (logic low applied to the RESET pin) the counter is forced to timer interrupt vector. If a valid input capture edge occurs at the PA2/TCAP pin during the STOP mode the input capture detect circuitry will be armed. This action does not set any ags or “wake up” the MCU, but when the MCU does “wake up” there will be an active input capture ag (and data) from the rst v alid edge. If the STOP mode is exited by an external reset, no input capture ag or data will be present even if a valid input capture edge was detected during the STOP mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 16-BIT PROGRAMMABLE TIMER MC68HC05PL4 9-12 REV 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 8-BIT TIMER REV 2.0 10-1 SECTION 10 8-BIT TIMER This section describes the 8-bit count down timer module.

10.1 OVERVIEW

Figure 10-1. Timer8 Block Diagram As shown in Figure 10-1 this timer contains a single 8-bit software programmable countdown timer counter with a 3-bit software control prescaler. The counter’s value may be preset under software control and counts down to zero. When the counter decrements to zero, the timer8 interrupt request bit (T8IF in T8CR) is set. Then if the timer interrupt is enabled (T8IE in T8CR is set) and the I-bit of the con- dition code register are is cleared, the processor receives an interrupt. After com- pletion of the current instruction, the processor proceeds to store the appropriate registers on the stack and then fetches the timer8 interrupt vector in order to begin serving the interrupt. Interrupt Circuit Timer8 Counter Register ($0E) T8IF T8IFR T8IE T8EN PS2 PS1 PS0 Timer8 Control and Status Register ($0D) Overflow Detect Circuit 8-bit count-down timer counter 7-bit prescaler counter Prescaler Select Logic (8 to 1 MUX) Internal Bus Internal Bus Clock To COP Watchdog Circuit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 8-BIT TIMER MC68HC05PL4 10-2 REV 2.0 The counter continues to count after it reaches zero, allowing the software to determine the number of internal or external clocks since the timer interrupt request bit (T8IF) was set. The counter may be read at any time by the processor without disturbing the count. The contents of the counter become stable prior to the read portion of a cycle and do not change during the read. The timer interrupt request bit (T8IF) remains set until cleared by writing a “1” to the T8IFR bit in the T8CR. If writing to the timer 8 counter register (T8CNTR) occurs before the timer interrupt is served, the interrupt is lost. The T8IF bit may also be used as a scanned status bit in a non-interrupt mode of operation. The 3-bit control prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit 0, bit 1 and bit 2 (PS0, PS1 and PS2) of T8CR are pro- grammed to choose the appropriate prescaler output which is used as the counter input.

10.2 TIMER8 CONTROL AND STATUS REGISTER (T8CSR)

The T8CSR at address $000D enables the software to control the operation of the 8-bit timer. T8IF - Timer8 Interrupt Flag T8IF is set when Timer8 Counter Register counts down to zero. A CPU interrupt request will be generated if T8IE is set. Writing a "1" to the T8IFR bit clears the T8IF bit. Writing a "0" to this bit has no effect. Reset clears T8IF . 1 = Timer8 has count down to zero 0 = Timer8 has not count down to zero T8IFR - Timer8 Interrupt Flag Reset The T8IFR bit is a write-only bit, which clears the T8IF ag b y writing “1” to this bit when the T8IF bit is set. Writing a "0" has no effect. Reset does not affect this bit 1 = Clear T8IF ag bit 0 = No effect on T8IF ag bit T8IE - Interval Timer Interrupt Enable When this bit is set, a CPU interrupt request is generated when the T8IF bit is set. Reset clears this bit. 1 = 8-Bit Timer Interrupt enabled 0 = 8-Bit Timer Interrupt disabled BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T8CSR R T8IF 0 T8IE 0 T8EN PS2 PS1 PS0$000D W T8IFR reset: 00000100 Figure 10-2. Timer8 Control and Status Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 8-BIT TIMER REV 2.0 10-3 T8EN - Timer8 Enable This read/write bit enables the Timer8. Reset clears this bit. 1 = Timer8 enabled 0 = Timer8 disabled PS2-PS0 - Prescaler select These read/write bits is used to select the clock frequency to drive the 8-bit timer counter. The counter will be driven by a internal bus clock (E-clock) through this prescaler ratio. Upon reset and power on reset, the value of prescaler is set to a default value of divided by 16.

10.3 TIMER8 COUNTER REGISTER (T8CNTR)

The T8CNTR is a read/write register which contains the current value of the 8-bit timer counter. Reading this register enables the software to calculate the number of internal and external clocks since the timer interrupt request ag (T8IF) was set. Reading this address does not disturb the counter operation. NOTE This timer is used during the power-on sequence to time out the POR signal. The timer is con gured at po wer-on, with a prescaler division ratio of 16 and set to $FF in Timer counter register. Also the clock source for the COP watchdog system is derived from the output of this timer, hence a reset or preset of the prescaler and timer counter register may affect the frequency of the watchdog timeout.

10.4 COMPUTER OPERATING PROPERLY (COP) WATCHDOG

Please refer to section on RESETS for details. PS2 PS1 PS0 DIVIDE RATIO 000 1 001 2 010 4 011 8 1 0 0 16 (default after reset) 101 3 2 110 6 4 111 1 2 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T8CNTR R Timer 8 Counter Register$000E W reset: UUUUUUUU Figure 10-3. Timer8 Counter Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 8-BIT TIMER MC68HC05PL4 10-4 REV 2.0 10.5 8-BIT TIMER OPERATION DURING WAIT MODE The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. 10.6 8-BIT TIMER OPERATION DURING STOP MODE The timer ceases counting in STOP mode. When STOP is exited by an external interrupt or an external reset, the internal oscillator will resume its operation, fol- lowed by internal processor stabilization delay. The timer is then cleared to zero and resumes its operation. NOTE The T8IF bit in T8CSR will be set after MCU exit from STOP mode. To avoid generation of the timer 8 interrupt when exiting STOP mode, it is recommended to clear T8IE bit prior entering STOP mode. After exiting STOP mode T8IF bit must be cleared before setting T8IE bit. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 DIGITAL TO ANALOG CONVERTER REV 2.0 11-1 SECTION 11 DIGITAL TO ANALOG CONVERTER This section describes Digital-to-Analog module used for DTMF generation.

11.1 DAC CONTROL AND DATA REGISTER

DACEN - DAC Channel Enable Ths read/write bit enables/disables the DAC module for DTMF output. 1 = Enable DAC module and con gure PA1/DTMF as DTMF output pin. 0 = Disable DAC module and con gure PA1/DTMF as general purpose PA1 pin. DA5-DA0 These bits determine the output voltage of the DAC channel. The output volt- age value is determined by: VOUT = (VDD x DA[0:5]) x 26 There are 64 evenly spaced voltage levels available between VDD and VSS. The lowest voltage is VSS and the highest voltage is 63/64VDD.

11.2 DAC OPERATION DURING WAIT MODE

In WAIT mode, the DAC continues to output a xed voltage level which is set by the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur- ther power saving is required in WAIT mode.

11.3 DAC OPERATION DURING STOP MODE

In STOP mode, the DAC continues to output a x ed voltage level which is set by the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur- ther power saving is required in STOP mode. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DACDR R DACEN 0 DA5 DA4 DA3 DA2 DA1 DA0$000F W reset: 00000000 Figure 11-1. DAC Control and Data Register Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 DIGITAL TO ANALOG CONVERTER MC68HC05PL4 11-2 REV 2.0

11.4 DAC CHARACTERISTICS

(VDD = 4.0V –10%, VSS = 0 Vdc, TA = TL°C to TH°C, unless otherwise noted) Characteristic Symbol Min Max Unit Resolution — 6 6 Bits Absolute Accuracy 4.0V 2.0V Vout Vout 0 –VDD/64 V DAC Output Resistance R dac 7600 15600 W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-1 SECTION 12 INSTRUCTION SET This section describes the addressing modes and instruction types.

12.1 ADDRESSING MODES

The CPU uses eight addressing modes for exibility in accessing data. The addressing modes de ne the manner in which the CPU nds the data required to execute an instruction. The eight addressing modes are the following:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, No Offset
• Indexed, 8-Bit Offset
• Indexed, 16-Bit Offset
• Relative

12.1.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry ag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long.

12.1.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the rst b yte, and the immediate data value is the second byte. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INSTRUCTION SET MC68HC05PL4 12-2 REV 2.0

12.1.3 Direct

Direct instructions can access any of the rst 256 memory addresses with two bytes. The rst b yte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination.

12.1.4 Extended

Extended instructions use only three bytes to access any address in memory. The rst b yte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.

12.1.5 Indexed, No Offset

Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the rst 256 memor y locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF . Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

12.1.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the rst 511 memor y locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the rst 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-3

12.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The rst byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing.

12.1.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU nds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri es that it is within the span of the branch.

12.1.9 Instruction Types

The MCU instructions fall into the following v e categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INSTRUCTION SET MC68HC05PL4 12-4 REV 2.0

12.1.10 Register/Memory Instructions

Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU nds the other operand in memory. Table 12-1 lists the register/memory instructions. Table 12-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-5

12.1.11 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modi ed v alue back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions.

12.1.12 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any readable bit in the rst 256 memor y locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU nds the conditional br anch destination by adding the Table 12-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left ASL Arithmetic Shift Right ASR Clear Bit in Memory BCLR Set Bit in Memory BSET Clear CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INSTRUCTION SET MC68HC05PL4 12-6 REV 2.0 third byte to the program counter if the speci ed bit tests tr ue. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 12-3 lists the jump and branch instructions. Table 12-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if IRQ Pin High BIH Branch if IRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-7

12.1.13 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the rst 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the rst 256 b ytes of memory. The CPU can also test and branch based on the state of any bit in any of the rst 256 memory locations. Bit manipulation instructions use direct addressing. Table 12-4 lists these instructions.

12.1.14 Control Instructions

These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 12-5, use inherent addressing. Table 12-4. Bit Manipulation Instructions Instruction Mnemonic Clear Bit BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Set Bit BSET Table 12-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and Enable IRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable Interrupts WAIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INSTRUCTION SET MC68HC05PL4 12-8 REV 2.0

12.1.15 Instruction Set Summary

Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 12-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Add with Carry A ‹ (A) + (M) + (C) à — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ‹ (A) + (M) à — ààà IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X Logical AND A ‹ (A) Ù (M) — — àà — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left (Same as LSL) —— ààà DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ààà DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ‹ (PC) + 2 + rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ‹ 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ‹ (PC) + 2 + rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ‹ (PC) + 2 + rel ? Z = 1 ————— R E L 2 7 r r 3 BHCC rel Branch if Half-Carry Bit Clear PC ‹ (PC) + 2 + rel ? H = 0 ————— R E L 2 8 r r 3 C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-9 BHCS rel Branch if Half-Carry Bit Set PC ‹ (PC) + 2 + rel ? H = 1 ————— R E L 2 9 r r 3 BHI rel Branch if Higher PC ‹ (PC) + 2 + rel ? C Ú Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ‹ (PC) + 2 + rel ? C = 0 ————— R E L 2 4 r r 3 BIH rel Branch if IRQ Pin High PC ‹ (PC) + 2 + rel ? IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch if IRQ Pin Low PC ‹ (PC) + 2 + rel ? IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte (A) Ù (M) — — àà — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff p BLO rel Branch if Lower (Same as BCS) PC ‹ (PC) + 2 + rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch if Lower or Same PC ‹ (PC) + 2 + rel ? C Ú Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ‹ (PC) + 2 + rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ‹ (PC) + 2 + rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ‹ (PC) + 2 + rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ‹ (PC) + 2 + rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ‹ (PC) + 2 + rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ‹ (PC) + 2 + rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr rel Branch if bit n clear PC ‹ (PC) + 2 + rel ? M n = 0 ———— à DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRSET n opr rel Branch if Bit n Set PC ‹ (PC) + 2 + rel ? M n = 1 ———— à DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ‹ (PC) + 2 + rel ? 1 = 0 ————— R E L 2 1 r r 3 Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INSTRUCTION SET MC68HC05PL4 12-10 REV 2.0 BSET n opr Set Bit n Mn ‹ 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ‹ (PC) + 2; push (PCL) SP ‹ (SP) – 1; push (PCH) SP ‹ (SP) – 1 PC ‹ (PC) + rel CLC Clear Carry Bit C ‹ 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ‹ 0 — 0 — — — INH 9A 2 CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ‹ $00 A ‹ $00 X ‹ $00 M ‹ $00 M ‹ $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte (A) – (M) — — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) —— àà 1 DIR INH INH IX1 IX dd ff CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte (X) – (M) — — àà 1 IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ‹ (M) – 1 A ‹ (A) – 1 X ‹ (X) – 1 M ‹ (M) – 1 M ‹ (M) – 1 —— àà — DIR INH INH IX1 IX dd ff EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC M A X M M Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-11 INC opr INCA INCX INC opr,X INC ,X Increment Byte M ‹ (M) + 1 A ‹ (A) + 1 X ‹ (X) + 1 M ‹ (M) + 1 M ‹ (M) + 1 —— àà — DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ‹ Jump Address ————— DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ‹ (PC) + n (n = 1, 2, or 3) Push (PCL); SP ‹ (SP) – 1 Push (PCH); SP ‹ (SP) – 1 PC ‹ Conditional Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ‹ (M) — — àà — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ‹ (M) — — àà — IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left (Same as ASL) —— ààà DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 àà DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ‹ (X) · (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) —— ààà DIR INH INH IX1 IX ii ff NOP No Operation ————— I N H 9 D 2 Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC C b0b7 b0b7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 INSTRUCTION SET MC68HC05PL4 12-12 REV 2.0 ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory A ‹ (A) Ú (M) — — àà — IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left through Carry Bit —— ààà DIR INH INH IX1 IX dd ff ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit —— ààà DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ‹ $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ‹ (SP) + 1; Pull (CCR) SP ‹ (SP) + 1; Pull (A) SP ‹ (SP) + 1; Pull (X) SP ‹ (SP) + 1; Pull (PCH) SP ‹ (SP) + 1; Pull (PCL) ààààà INH 80 6 RTS Return from Subroutine SP ‹ (SP) + 1; Pull (PCH) SP ‹ (SP) + 1; Pull (PCL) INH SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator A ‹ (A) – (M) – (C) — — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ‹ 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ‹ 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in Memory M ‹ (A) — — àà — DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ‹ (X) — — àà — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-13 SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator A ‹ (A) – (M) — — ààà IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ‹ (PC) + 1; Push (PCL) SP ‹ (SP) – 1; Push (PCH) SP ‹ (SP) – 1; Push (X) SP ‹ (SP) – 1; Push (A) SP ‹ (SP) – 1; Push (CCR) SP ‹ (SP) – 1; I ‹ 1 PCH ‹ Interrupt Vector High Byte PCL ‹ Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 ————— DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts — à — — — INH 8F 2 A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask Ù Logical AND ii Immediate operand byte Ú Logical OR IMM Immediate addressing mode ¯ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ‹ Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag × Set or cleared n Any bit — Not affected Table 12-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesH I NZC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

INSTRUCTION SET MC68HC05PL4 12-14 REV 2.0 Table 12-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

0123456789 AB C D EF

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 ELECTRICAL SPECIFICATIONS REV 2.0 13-1 SECTION 13 ELECTRICAL SPECIFICATIONS This section contains the electrical and timing speci cations f or the MC68HC05PL4.

13.1 MAXIMUM RATINGS

Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. The device is not intended to operate at these conditions. The MCU contains circuitry that protects the inputs against dam- age from high static voltages; however, do not apply voltages higher than those shown below. Keep V IN and V OUT within the range from V SS to V DD. Connect unused inputs to the appropriate logical voltage level, either VSS or VDD.

13.2 OPERATING TEMPERATURE RANGE

13.3 THERMAL CHARACTERISTICS

Supply Voltage V DD –0.3 to +7.0 V Bootloader/Self-Check Mode (IRQ Pin Only) V IN VSS–0.3 to 17 V Current Drain Per Pin Excluding VDD and VSS I2 5 m A Operating Junction Temperature T J +150 °C Storage Temperature Range T STG –65 to +150 °C Characteristic Symbol Value Unit Operating Temperature Range MC68HC05PL4 T A TL to TH –40 to +80 °C Characteristic Symbol Value Unit Thermal Resistance SOIC PDIP qJA qJA °C/W °C/W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 ELECTRICAL SPECIFICATIONS MC68HC05PL4 13-2 REV 2.0

13.4 SUPPLY CURRENT CHARACTERISTICS

NOTES: 1. V DD as indicated, VSS = 0 V, TL £ TA £ TH, unless otherwise noted. 2. All values shown re ect a verage measurements. 3. Typical values at midpoint of voltage range, 25 °C only. 4. Run (Operating) I DD, Wait IDD: Measured using external square wave clock source to OSC1 pin or inter- nal oscillator, all inputs 0.2 VDC from either supply rail (V DD or VSS); no DC loads, less than 50 pF on all outputs, CL = 20pF on OSC2. 5. Wait, Stop I DD: All ports con gured as inputs , VIL = 0.2 VDC, VIH = VDD – 0.2 VDC. 6. Stop I DD measured with OSC1 = VDD. 7. Wait I DD is affected linearly by the OSC2 capacitance. Characteristic Symbol Min Typ Max Unit VDD = 4.4 to 3.6 V Internal RC (about 500kHz) Run Wait Stop External Crystal/Ceramic Resonator @ 5.12MHz Run Wait Stop IDD IDD IDD IDD IDD IDD 394 2.816 348 mA mA mA mA mA mA VDD = 2.5 to 2.0 V Internal RC (about 500kHz) Run Wait Stop External Crystal/Ceramic Resonator @ 2MHz Run Wait Stop IDD IDD IDD IDD IDD IDD 128 560 mA mA mA mA mA mA Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 ELECTRICAL SPECIFICATIONS REV 2.0 13-3

13.5 DC ELECTRICAL CHARACTERISTICS (4V)

NOTES: 1. V DD = 4.0V, VSS = 0 V, TL £ TA £ TH, unless otherwise noted. 2. All values shown re ect a verage measurements. 3. Typical values at midpoint of voltage range, 25 °C only. Characteristic Symbol Min Typ Max Unit Output Voltage Iload = 10mA Iload = –10mA VOL VOH VDD–0.1 0.1 V V Output High Voltage (Iload = –0.8 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET VOH VDD–0.8 — — V Output Low Voltage (Iload = 1.6 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET (Iload = 10 mA) LED/IRQ/VPP VOL VOL 0.15 0.20 0.4 0.4 V V High Sink Current (VOL = 0.4) Sink current per pin, PA5, PA6 Sink current total for PC4:7 pins IOL IOL mA mA Input High Voltage PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP VIH 0.7 x VDD —V DD V Input Low Voltage PA0:6, PB0:7, PC0:7,PD0:3, RESET,LED/IRQ/VPP VIL VSS — 0.3 x V DD V Input Current (with pulldowns disabled) PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP IIN —— –1 mA I/O Ports High-Z Leakage Current PA0:6, PB0:7, PC0:7, PD0:3 I OZ —— –10 mA Input Pulldown Current (VDD = 4.0V) PB0:7 I IL —3 46 0 mA Internal Pull-Up for PB0:7 R — 110 — k W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 ELECTRICAL SPECIFICATIONS MC68HC05PL4 13-4 REV 2.0

13.6 DC ELECTRICAL CHARACTERISTICS (2V)

NOTES: 1. V DD = 2.0V, VSS = 0 V, TL £ TA £ TH, unless otherwise noted. 2. All values shown re ect a verage measurements. 3. Typical values at midpoint of voltage range, 25 °C only. Characteristic Symbol Min Typ Max Unit Output Voltage Iload = 10mA Iload = –10mA VOL VOH VDD–0.1 0.1 V V Output High Voltage (Iload = –0.8 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET VOH VDD–0.3 — — V Output Low Voltage (Iload = 1.6 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET (Iload = 10 mA) LED/IRQ/VPP VOL VOL 0.15 0.30 V V High Sink Current (VOL = 0.4) Sink current per pin, PA5, PA6 Sink current total for PC4:7 pins IOL IOL mA mA Input High Voltage PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP VIH 0.7 x VDD —V DD V Input Low Voltage PA0:6, PB0:7, PC0:7,PD0:3, RESET,LED/IRQ/VPP VIL VSS — 0.2 x V DD V Input Current (with pulldowns disabled) PA0:6, PB0:7, PC0:7, PD0:3, RESET, LED/IRQ/VPP IIN —— –1 mA I/O Ports High-Z Leakage Current PA0:6, PB0:7, PC0:7, PD0:3 I OZ —— –10 mA Input Pulldown Current (VDD = 4.0V) PB0:7 I IL —61 1 mA Internal Pull-Up for PB0:7 R — 330 — k W Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 ELECTRICAL SPECIFICATIONS REV 2.0 13-5

13.7 CONTROL TIMING (4V)

NOTES: 1. V DD = 4.0V, VSS = 0 V, TL £ TA £ TH, unless otherwise noted. 2. The minimum period TILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC.

13.8 CONTROL TIMING (2V)

NOTES: 1. V DD = 2.0V, VSS = 0 V, TL £ TA £ TH, unless otherwise noted. 2. The minimum period TILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tCYC. Characteristic Symbol Min Max Unit Frequency of Oscillation (OSC) RC Oscillator Option Crystal Oscillator Option External Clock Source fOSC fOSC fOSC 200 0.1 DC 500 5.12 5.12 kHz MHz MHz Internal Operating Frequency, Crystal or External Clock (fOSC/2) RC Oscillator Option Crystal Oscillator Option External Clock Source fOP fOP fOP 100 0.05 DC 250 2.56 2.56 kHz MHz MHz Cycle Time RC Oscillator Option External oscillator or clock source tCYC tCYC 0.39 ms ms OSC1 Pulse Width (external clock input) t OH,tOL 195 — ns Timer Resolution Input Capture (TCAP) pulse width tRESL tTH, tTL 284 tCYC ns Interrupt Pulse Width Low (Edge-Triggered) t ILIH 284 — ns Interrupt Pulse Period t ILIL see note 2 — t CYC Characteristic Symbol Min Max Unit Frequency of Oscillation (OSC) RC Oscillator Option Crystal Oscillator Option External Clock Source fOSC fOSC fOSC 200 0.1 DC 500 kHz MHz MHz Internal Operating Frequency, Crystal or External Clock (fOSC/2) RC Oscillator Option Crystal Oscillator Option External Clock Source fOP fOP fOP 100 0.05 DC 250 kHz MHz MHz Cycle Time RC Oscillator Option External oscillator or clock source tCYC tCYC ms ms OSC1 Pulse Width (external clock input) t OH,tOL 5— n s Timer Resolution Input Capture (TCAP) pulse width tRESL tTH, tTL 284 tCYC ns Interrupt Pulse Width Low (Edge-Triggered) t ILIH 284 — ns Interrupt Pulse Period t ILIL see note 2 — t CYC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 ELECTRICAL SPECIFICATIONS MC68HC05PL4 13-6 REV 2.0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 MECHANICAL SPECIFICATIONS REV 2.0 14-1 SECTION 14 MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 28-pin PDIP , 28-pin SOIC, and 28-pin SSOP packages. 14.1 28-PIN PDIP (CASE 710) 14.2 28-PIN SOIC (CASE 751F) /C0052 /C0052 /C0077/C0073 /C0077/C0073/C0077 /C0077 /C0077/C0073 /C0073/C0077 /C0073 /C0073/C0077 /C0051 /C0052 /C0051/C0055 /C0051/C0052 /C0051 /C0051/C0055 /C0052 /C0051 /C0051/C0052/C0051 /C0052/C0051 /C0052 /C0052 /C0052 /C0052 /C0051 /C0052 /C0074 /C0077 %%! $"! /C0051 11 4 1528 B A C N K M J D /C0073 F HG L /C0077/C0073 /C0077/C0073/C0077 /C0077 /C0077/C0073 /C0073/C0077 /C0073 /C0073/C0077 /C0074 /C0077 /C0055 /C0055/C0052 /C0051 /C0051 /C0052 /C0051 /C0051 /C0055 /C0052 /C0051 /C0055 /C0055 /C0051 /C0052 /C0051 /C0055 /C0052 /C0051 /C0051 /C0052 /C0055 /C0089/C0052 /C0051 /C0052 $" /C0051 !$"! -A- -B- 11 4 1528 -T- C /C0073 M J -T- K 26X G 28X D 14X P R X 45° F Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MECHANICAL SPECIFICATIONS MC68HC05PL4 14-2 REV 2.0 14.3 28-PIN SSOP -D- A - T - e b N 1.00 DIA. H A 2 SIDE VIEW END VIEW TOP VIEW SEATING PLANE -E- 123 SEE DETAIL "A" - C - 2.36 BOTTOM VIEW E/2 D/21.00 1.00 DIA. PIN PINES-PHILI P C0.076 M+E M0.20 SD0.12 M T E+ c b BASE METAL 10SECTION G-G WITH LEAD FINISH 12-16° PARTING LINE DETAIL 'A' G G

0.25 BSC

L 0° MIN.

0.235 MIN

R CONTROLLING DIMENSION: MILLIMETERS.9. 1. MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES). ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.8. ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. FOR SOLDERING TO A SUBSTRATE. DIMENSION IS THE LENGTH OF TERMINAL PROTRUSIONS SHALL NOT EXCEED 0.15mm PER SIDE. AT THE PARTING LINE, MOLD FLASH OR DO INCLUDE MOLD MISMATCH AND ARE MEASURED INCLUDE MOLD FLASH OR PROTRUSIONS, BUT "D" & "E" ARE REFERENCE DATUMS AND DO NOT "T" IS A REFERENCE DATUM. NOTES: DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982. EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.07mm AT LEAST MATERIAL CONDITION. 10. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS. THIS PACKAGE OUTLINE DRAWING COMPLIES WITH JEDEC SPECIFICATION NO. MO-150 FOR THE LEAD COUNTS SHOWN 11. DIMENSIONS IN MM MIN. MAX. L N H e E D A A O L Y M B S NOM. A 2

0.65 BSC

1.86 0.13 1.73 1.78 0.21 1.991.73 0.05 1.68 5.20 5.30 5.38 7.65 0.63 0.75 7.80 7.90 0.95 10.07 10.20 10.33 b 0.25 0.38 b1 0.25 0.30 0.33 c1 0.09 0.15 0.16 c 0.09 0.20 1.25 REF.L1 O N E T 8,10 R 0.09 0.15 .407.402.397 .037 .311.307 .030.025 .301 .212.209.205 .066 .002 .068 .078 .008 .070.068 .005 .073 .0256 BSC NOM. MAX.MIN. DIMENSIONS IN INCH .010 .015 .010 .012 .013 .004 .008 .004 .006 .006 .049 REF. .004 .006 M M Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 A-1 APPENDIX A MC68HC705PL4 This appendix describes the MC68HC705PL4 and MC68HC705PL4B, the emula- tion parts for MC68HC05PL4 and MC68HC05PL4B respectively. The entire MC68HC05PL4 data sheet applies to the MC68HC705PL4 and MC68HC705PL4B, with exceptions outlined in this appendix. References to MC68HC705PL4 in this appendix refers to both the MC68HC705PL4 and MC68HC705PL4B devices, unless otherwise stated. A.1 INTRODUCTION The MC68HC705PL4 is an EPROM version of the MC68HC705PL4, and the MC68HC705PL4B is an EPROM version of the MC68HC705PL4B. Both HC705 parts are used as the emulation part for their MC68HC05 counterparts. Both MC68HC705 parts are functionally identical to their MC68HC05 counterparts, with the exception of the 4k-bytes user ROM is replaced by 4k-bytes user EPROM. A.2 MEMORY The MC68HC705PL4 memory map is shown on Figure A-1. A.3 BOOTLOADER MODE Bootloader mode is entered upon the rising edge of RESET if LED/IRQ/VPP pin is at VTST and PB0/KBI0 at V DD. The Bootloader program is masked in the ROM area from $1E00 to $1FEF . This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from an external EPROM. The bootloader performs one programming pass at 1ms per byte then does a verify pass. A.4 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Reg- ister located at address $001E. Please contact Freescale for programming board availability. Table A-1. MC68HC705PL4 and MC68HC705PL4B Differences Device Pin27 MC68HC705PL4 PA0 MC68HC705PL4B OSC2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 A-2 REV 2.0 Figure A-1. MC68HC705PL4B Memory Map A.4.1 EPROM Program Control Register (PCN) This register is provided for programming the on-chip EPROM in the MC68HC705PL4. ELAT – EPROM LATch control 0 = EPROM address and data bus con gured f or normal reads 1 = EPROM address and data bus con gured for programming (writes to EPROM cause address and data to be latched). EPROM is in programming mode and cannot be read if ELAT is 1. This bit should not be set when no programming voltage is applied to the VPP pin. PCR $001E bit-7 bit-6 bit-5 bit4 bit-3 bit-2 bit1 bit-0 Read RESERVED ELAT PGM Write Reset 00000000 I/O REGISTERS $0000 $001F $0020 $011F $0120 $0DFF $0E00 $1DFF $1E00 $1FEF $1FFF $1FF0 $00C0 $00FF STACK $1FF0-$1FF1 $1FF2-$1FF3 $1FF4-$1FF5 $1FF6-$1FF7 $1FF8-$1FF9 $1FFA-$1FFB $1FFC-$1FFD $1FFE-$1FFF Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 A-3 PGM – EPROM ProGraM command 0 = Programming power is switched OFF from EPROM array. 1 = Programming power is switched ON to EPROM array. If ELAT „ 1, then PGM = 0. A.4.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3. Set the PGM bit 4. Delay for a time t PGMR 5. Clear the PGM bit 6. Clear the ELAT bit The last two steps must be performed with separate CPU writes. CAUTION It is important to remember that an external programming voltage must be applied to the V PP pin while programming, but it should be equal to VDD during normal operations. Figure A-2 shows the o w required to successfully program the EPROM. A.5 EPROM PROGRAMMING SPECIFICATIONS Table A-2. EPROM Programming Electrical Characteristics (VDD = 4V –10%, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit Programming Voltage VPP — 12.5 — V Programming Current IPP — 5 10 mA Programming Time per byte tEPGM —1— m s Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 A-4 REV 2.0 Figure A-2. EPROM Programming Sequence START ELAT=1 Write EPROM byte EPGM=1 Wait 1ms EPGM=0 ELAT=0 Write additional byte? N Y END Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 REV 2.0 A-5 Figure A-3. MC68HC705PL4 Pin Assignment Figure A-4. MC68HC705PL4B Pin Assignment VSS VDD PC7 PC6 RESET PB7 PB6 PB5 PB4 PB3/KBI3 PC5 PC4 PB2/KBI2 PB1/KBI1 OSC1 PA0 PC0 PC1 PA1/DTMF PA2/TCAP PA3/TCMP PA4 PA5 PA6 PC2 PC3 LED/IRQ/VPP PB0/KBI0 VSS VDD PC7 PC6 RESET PB7 PB6 PB5 PB4 PB3/KBI3 PC5 PC4 PB2/KBI2 PB1/KBI1 OSC1 OSC2 PC0 PC1 PA1/DTMF PA2/TCAP PA3/TCMP PA4 PA5 PA6 PC2 PC3 LED/IRQ/VPP PB0/KBI0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

GENERAL RELEASE SPECIFICATION April 30, 1998 MC68HC05PL4 A-6 REV 2.0 A.6 SUPPLY CURRENT CHARACTERISTICS NOTES: 1. V DD as indicated, V SS = 0 V, T L T A T H , unless otherwise noted. 2. All values shown re ect a verage measurements. 3. Typical values at midpoint of voltage range, 25 C only. 4. Run (Operating) I DD , Wait I DD : Measured using external square wave clock source to OSC1 pin or inter- nal oscillator, all inputs 0.2 VDC from either supply rail (V DD or V SS ); no DC loads, less than 50 pF on all outputs, C L = 20pF on OSC2. 5. Wait, Stop I DD : All ports con gured as inputs , V IL = 0.2 VDC, V IH = V DD – 0.2 VDC. 6. Stop I DD measured with OSC1 = V DD 7. Wait I DD is affected linearly by the OSC2 capacitance. Characteristic Symbol Min Typ Max Unit V DD = 4.4 V to 3.6V Internal RC (about 500kHz) Run Wait Stop External Crystal/Ceramic Resonator @ 5.12MHz Run Wait Stop I DD I DD I DD I DD I DD I DD 966 486 4.398 922 m A m A m A mA m A m A Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...