68HC705L5

68HC05L5 MOTOROLA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 200

Technical content

REV. 2.0 NON-DISCLOSURE AGREEMENT REQUIRED 68HC05L5 68HC705L5 General Release Specification July 9, 1998 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification General Release Specification MC68HC(7)05L5 — Rev. 2.0

2 MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.  Motorola, Inc., 1998 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA List of Sections 3 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 List of Sections Section 8. Simple Serial Peripheral Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED List of Sections General Release Specification MC68HC(7)05L5 — Rev. 2.0

4 List of Sections MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Table of Contents 5 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Table of Contents Section 1. General Description

1.6.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP,

1.6.8 Port D (PD1–PD3/BP1–BP3,

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC(7)05L5 — Rev. 2.0

6 Table of Contents MOTOROLA

Section 2. Memory Map Section 3. Central Processor Unit (CPU) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Table of Contents 7 NON-DISCLOSURE AGREEMENT REQUIRED Section 4. Resets and Interrupts Section 5. Low-Power Modes Section 6. Parallel Input/Output (I/O) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC(7)05L5 — Rev. 2.0

8 Table of Contents MOTOROLA

Section 7. Oscillators/Clock Distributions Section 8. Simple Serial Peripheral Interface (SSPI) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Table of Contents 9 NON-DISCLOSURE AGREEMENT REQUIRED Section 9. Timer System Section 10. LCD Driver Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC(7)05L5 — Rev. 2.0

10 Table of Contents MOTOROLA

Section 11. Instruction Set Section 12. Electrical Specifications Section 13. Mechanical Specifications Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Table of Contents 11 NON-DISCLOSURE AGREEMENT REQUIRED Section 14. Ordering Information Appendix A. MC68HC705L5 A.3 Differences between MC68HC05L5 and MC68HC705L5 . . .182 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents General Release Specification MC68HC(7)05L5 — Rev. 2.0

12 Table of Contents MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA List of Figures 13 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 List of Figures Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED List of Figures General Release Specification MC68HC(7)05L5 — Rev. 2.0

14 List of Figures MOTOROLA

5-1 Clock State and STOP Recovery/Power-On Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA List of Figures 15 NON-DISCLOSURE AGREEMENT REQUIRED Figure Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED List of Figures General Release Specification MC68HC(7)05L5 — Rev. 2.0

16 List of Figures MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA List of Tables 17 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 List of Tables Table Title Page Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED List of Tables General Release Specification MC68HC(7)05L5 — Rev. 2.0

18 List of Tables MOTOROLA

A-1 Differences Between MC68HC05L5 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 19 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 1. General Description

1.1 Contents

1.6.8 Port D (PD1–PD3/BP1–BP3, and PD4–PD7/FP34–FP27) .29 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

20 General Description MOTOROLA

1.2 Introduction

The MC68HC05L5 is an 80-pin microcontroller unit (MCU) with highly sophisticated on-chip peripheral functions. The memory map includes 8 Kbytes of user ROM and 256 bytes of static RAM. The MCU has five parallel ports: A, B, C, D, and E. The MC68HC05L5 includes a timebase circuit, 8- and 16-bit timers, a computer operating properly (COP) watchdog timer, liquid crystal display (LCD) drivers, and a simple serial peripheral interface (SSPI).

1.3 Features

Features of the MC68HC05L5 MCU include:

• Low-cost HC05 core
• 8,208 bytes of user ROM and 256 bytes of user static RAM
• General-purpose data pins: – 14 bidirectional pins – 10 input/ouptut-only pins – 15 output-only pins, including 8-bit key wakeup interrupts
• Pullup resistors options
• Open-drain outputs options
• Two interrupt request (IRQ) inputs
• 16-bit timer with input capture and output compare (timer 1)
• 8-bit event counter/modulus clock divider (timer 2)
• Simple serial peripheral interface (SSPI)
• LCD drivers — 1-to-4 backplane drivers x 27-to-39 frontplane drivers
• On-chip timebase circuits with COP watchdog timer and timebase interrupts
• Dual oscillators and selectable system clock frequency
• Power-saving stop mode and wait mode
• 80-pin quad flat pack (QFP) package Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 21 NON-DISCLOSURE AGREEMENT REQUIRED

1.4 MCU Structure

Figure 1-1 shows the structure of the MC68HC05L5 MCU. Figure 1-1. Block Diagram PA0 PC5/EVO PC6/IRQ2 PC7/IRQ1 PC0/SDI TIMEBASE INTERNAL COP CPU M68HC05 CPU ALU CPU REGISTERS CONTROL SELF-CHECK ROM SYSTEM SYSTEM PROCESSOR CLOCK

496 BYTES

÷ 2 PA1 PA2 PA3 PA4 PORT A DATA A PA5 PA6 PA7 OSC SEL LCD DRIVERS USER ROM RESET VDD OSC1 OSC2 VSS PORT B DATA B KEY WAKEUP PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB6/KWI6 PB7/KWI7 PB5/KWI5 PB4/KWI4 PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PORT C DATA C SPITIMER2 FP0–PF26 PORT E FP36/PD6 BP0 BP2/PD2 BP1/PD1 FP35/PD7 FP37/PD5 FP38/PD4 BP3/PD3 FP28/PE6 FP34/PE0 FP32/PE2 FP33/PE1 FP27/PE7 FP29/PE5 FP30/PE4 FP31/PE3 PORT D VLCD3 VLCD2 VLCD1 DIV NDLY (1)

8028 BYTES

256 BYTES

Note 1. The NDLY pin should be connected toVDD. DIR REGDIR REGDIR REG Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

22 General Description MOTOROLA

NOTE: A line over a signal name indicates an active low signal. For example, RESET is active low.

1.5 Mask Options

The three mask options on the MC68HC05L5 are: 1. RSTR: RESET pin pullup resistor 2. OSCR: OSC feedback resistor 3. XOSCR: XOSC feedback/damping resistor See 2.5.6 Mask Option Status Register. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Functional Pin Description MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 23 NON-DISCLOSURE AGREEMENT REQUIRED

1.6 Functional Pin Description

The MC68HC05L5 is available in an 80-pin QFP. The pin assignment is shown inFigure 1-2. Figure 1-2. Pin Assignment for Single-Chip Mode 20 40 41 6180 VDD FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 VLCD1 VSS NDLY(1) XOSC1 XOSC2 RESET VSS FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1/PD1 BP2/PD2 BP3/PD3 VDD PC7/IRQ1 PC6/IRQ2 PC5/EVO PC4/EVI PC3/TCAP PC2/SCK FP27/PE7 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO Note 1. The NDLY pin should be connected toVDD. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

24 General Description MOTOROLA

Table 1-1. Pin Configuration Pin Number SCM, Self-Check I/O Pin Number SCM, Self-Check I/O PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 I/O I/O I/O I/O I/O I/O I/O I/O FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 O O O O O O O O O O O O O O O O O O O O O O O O O O O PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 I I I I I I I I PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6/IRQ2 PC7/IRQ1 I/O I/O I/O I/O I/O I/O I I

17 NDL Y (1) I

I I O O I O I O FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 O O O O O O O O VLCD1 VLCD2 VLCD3 BP3/PD3 BP2/PD2 BP1/PD1 BP0 I I I O O O O FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 O O O O Note 1.The NDLY pin should be connected toVDD . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Functional Pin Description MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 25 NON-DISCLOSURE AGREEMENT REQUIRED

1.6.1 VDD and VSS

Power is supplied to the MCU through VDD and VSS .VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.

1.6.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the connections for the 2-pin on-chip oscillator. The OSC1 and OSC2 pins can accept:

• A crystal as shown inFigure 1-3 (a)
• An external clock signal as shown inFigure 1-3 (b) The frequency, fOSC , of the oscillator or external clock source is divided by 64 to produce the internal operating frequency, fOP , by default.

1.6.2.1 Crystal or Ceramic Resonator

The circuit inFigure 1-3 (a)shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of ROF between OSC1 and OSC2 may be selected as a mask option for MC68HC05L5. Typical ROF resistor value is 2 MΩ . Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

26 General Description MOTOROLA

Figure 1-3. Oscillator Connections

1.6.2.2 External Clock

An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown inFigure 1-3. This configuration is possible regardless of how the oscillator is set up.

1.6.3 XOSC1 and XOSC2

The XOSC1 and XOSC2 pins are the connections for the 2-pin on-chip oscillator. The XOSC1 and XOSC2 pins can accept:

• A crystal as shown inFigure 1-4 (a)
• An external clock signal as shown inFigure 1-4 (b) The frequency, fOSC , of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP , if selected by SYS1–SYS0 bits. When XOSC is not used, the XOSC1 pin must be connected to the RESET pin to assure proper initialization of the clock circuitry. XOSC2 pin should remain unconnected. MCU C O2 (a) Crystal Connections OSC1 OSC2 C O1 R OF UNCONNECTED EXTERNAL CLOCK (b) External Clock Source Connection OSC1 OSC2 MCU

4 MHz (TYP)

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Functional Pin Description MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 27 NON-DISCLOSURE AGREEMENT REQUIRED

1.6.3.1 Crystal Resonator

The circuit inFigure 1-4 (a)shows a typical 2-pin oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of RXOF between XOSC1 and XOSC2 and a damping resistor of RXOD in series to XOSC2 may be selected as a mask option. Typical RXOF resistor value is 5.5 MΩ , and RXOD resistor value is 320 kΩ . Figure 1-4. Oscillator Connections

1.6.3.2 External Clock

An external clock from another CMOS-compatible device can be connected to the XOSC1 input, with the XOSC2 input not connected, as shown inFigure 1-4 (b). This configuration is possible regardless of how the oscillator is set up. MCU C XO2 (a) Crystal Connections XOSC1 XOSC2 C XO1 R XOF UNCONNECTED EXTERNAL CLOCK (b) External Clock Source Connection XOSC1 XOSC2 MCU R XOD 32.768 kHz (TYP) MASK OPTIONS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

28 General Description MOTOROLA

1.6.4 RESET

This pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. When power is removed, theRESET pin contains a steering diode to discharge any voltage on the pin to VDD . The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. An internalRESET pin pullup resistor may be selected as a mask option. A typical pullup resistor value is 33 kΩ .

1.6.5 Port A (PA0–PA7)

Port A is an 8-bit I/O port. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. Port A outputs may be configured as open-drain outputs and connected to a pullup resistor by software option.

1.6.6 Port B (PB0–PB7/KWI0–KWI7)

Port B is an 8-bit input-only port that shares its lines with the key wakeup interrupt (KWI) system. Port B has a pullup option by software option.

1.6.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI,

PC5/EVO, PC6/IRQ2, and PC7/IRQ1) Port C is a 6-bit I/O port and 2-bit input-only port. The state of the PC0–PC5 pins are software programmable and all port C lines are configured as inputs during power-on or reset. All port C lines may connect to a pullup resistor by software option.

• Bits PC0–PC2 are shared with the SSPI subsystem and may be configured as open-drain outputs.
• Bit 3 is shared with the TCAP pin of timer 1 and may be configured as an open-drain output.
• Bit 4 is shared with the EVI bit of timer 2 and may be configured as an open-drain output. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Functional Pin Description MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 29 NON-DISCLOSURE AGREEMENT REQUIRED

• Bit 5 is shared with the EVO bit of timer 2 and may be configured as an open-drain output.
• Bit 6 is shared with theIRQ2 input. This bit is an input-only pin.
• Bit 7 is shared with theIRQ1 input. This bit is an input-only pin.

1.6.8 Port D (PD1–PD3/BP1–BP3 and PD4–PD7/FP34–FP27)

Port D is a 7-bit output-only port that shares its bits with the LCD backplane/frontplane drivers. Port D lines are configured as LCD outputs during power-on or reset. PD1–PD3 and PD4–PD7 outputs may be configured as open-drain outputs by a software option.

1.6.9 Port E (PE0–PE7/FP38–FP35)

Port E is an 8-bit output-only port that shares its bits with LCD frontplane drivers. Port E lines are configured as LCD outputs during power-on or reset. PE0–PE3 and PE4–PE7 outputs may be configured as open- drain outputs by a software option.

1.6.10 VLCD1, VLCD2, and VLCD3

These pins provide offset to the LCD driver bias for adjusting the contrast of the LCD.

1.6.11 NDLY

This pin is reserved for factory test and should be connected to VDD in single-chip mode (user mode). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

30 General Description MOTOROLA

1.7 Modes of Operation

The MC68HC05L5 has two operating modes:

• Single-chip mode (SCM)
• Self-check mode Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The self-check capability of MC68HC05L5 provides an internal check to determine if the device is functional.

1.7.1 Mode Entry

Mode entry is done at the rising edge of theRESET pin. Once the device enters one of the modes, the mode cannot be changed by software. Only an external reset can change the mode. At the rising edge of theRESET pin, the device latches the states of IRQ1 andIRQ2 and places itself in the specified mode. While the RESET pin is low, all pins are configured as single-chip mode. Table 1-2 shows the states ofIRQ1 andIRQ2 for each mode entry. High voltage VTST = 2 x VDD is required to select modes other than single-chip mode. Table 1-2. Mode Select Summary Modes RESET PC6/ IRQ1 PC7/ IRQ2 Single-chip (user) mode V SS or VDD VSS or VDD Self-check mode V TST VDD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA General Description 31 NON-DISCLOSURE AGREEMENT REQUIRED Figure 1-5.Mode Entry Diagram

1.7.2 Single-Chip Mode (SCM)

In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows the maximum number of I/O pins for on-chip peripheral functions, for example, ports A through E, and LCD drivers.

1.7.3 Self-Check Mode

In this mode, the reset vector is fetched from a 496-byte internal self- check ROM at $3E00–$3FEF. The self-check ROM contains a self- check program to test the functions of internal modules. Since this mode is not a normal user mode, all of the privileged control bits are accessible. This allows the self-check mode to be used for self- test of the device. VTST VDD VSS VDD VSS IRQ2 IRQ1 RESET SINGLE-CHIP MODE VTST = 2 x VDD VDD VSS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Description General Release Specification MC68HC(7)05L5 — Rev. 2.0

32 General Description MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 33 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 2. Memory Map

2.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

34 Memory Map MOTOROLA

2.2 Introduction

The MC68HC05L5 contains an 8,192-byte mask ROM, 480 bytes of self- check ROM, and 256 bytes of RAM. An additional 16 bytes of mask ROM are provided for user vectors at $3FF0–$3FFF. The MCU’s memory map is shown inFigure 2-1. Figure 2-1.Memory Map $0000 $000F $0010 $003F SRAM

64 BYTES

$0000 $003F $0040 $00C0 $00FF $013F $0140 $0FFF $1000 $2FFF $3000 $3DFF $3E00 $3FDF $3FE0 $3FEF $3FF0 $3FFF UNUSED MASK ROM UNUSED SELF-CHECK ROM TEST VECTORS USER VECTORS DUAL-MAPPED

16 BYTES

48 BYTES

8 KBYTES

480 BYTES

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Input/Output and Control Registers MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 35 NON-DISCLOSURE AGREEMENT REQUIRED

2.3 Input/Output and Control Registers

The input/output (I/O) and control registers reside in locations $0000–$003F. A summary of these registers is shown inFigure 2-3. The bit assignments for each register are shown inFigure 2-4. Reading from unimplemented bits (denoted by shading) will return unknown states (unless explicitly defined to read 0), and writing to unimplemented bits will have no effect. See alsoFigure 2-2. Figure 2-2. Register Description Key

2.3.1 Read/Write Bits

Read/write bits are typically control bits. They are, in general, not modified by a module. Reset indicates the initial value of the latch.

2.3.2 Read-Only Bits

Read-only bits are status flag bits. They are indicators of module status. Reset indicates the value that will be read immediately after system reset or before the module is enabled. $003E Miscellaneous Register (MISC) Read: FTUP STUP 0 0 SYS1 SYS0 FOSCE OPTMWrite: Reset: * * 001010 Register Address (Main map unless otherwise specified) Bit Name (Mnemonic)Register Name (Full) Register Name (Mnemonic) Read Write Read-Only Bit Read/Write Bit Reset Value Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

36 Memory Map MOTOROLA

2.3.3 Write-Only Bits

Write-only bits are control bits. They typically return a state of 0 to prevent an inadvertent write to this bit by a READ-MODIFY-WRITE instruction. Reset indicates the value that will be read immediately after system reset, which is the forced read value (typically 0).

2.3.4 Reserved Bits

Reserved bits are read-only bits that typically read 0. Writes to these bits are ignored, and the user should not write 1 for future compatibility. Reset indicates the value that will be read immediately after system reset which is the forced read value (typically 0).

2.3.5 Reset Value

Values specified on the row markedReset: are initial values of register bits after system reset. Those bits unaffected by reset are marked with the letter U. Those bits that are unaffected by reset but initialized by power-on reset are marked with an asterisk (*).

2.3.6 Option Map

Address locations $0000–$000F are dual mapped. When the OPTM bit in the MISC register is cleared, the main address map is accessed. When the OPTM bit in the MISC register is set, the option address map is accessed. NOTE: Although not necessary for this device, for future compatibility the OPTM bit should be cleared when accessing memory locations $0010 and above. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Summary of Internal Registers and I/O Map MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 37 NON-DISCLOSURE AGREEMENT REQUIRED

2.4 Summary of Internal Registers and I/O Map

Figure 2-3 contains a detailed memory map of the I/O registers. Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0000 Port A Data Register (PORTA) Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0Write: Reset: Unaffected by reset $0001 Port B Data Register (PORTB) Read: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0Write: Reset: Unaffected by reset $0002 Port C Data Register (PORTC) Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0Write: Reset: Unaffected by reset $0003 Port D Data Register (PORTD) Read: PD7 PD6 PD5 PD4 PD3 PD2 PD1 1Write: Reset: 1 1 1 1 1 1 1 1 $0004 Port E Data Register (PORTE) Read: PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0Write: Reset: 1 1 1 1 1 1 1 1 $0005 Reserved R R R R R R R R $0006 Reserved R R R R R R R R $0007 Reserved R R R R R R R R $0008 Interrupt Control Register (INTCR) Read: IRQ1E IRQ2E 0 KWIE IRQ1S IRQ2S 0 0Write: Reset: 0 0 0 0 0 0 0 0 $0009 Interrupt Status Register (INTSR) Read: IRQ1F IRQ2F 0 KWIF 0 0 0 0 Write: RIRQ1 RIRQ2 RKWIF Reset: 0 0 0 0 0 0 0 0 = Unimplemented R = Reserved Figure 2-3. Main I/O Map (Sheet 1 of 6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

38 Memory Map MOTOROLA

$000A Serial Peripheral Control Register (SPCR) Read: SPIE SPE DORD MSTR 0 0 0 SPRWrite: Reset: 0 0 0 0 0 0 0 0 $000B Serial Peripheral Status Register (SPSR) Read: SPIF DCOL 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 $000C Serial Peripheral Data Register (SPDR) Read: MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 2 LSBWrite: Reset: Unaffected by reset $000D Reserved R R R R R R R R $000E Reserved R R R R R R R R $000F Reserved R R R R R R R R $0010 Timer Base Control Register 1 (TBCR1) Read: TBCLK 0 LCLK 0 0 0 T2R1 T2R0Write: Reset: 0 0 0 0 0 0 0 0 $0011 Timer Base Control Register 2 (TBCR2) Read: TBIF TBIE TBR1 TBR0 0 0 00 Write: RTBIF COPE COPC Reset: 0 0 1 1 0 0 0 0 $0012 Timer Control Register (TCR) Read: ICIE OC1IE TOIE 0 0 0 IEDG OLVLWrite: Reset: 0 0 0 0 0 0 U 0 $0013 Timer Status Register (TSR) Read: ICF OC1F TOF 0 0 0 0 0 Write: Reset: U U U 0 0 0 0 0 $0014 Input Capture Register High (ICH) Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 Write: Reset: Unaffected by reset = Unimplemented R = Reserved U = Unaffected Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 2-3. Main I/O Map (Sheet 2 of 6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Summary of Internal Registers and I/O Map MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 39 NON-DISCLOSURE AGREEMENT REQUIRED $0015 Input Capture Register Low (ICL) Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write: Reset: Unaffected by reset $0016 Output Compare Register 1 High (OC1H) Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8Write: Reset: Unaffected by reset $0017 Output Compare Register 1 Low (OC1L) Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0Write: Reset: Unaffected by reset $0018 Timer Counter Register High (TCNTH) Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8Write: Reset: Unaffected by reset $0019 Timer Counter Register Low (TCNTL) Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0Write: Reset: Unaffected by reset $001A Alternate Timer Counter Register High (ACNTH) Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8Write: Reset: Unaffected by reset $001B Alternate Timer Counter Register Low (ACMTL) Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0Write: Reset: Unaffected by reset $001C Timer Control Register 2 (TCR2) Read: TI2IE OC2IE 0 T2CLK IM2 IL2 OE2 OL2Write: Reset: 0 0 0 0 0 0 0 0 $001D Timer Status Register 2 (TSR2) Read: TI2F OC2F 00 00 00Write: RTI2F ROC2F Reset: 0 0 0 0 0 0 0 0 $001E Output Compare Register 2 (OC2) Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 2-3. Main I/O Map (Sheet 3 of 6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

40 Memory Map MOTOROLA

$001F Timer Counter Register 2 (TCNT2) Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0Write: Reset: 0 0 0 0 0 0 0 1 $0020 LCD Control Register (LCDCR) Read: LCDE DUTY1 DUTY0 0 PEH PEL PDH 0Write: Reset: 0 0 0 0 0 0 0 0 $0021 LCD Data Register 1 (LCDR1) Read: F1B3 F1B2 F1B1 F1B0 F0B3 F0B2 F0B1 F0B0Write: Reset: Unaffected by reset $0022 LCD Data Register 2 (LCDR2) Read: F3B3 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0Write: Reset: Unaffected by reset $0023 LCD Data Register 3 (LCDR3) Read: F5B3 F5B2 F5B1 F5B0 F4B3 F4B2 F4B1 F4B0Write: Reset: Unaffected by reset $0024 LCD Data Register 4 (LCDR4) Read: F7B3 F7B2 F7B1 F7B0 F6B3 F6B2 F6B1 F6B0Write: Reset: Unaffected by reset $0025 LCD Data Register 5 (LCDR5) Read: F9B3 F9B2 F9B1 F9B0 F8B3 F8B2 F8B1 F8B0Write: Reset: Unaffected by reset $0026 LCD Data Register 6 (LCDR6) Read: F11B3 F11B2 F11B1 F11B0 F10B3 F10B2 F10B1 F10B0Write: Reset: Unaffected by reset $0027 LCD Data Register 7 (LCDR7) Read: F13B3 F13B2 F13B1 F13B0 F12B3 F12B2 F12B1 F12B0Write: Reset: Unaffected by reset Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 2-3. Main I/O Map (Sheet 4 of 6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Summary of Internal Registers and I/O Map MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 41 NON-DISCLOSURE AGREEMENT REQUIRED $0028 LCD Data Register 8 (LCDR8) Read: F15B3 F15B2 F15B1 F15B0 F14B3 F14B2 F14B1 F14B0Write: Reset: Unaffected by reset $0029 LCD Data Register 9 (LCDR9) Read: F17B3 F17B2 F17B1 F17B0 F16B3 F16B2 F16B1 F16B0Write: Reset: Unaffected by reset $002A LCD Data Register 10 (LCDR10) Read: F19B3 F19B2 F19B1 F19B0 F18B3 F18B2 F18B1 F18B0Write: Reset: Unaffected by reset $002B LCD Data Register 11 (LCDR11) Read: F21B3 F21B2 F21B1 F21B0 F20B3 F20B2 F20B1 F20B0Write: Reset: Unaffected by reset $002C LCD Data Register 12 (LCDR12) Read: F23B3 F23B2 F23B1 F23B0 F22B3 F22B2 F22B1 F22B0Write: Reset: Unaffected by reset $002D LCD Data Register 13 (LCDR13) Read: F25B3 F25B2 F25B1 F25B0 F24B3 F24B2 F24B1 F24B0Write: Reset: Unaffected by reset $002E LCD Data Register 14 (LCDR14) Read: F27B3 F27B2 F27B1 F27B0 F26B3 F26B2 F26B1 F26B0Write: Reset: Unaffected by reset $002F LCD Data Register 15 (LCDR15) Read: F29B3 F29B2 F29B1 F29B0 F28B3 F28B2 F28B1 F28B0Write: Reset: Unaffected by reset $0030 LCD Data Register 16 (LCDR16) Read: F31B3 F31B2 F31B1 F31B0 F30B3 F30B2 F30B1 F30B0Write: Reset: Unaffected by reset Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 2-3. Main I/O Map (Sheet 5 of 6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

42 Memory Map MOTOROLA

$0031 LCD Data Register 17 (LCDR17) Read: F33B3 F33B2 F33B1 F33B0 F32B3 F32B2 F32B1 F32B0Write: Reset: Unaffected by reset $0032 LCD Data Register 18 (LCDR18) Read: F35B3 F35B2 F35B1 F35B0 F34B3 F34B2 F34B1 F34B0Write: Reset: Unaffected by reset $0033 LCD Data Register 19 (LCDR19) Read: F37B3 F37B2 F37B1 F37B0 F36B3 F36B2 F36B1 F36B0Write: Reset: Unaffected by reset $0034 LCD Data Register 20 (LCDR20) Read: 0 0 0 0 F38B3 F38B2 F38B1 F38B0Write: Reset: Unaffected by reset $0035 Reserved R R R R R R R R $0036 Reserved R R R R R R R R $0037 Reserved R R R R R R R R $0038 Reserved R R R R R R R R $0039 Reserved R R R R R R R R $003A Reserved R R R R R R R R $003B Reserved R R R R R R R R $003C Reserved R R R R R R R R $003D Reserved R R R R R R R R $003E Miscellaneous Register (MISC) Read: FTUP STUP 0 0 SYS1 SYS0 FOSCE OPTMWrite: Reset: * * 0 0 1 0 1 0 $003F Reserved R R R R R R R R * Unaffected by reset but initialized by power-on reset = Unimplemented R = Reserved Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 2-3. Main I/O Map (Sheet 6 of 6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Option Map for I/O Configurations MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 43 NON-DISCLOSURE AGREEMENT REQUIRED

2.5 Option Map for I/O Configurations

Most of the I/O configurations are done in the option map (Figure 2-4). Some options still remain as mask options for the MC68HC05L5 such as a pullup resistor for theRESET pin and resistors for the OSC1/OSC2 and XOSC1/XOSC2 pins. These mask options may be read by the MOSR ($000F) in the option map. The option map is located at $0000–$000F of the main memory map and it is available when the OPTM bit in the MISC register ($003E) is set. Main registers at $0000–$000F are not available when OPTM = 1. I/O port data direction registers are contained in the option map in Figure 2-4. Addr. Register Name Bit 7 6 5 4321 Bit 0 $0000 Port A Data Direction Register (DDRA) Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0Write: Reset: 0 0 0 00000 $0001 Reserved R R R RRRRR $0002 Port C Data Direction Register (DDRC) Read: 0 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0Write: Reset: 0 0 0 00000 $0003 Reserved R R R RRRRR $0004 Reserved R R R RRRRR $0005 Reserved R R R RRRRR $0006 Reserved R R R RRRRR $0007 Reserved R R R RRRRR $0008 Resistor Control Register 1 (RCR1) Read: 0 0 0 0 RBH RBL RAH RALWrite: Reset: 0 0 0 00000 R = Reserved Figure 2-4. Option Map (Sheet 1 of 2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

44 Memory Map MOTOROLA

$0009 Resistor Control Register 2 (RCR2) Read: RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0Write: Reset: 0 0 0 00000 $000A Open-Drain Output Control Register 1 (WOM1) Read: DWOMH DWOML EWOMH EWOML 0 0 AWOMH AWOMLWrite: Reset: 0 0 0 00000 $000B Open-Drain Output Control Register 2 (WOM2) Read: 0 0 CWOM5 CWOM4 CWOM3 CWOM2 CWOM1 CWOM0Write: Reset: 0 0 0 00000 $000C Reserved R R R RRRRR $000D Reserved R R R RRRRR $000E Key Wakeup Input Enable Register (KWIEN) Read: KWIE7 KWIE6 KWIE5 KWIE4 KWIE3 KWIE2 KWIE1 KWIE0Write: Reset: 0 0 0 00000 $000F Mask Option Status Register Read: RSTR OSCR XOSCR 00000 Write: Reset: U U U 00000 = Unimplemented R = Reserved U = Unaffected Addr. Register Name Bit 7 6 5 4321 Bit 0 Figure 2-4. Option Map (Sheet 2 of 2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Option Map for I/O Configurations MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 45 NON-DISCLOSURE AGREEMENT REQUIRED

2.5.1 Resistor Control Register 1

Bits 7–4 — Reserved These bits are not used and always read as logic 0. RBH — Port B Pullup Resistor (H) When this bit is set, pullup resistors are connected to the upper four bits of port B. This bit is cleared on reset. RBL — Port B Pullup Resistor (L) When this bit is set, pullup resistors are connected to the lower four bits of port B. This bit is cleared on reset. RAH — Port A Pullup Resistor (H) When this bit is set, pullup resistors are connected to the upper four bits of port A. This bit is cleared on reset. RAL — Port A Pullup Resistor (L) When this bit is set, pullup resistors are connected to the lower four bits of port A. This bit is cleared on reset. Address: Option Map — $0008 Bit 7 654321 Bit 0 Read:

0000 R B H R B L R A H R A L

Write: Reset: 00000000 Figure 2-5. Resistor Control Register 1 (RCR1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

46 Memory Map MOTOROLA

2.5.2 Resistor Control Register 2

RC x — Port C Pullup Resistor (Bitx) When RC x bit is set, the pullup resistor is connected to the corresponding bit of port C. This bit is cleared on reset.

2.5.3 Open-Drain Output Control Register 1

DWOMH — Port D Open-Drain Mode (H) When this bit is set, the upper four bits of port D are configured as open-drain outputs if these bits are selected as port D output by the PDH bit in the LCDCR. This bit is cleared on reset. DWOML — Port D Open-Drain Mode (L) When this bit is set, the lower three bits of port D are configured as open-drain outputs if the corresponding BPx pin is not used by the LCD driver. This bit is cleared on reset. Address: Option Map — $0009 Bit 7 654321 Bit 0 Read: RC7 RC6 RC5 RC4 RC3 RC1 RC1 RC0 Write: Reset: 00000000 Figure 2-6. Resistor Control Register 2 (RCR2) Address: Option Map — $000A Bit 7 654321 Bit 0 Read: DWOMH DWOML EWOMH EWOML 0 0 AWOMH AWOML Write: Reset: 00000000 Figure 2-7. Open-Drain Output Control Register 1 (WOM1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Option Map for I/O Configurations MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 47 NON-DISCLOSURE AGREEMENT REQUIRED EWOMH — Port E Open-Drain Mode (H) When this bit is set, the upper four bits of port E (that are configured as I/O output by the PEH bit in the LCDCR) are configured as open- drain outputs. This bit is cleared on reset. EWOML — Port E Open-Drain Mode (L) When this bit is set, the lower four bits of port E (that are configured as I/O output by the PEL bit in the LCDCR) are configured as open- drain outputs. This bit is cleared on reset. Bits 3 and 2 — Reserved These bits are not used and always return to logic 0. AWOMH — Port A Open-Drain Mode (H) When this bit is set, the upper four bits of port A that are configured as output (corresponding to the DDRA bit set) become open-drain outputs. This bit is cleared on reset. AWOML — Port E Open-Drain Mode (L) When this bit is set, the lower four bits of port A that are configured as output (corresponding DDRA bit set) become open-drain outputs. This bit is cleared on reset. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

48 Memory Map MOTOROLA

2.5.4 Open-Drain Output Control Register 2

Bits 7 and 6 — Reserved These bits are not used and always read as logic 0. CWOM x — Port C Open-Drain Mode (Bitx) When CWOM x bit is set, port C bits x are configured as open-drain outputs if DDRCx is set. This bit is cleared on reset.

2.5.5 Key Wakeup Input Enable Register

KWIE x — Key Wakeup Input Enable (Bitx) When KWIE x bit is set, the KWIx (PBx) input is enabled for key wakeup interrupt. This bit is cleared on reset. Address: Option Map — $000B Bit 7 654321 Bit 0 Read: 0 0 CWOM5 CWOM4 CWOM3 CWOM2 CWOM1 CWOM0 Write: Reset: 00000000 Figure 2-8. Open-Drain Output Control Register 2 (WOM2) Address: Option Map — $000E Bit 7 654321 Bit 0 Read: KWIE7 KWIE6 KWIE5 KWIE4 KWIE3 KWIE2 KWIE1 KWIE0 Write: Reset: 00000000 Figure 2-9. Key Wakeup Input Enable Register (KWIEN) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Option Map for I/O Configurations MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Memory Map 49 NON-DISCLOSURE AGREEMENT REQUIRED

2.5.6 Mask Option Status Register

The mask option status register (MOSR) indicates the state of mask options specified prior to production of the MC68HC05L5. RSTR — RESET Pin Pullup Resistor When this bit is set, it indicates an internal pullup resistor is attached to theRESET pin by mask option. OSCR — OSC Feedback Resistor When this bit is set, it indicates that an internal feedback resistor is attached between OSC1 and OSC2 by mask option. XOSCR — OSC Feedback Resistor When this bit is set, it indicates that an internal feedback resistor is attached between XOSC1 and XOSC2. The damping resistor at the XOSC2 pin is attached by mask option. Bits 4–0 — Reserved These bits are not used and always read as logic 0. Address: Option Map — $000F Bit 7 654321 Bit 0 Read: RSTR OSCR XOSCR 00000 Write: Reset: U U U 00000 = Unimplemented U = Unaffected Figure 2-10. Mask Option Status Register (MOSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Memory Map General Release Specification MC68HC(7)05L5 — Rev. 2.0

50 Memory Map MOTOROLA

2.6 RAM

The 256-byte internal RAM is positioned at $0040–$013F in the memory map. The lower 192 bytes are positioned in the page zero which are accessible by the direct addressing mode. The upper 64 bytes of this area (page zero) are used for the CPU stack area. Care should be taken if the stack area is used for data storage. The remaining 64 byte of RAM at $0100–$013F are accessed by extended addressing mode. The RAM is implemented with static cells and retains its contents during the stop and wait modes.

2.7 Self-Check ROM

Self-check ROM is 480 bytes of mask ROM positioned at $3E00–$3FDF. This ROM contains self-check programs and reset/interrupt vectors in the self-check mode.

2.8 Mask ROM

The 8,192-byte user ROM is positioned at $1000–$2FFF, and an additional 16 bytes of ROM are located at $3FF0–$3FFF for user vectors. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Central Processor Unit (CPU) 51 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 3. Central Processor Unit (CPU)

3.1 Contents

3.2 Introduction

This section describes the central processor unit (CPU). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Central Processor Unit (CPU) General Release Specification MC68HC(7)05L5 — Rev. 2.0

52 Central Processor Unit (CPU) MOTOROLA

3.3 CPU Registers

The MCU contains five registers as shown inFigure 3-1. The interrupt stacking order is shown inFigure 3-2. Figure 3-1. Programming Model Figure 3-2. Stacking Order A X HI N Z C CCR 11 SP PC 13 0 ACCUMULATOR INDEX REGISTER PROGRAM COUNTER STACK POINTER CONDITION CODE REGISTER 0000 0 INDEX REGISTER PCL ACCUMULATOR CONDITION CODE PCH 111

70 STACK

I N T E R R U P T DECREASING UNSTACK R E T U R N INCREASING NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. MEMORY ADDRESSES MEMORY ADDRESSES REGISTER Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Central Processor Unit (CPU) Accumulator MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Central Processor Unit (CPU) 53 NON-DISCLOSURE AGREEMENT REQUIRED

3.4 Accumulator

The accumulator (A) is a general-purpose, 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.

3.5 Index Register

The index register (X) is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area.

3.6 Condition Code Register

The condition code register (CCR) is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable or disable interrupts. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared. A X CCR HIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Central Processor Unit (CPU) General Release Specification MC68HC(7)05L5 — Rev. 2.0

54 Central Processor Unit (CPU) MOTOROLA

Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. This bit is affected also during bit test and branch instructions and during shifts and rotates.

3.7 Stack Pointer

The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the eight most significant bits are permanently set to 00000011. These eight 0 bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 13 7 0

00000011 S P

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Central Processor Unit (CPU) Program Counter MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Central Processor Unit (CPU) 55 NON-DISCLOSURE AGREEMENT REQUIRED

3.8 Program Counter

The program counter (PC) is a 14-bit register that contains the address of the next byte to be fetched.

3.9 Arithmetic Logic Unit

The arithmetic logic unit (ALU) performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal processor cycles to complete this chain of operations. 13 0 PC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Central Processor Unit (CPU) General Release Specification MC68HC(7)05L5 — Rev. 2.0

56 Central Processor Unit (CPU) MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Resets and Interrupts 57 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 4. Resets and Interrupts

4.1 Contents

4.2 Introduction

In user operating modes, the reset/interrupt vectors are located at the top of the address space ($3FF0–$3FFF). In self-check mode, the reset/interrupt vectors are located at $3FE0–$3FEF in the internal self- check ROM. Descriptions in this section assume a user operating mode is in use.Table 4-1 shows the address assignments for the vectors. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Resets and Interrupts General Release Specification MC68HC(7)05L5 — Rev. 2.0

58 Resets and Interrupts MOTOROLA

Upon reset, the I bit in the condition code register is set and interrupts are disabled (masked). When an interrupt occurs, the I bit is set automatically by hardware after stacking the condition code register (CCR). All interrupts in the MC68HC05L5 follow a fixed hardware priority circuit to resolve simultaneous requests. Each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit automatic hardware response. In addition, the I bit in the CCR acts as a class inhibit mask to inhibit all sources in the I-bit class.RESET and software interrupt (SWI) are not masked by the I bit in the CCR. SWI is an instruction rather than a prioritized asynchronous interrupt source. In a sense, it is lower in priority than any source because once any interrupt sequence has begun, SWI cannot override it. In another sense, it is higher in priority than any hardware sources, except reset, because once the SWI opcode is fetched, no other sources can be honored until after the first instruction in the SWI service routine has been executed. SWI causes the I mask bit in the CCR to be set. Table 4-1. Interrupt Vector Assignments Vector Address Interrupt Source Masked by Local Mask Priority (1 = Highest) 3FF0–3FF1 Timebase I bit TBIE 7 3FF2–3FF3 SSPI I bit SPIE 6 3FF4–3FF5 Timer 2 TI2I OC2I I bit I bit TI2IE OC2IE 3FF6–3FF7 Timer 1 ICI OC1I TOI I bit I bit I bit ICIE OC1IE TOIE 3FF8–3FF9 KWI I bit KWIE 3 3FFA–3FFB IRQ IRQ1 IRQ2 I bit I bit IRQ1E IRQ2E 3FFC–3FFD SWI None None Same level as an instruction 3FFE–3FFF Reset COP RESET pin Power-on None None None COPE None None Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Resets and Interrupts 59 NON-DISCLOSURE AGREEMENT REQUIRED

4.3 Interrupts

There are six hardware interrupt sources in the MC68HC05L5:

• IRQ1 andIRQ2
• Key wakeup interrupt (KWI)
• Timer 1 (TOI, ICI, and OC1I)
• Timer 2 (TI2I and OC2I)
• Serial transfer complete interrupt (SSPI)
• Timebase interrupt (TBI)

4.3.1 IRQ1 and IRQ2

Two external interrupt request inputs,IRQ1 andIRQ2, share the same vector address at $3FFA and $3FFB. Bits IRQ1S and IRQ2S in interrupt control register (INTCR) control whetherIRQ1 andIRQ2, respectively, respond only to the falling edge or falling edge and low level to trigger an interrupt. TheIRQ1 andIRQ2 are enabled by IRQ1E and IRQ2E bits and IRQ1F and IRQ2F bits are provided as an indicator in the interrupt status register (INTSR). Since the IRQ1(2)F can be set by either the pins or the data latches of PC7(6), be sure to clear the flags by software before setting the IRQ1(2)E bit. The IRQ1 and theIRQ2 pins are shared with port C bit 7 and bit 6, respectively, and IRQx pin states can be determined by reading port C pins. The BIL and BIH instructions apply only to theIRQ1 input.

4.3.2 Key Wakeup Interrupt (KWI)

Eight key wakeup inputs (KWI0– KWI7) share pins with port B. Each key wakeup input is enabled by the corresponding bit in the KWIEN register which resides in the option map, andKWI is enabled by the KWIE bit in the INTCR. When a falling edge is detected at one of the enabled key wakeup inputs, the KWIF bit in the INTSR is set andKWI is generated if KWIE = 1. Each input has a latch which responds only to the falling edge at the pin, and all input latches are cleared at the same time by clearing the KWIF bit. SeeFigure 4-6. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Resets and Interrupts General Release Specification MC68HC(7)05L5 — Rev. 2.0

60 Resets and Interrupts MOTOROLA

4.3.3 IRQ (KWI) Software Consideration

IRQ and KWI interrupts have a timing delay in a case described in Figure 4-2. This section shows programming for proper interrupts with IRQ or KWI. Figure 4-1 shows an example of timer 1 interrupt. In this case, the interrupt by TOF occurs as soon as the TOIE (timer 1 overflow interrupt enable) bit is set. Figure 4-1. Timer 1 Interrupt Figure 4-2 shows an example ofIRQ1 interrupt. In this case, the interrupt occursafter execution the instruction following the instruction which sets IRQ1E bit. The similar action occurs againstIRQ2 andKWI interrupts. Figure 4-2. IRQ Timing Delay This problem can be solved by using a software patch likeFigure 4-3.A similar procedure could be used forIRQ2 orKWI. Figure 4-3. Software Patch forIRQ1 CLI BSET TOIE, TCR LDA #$55 TOF INTERRUPT PENDING INTERRUPT OCCURS BEFORE THIS INSTRUCTION CLI BSET IRQ1E, INTCR LDA #$55 IRQ1 INTERRUPT PENDING INTERRUPT OCCURS AFTER THIS INSTRUCTION CLI BSET IRQ1E, INTCR NOP LDA #$55 IRQ1 INTERRUPT PENDING INTERRUPT OCCURS AFTER THIS INSTRUCTION Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Resets and Interrupts 61 NON-DISCLOSURE AGREEMENT REQUIRED Figure 4-4. Interrupt Flowchart INTERNAL INTERRUPT (1) IRQ EXTERNAL INTERRUPT LOAD PC FROM SWI: $3FFC–$3FFD IRQx: $3FFA–$3FFB KWI: $3FF8–$3FF9 TIMER 1: $3FF6–$3FF7 TIMER 2: $3FF4–$3FF5 SSPI: $3FF2–$3FF3 TBI: $3FF0–$3FF1 SET I BIT IN CC REGISTER STACK PC, X, A, CCR CLEAR IRQ REQUEST LATCH FETCH NEXT INSTRUCTION EXECUTE INSTRUCTION N N Y Y Y N I BIT IN CCR SET ? SWI INSTRUCTION N Y RTI INSTRUCTION N Y RESTORE REGISTERS FROM STACK: CCR, A, X, PC Note 1.KWI, timer 1, timer 2, SSPI, and TBI FROM RESET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Resets and Interrupts General Release Specification MC68HC(7)05L5 — Rev. 2.0

62 Resets and Interrupts MOTOROLA

Figure 4-5.IRQ1 and IRQ2 Block Diagram D C H SEL IRQ1S Q IRQ1F READ INSTRUCTION FOR BIH/BIL D C H SEL IRQ2S Q IRQ2F READ INSTRUCTION DATA BUS DATA BUS RESET/POR IRQ1E IRQ2E WRITE 1 TO RIRQ2 RESET/POR WRITE 1 TO RIRQ1 INT IRQ1 (PC7) Q R S R Q S R R IRQ2 (PC6) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Resets and Interrupts 63 NON-DISCLOSURE AGREEMENT REQUIRED Figure 4-6. Key Wakeup Interrupt (KWI) KWIE1 D C QH READ KWIF KWIE0 Q KWIF D C QH D C QH KWIE7 RESET/POR KWI DATA BUS KWI2 TO KWI6 WRITE 1 TO RKWIF KWIE KWI0 (PB0) KWI1 (PB1) KWI7 (PB7) R R R R S Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Resets and Interrupts General Release Specification MC68HC(7)05L5 — Rev. 2.0

64 Resets and Interrupts MOTOROLA

4.3.4 Timer 1 Interrupt

Three timer 1 interrupts (TOI, ICI, and OC1I) share the same interrupt vector at $3FF6 and $3FF7. See9.3 Timer 1.

4.3.5 Timer 2 Interrupt

Two timer 2 interrupts (TI2I and OC2I) share the same interrupt vector at $3FF4 and $3FF5. See9.4.1 Timer Control Register 2.

4.3.6 SSPI Interrupt

The SSPI transfer complete interrupt uses the vector at $3FF2 and $3FF3. SeeSection 8. Simple Serial Peripheral Interface (SSPI).

4.3.7 Timebase Interrupt

The timebase interrupt uses the vector at $3FF0 and $3FF1. See7.6 Timebase .

4.4 Interrupt Control Register

Address: $0008 Bit 7 654321 Bit 0 Read: IRQ1E IRQ2E 0 KWIE IRQ1S IRQ2S 0 0 Write: Reset: 00000000 Figure 4-7. Interrupt Control Register (INTCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Interrupt Control Register MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Resets and Interrupts 65 NON-DISCLOSURE AGREEMENT REQUIRED IRQ1E — IRQ1 Interrupt Enable The IRQ1E bit enables IRQ1 interrupt when IRQ1F is set. This bit is cleared on reset. 0 = IRQ1 interrupt disabled 1 = IRQ1 interrupt enabled IRQ2E — IRQ2 Interrupt Enable The IRQ2E bit enables IRQ2 interrupt when IRQ2F is set. This bit is cleared on reset. 0 = IRQ2 interrupt disabled 1 = IRQ2 interrupt enabled Bit 5 — Reserved This bit is not used and is always read as logic 0. KWIE — Key Wakeup Interrupt (KWI) Enable The KWIE bit enables key wakeup interrupt when KWIF is set. This bit is cleared on reset. 0 = KWI disabled 1 = KWI enabled IRQ1S — IRQ1 Select Edge Sensitive Only 0 = IRQ1 configured for low level and negative edge sensitive 1 = IRQ1 configured to respond only to negative edges IRQ2S — IRQ2 Select Edge Sensitive Only 0 = IRQ2 configured for low level and negative edge sensitive 1 = IRQ2 configured to respond only to negative edges Bits 1 and 0 — Reserved These bits are not used and always read as logic 0. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Resets and Interrupts General Release Specification MC68HC(7)05L5 — Rev. 2.0

66 Resets and Interrupts MOTOROLA

4.5 Interrupt Status Register

IRQ1F — IRQ1 Interrupt Flag When IRQ1S = 0, the falling edge or low level at theIRQ1 pin sets IRQ1F. When IRQ1S = 1, only the falling edge sets the IRQ1F bit. If the IRQ1E bit and this bit are set, an interrupt is generated. This read- only bit is cleared by writing a logic 1 to the RIRQ1 bit. Reset clears this bit. IRQ2F — IRQ2 Interrupt Flag When IRQ2S = 0, the falling edge or low level at theIRQ2 pin sets IRQ2F. When IRQ2S = 1, only the falling edge sets the IRQ2F bit. If the IRQ2E bit and this bit are set, an interrupt is generated. This read- only bit is cleared by writing a logic 1 to the RIRQ2 bit. Reset clears this bit. Bit 5 — Reserved This bit is not used and is always read as logic 0. KWIF — Key Wakeup Interrupt Flag When the KWIEx bit in the KWIEN register is set, the falling edge at the KWIx pin sets the KWIF bit. If the KWIE bit and this bit are set, an interrupt is generated. This read-only bit is cleared by writing a logic 1 to the RKWIF bit. Reset clears this bit. Address: $0009 Bit 7 654321 Bit 0 Read: IRQ1F IRQ2F 0 KWIF 0 0 Write: RIRQ1 RIRQ2 RKWIF Reset: 00000000 = Unimplemented Figure 4-8. Interrupt Status Register (INTSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Resets and Interrupts 67 NON-DISCLOSURE AGREEMENT REQUIRED RIRQ1 — Reset IRQ1 Flag The RIRQ1 bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the IRQ1F bit and writing logic 0 to this bit has no effect. RIRQ2 — Reset IRQ2 Flag The RIRQ2 bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the IRQ2F bit and writing a logic 0 to this bit has no effect. Bit 1 — Reserved This bit is not used and is always read as logic 0. RKWIF — Reset KWI Flag The RKWIF bit is a write-only bit and is always read as logic 0. Writing a logic 1 to this bit clears the KWIF bit and writing a logic 0 to this bit has no effect. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Resets and Interrupts General Release Specification MC68HC(7)05L5 — Rev. 2.0

68 Resets and Interrupts MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Low-Power Modes 69 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 5. Low-Power Modes

5.1 Contents

5.2 Introduction

The MCU has two power-saving modes, stop and wait. Flowcharts of these modes are shown inFigure 5-2.

5.3 Stop Mode

The STOP instruction places the MCU in its lowest-power mode. In stop mode, the internal main oscillator OSC is turned off, halting all internal processing, including timer operations (timer 1, timer 2, and computer operating properly (COP) watchdog timer. Suboscillator XOSC does not stop oscillating. Therefore, if XOSC is used as the clock source for the COP watchdog timer, COP is still functional in stop mode. SeeSection 7. Oscillators/Clock Distributions. During stop mode, the timer prescaler is cleared. The I bit in the condition code register (CCR) is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by RESET or an interrupt fromIRQ1,IRQ2,KWI, SSPI (slave mode only), or TBI. SeeSection 7. Oscillators/Clock Distributions. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes General Release Specification MC68HC(7)05L5 — Rev. 2.0

70 Low-Power Modes MOTOROLA

5.4 Wait Mode

The WAIT instruction places the MCU in a low-power mode, but wait mode consumes more power than stop mode. All CPU action is suspended, but on-chip peripherals and oscillators remain active. Any interrupt or reset (including a COP reset) will cause the MCU to exit wait mode. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timers may be enabled to allow a periodic exit from wait mode. Wait mode must be exited and the COP must be reset to prevent a COP timeout. The reduction of power in wait mode depends on how many of the on- chip peripheral's clocks can be shut down. Therefore, the amount of power that will be consumed is dependent on the application, and it would be prohibitive to test all parts for all variations. For these reasons, the values given inSection 12. Electrical Specificationsreflect typical application conditions after initial characterization of silicon. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Low-Power Modes 71 NON-DISCLOSURE AGREEMENT REQUIRED Figure 5-1. Clock State and STOP Recovery/Power-On Reset Delay Diagrams RESET INT STATE C CPU: RUN PH2: X1/64 X1: ON X2: ON STATE B CPU: RUN PH2: X1/4 X1: ON X2: ON STATE D CPU: RUN PH2: X2/2 X1: ON X2: ON STATE A CPU: RUN PH2: X1/2 X1: ON X2: ON STATE E CPU: RUN PH2: X2/2 X1: OFF X2: ON X1EN = 1X1EN = 0 STATE A STATE B STATE C STOP STATE D STATE E DELAY POWER-ON INT INT STOP STOP RESET INT Notes: PH2 is at same frequency as internal processor clock E. X1 = OSC X2 = XOSC X1EN = FOSCE Low Power High Speed RESET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes General Release Specification MC68HC(7)05L5 — Rev. 2.0

72 Low-Power Modes MOTOROLA

Figure 5-2. Stop/Wait Flowcharts 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE RESET? OSCILLATOR ACTIVE TIMER CLOCK ACTIVE PROCESSOR CLOCKS STOPPED CLEAR I BIT RESTART PROCESSOR CLOCK STOP OSCILLATOR OSC AND ALL CLOCKS EXCEPT XOSC CLEAR I BIT Y Y YY N N N EXTERNAL INTERRUPT IRQ? Y N KWI INTERRUPT? Y N TIMER 2 INTERRUPT? Y N SSPI INTERRUPT? Y N TIMEBASE INTERRUPT? EXTERNAL INTERRUPT IRQ? RESET? Y N TIMER 1 INTERRUPT? KWI INTERRUPT N N N Y YTIMEBASE INTERRUPT‡ SSPI INTERRUPT† N Y Notes: † Slave Mode Only ‡ When TBCLK = 0 STOP WAIT 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE IF FOSC = 1 TURN ON OSCILLATOR OSC WAIT FOR TIME Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 73 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 6. Parallel Input/Output (I/O)

6.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

74 Parallel Input/Output (I/O) MOTOROLA

6.2 Introduction

The MCU has five parallel ports:

• Port A has eight input/output (I/O) pins.
• Port B has eight input-only pins.
• Port C has six I/O pins and tow input-only pins.
• Port D has seven output-only pins.
• Port E has eight output-only pins. Most of these 39 I/O pins serve multiple purposes, depending on the configuration of the MCU system. The configuration is in turn controlled by hardware mode selection as well as internal control registers. Figure 6-1. Port I/O Circuitry for One Bit DATA DIRECTION REGISTER BIT LATCHED DATA BIT I/O PIN INPUT REG BIT INPUT I/O OUTPUT INTERNAL HC05 CONNECTIONS OUTPUT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Input/Output (I/O) Port A MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 75 NON-DISCLOSURE AGREEMENT REQUIRED

6.3 Port A

Port A is an 8-bit, bidirectional, general-purpose port. The data direction of a port A pin is determined by its corresponding DDRA bit. When a port A pin is programmed as an output by the corresponding DDRA bit, data in the PORTA data register becomes output data to the pin. This data is returned when the PORTA register is read. Open drain or CMOS outputs are selected by AWOMH and AWOML bits in the WOM1 register. If the AWOMH bit is set, the P-channel drivers of bits 7–4 output buffers are disabled (open drain). If the AWOML bit is set, the P-channel drivers of bits 3–0 output buffers are disabled (open drain). When a bit is programmed as input by the corresponding DDRA bit, the pin level is read by the CPU. Port A has optional pullup resistors. When the RAH bit or RAL bit in the RCR1 is set, pullup resistors are attached to the upper four bits or lower four bits of port A pins, respectively. When a pin outputs a low level, the pullup resistor is disconnected regardless of the RAH or RAL bit state. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

76 Parallel Input/Output (I/O) MOTOROLA

6.3.1 Port A Data Register

Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output Write Anytime; data stored in an internal latch; drives pin only if DDR set for output Reset Becomes high-impedance inputs Address: $0000 Bit 7 654321 Bit 0 Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Write: Reset: Unaffected by reset Figure 6-2. Port A Data Register (PORTA) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Input/Output (I/O) Port A MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 77 NON-DISCLOSURE AGREEMENT REQUIRED

6.3.2 Port A Data Direction Register

Anytime when OPTM = 1 Write Anytime when OPTM = 1 Reset Cleared to $00; all general-purpose I/O configured for input DDRA x — Port A Data Direction Register Bitx 0 = Configure I/O pin PAx to input 1 = Configure I/O pin PAx to output Address: Option Map — $0000 Bit 7 654321 Bit 0 Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: 00000000 Figure 6-3. Port A Data Direction Register (DDRA) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

78 Parallel Input/Output (I/O) MOTOROLA

6.4 Port B

Port B pins serve two basic functions:KWI input pins and general- purpose input pins. Each KWI input is enabled or disabled by the corresponding KWIEx bit in the KWIEN register, and the usage of theKWI input does not affect the general-purpose input function. Port B pin states may be read any time regardless of the configurations. Since there is no output drive logic associated with port B, there is no DDRB register and the write to the PORTB register has no meaning. Port B has optional pullup resistors. When the RBH or RBL bit in the RCR1 is set, pullup resistors are attached to the upper four bits or lower four bits of port A pins, respectively. Read Anytime; returns pin level Write Has no meaning or effect Reset Unaffected; always an input port Address: $0001 Bit 7 654321 Bit 0 Read: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Write: Reset: Unaffected by reset Figure 6-4. Port B Data Register (PORTB) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Input/Output (I/O) Port C MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 79 NON-DISCLOSURE AGREEMENT REQUIRED

6.5 Port C

Port C pins share functions with several on-chip peripherals. A pin function is controlled by the enable bit of each associated peripheral. Bit 7 and bit 6 of port C are input-only pins and IRQ input pins. Since IRQ1F or IRQ2F can be set by either the pins or the data latches, when using IRQs, be sure to clear the flags by software before enabling the IRQ1E or IRQ2E bits. The PC5 pin is a general-purpose I/O pin and the direction of the pin is determined by the DDRC5 bit in the data direction register C (DDRC). When the event output (EVO) is enabled, the PC5 is configured as an event output pin and the DDRC5 bit has meaning only for the read of PC5 bit in the PORTC register; if the DDRC5 is set, the PC5 data latch is read by the CPU. Otherwise, PC5 pin level (EVO state) is read. When EVO is disabled, the DDRC5 bit decides the idling state of EVO (if DDRC5 = 1). The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These bits are not affected by the usage of timer input functions and the directions of pins are always controlled by the DDRC4 and DDRC3 bits. Also, the DDRC4 and DDRC3 bits determine whether the pin states or data latch states should be read by the CPU. NOTE: Since the TCAP pin is shared with the PC3 I/O pin, changing the state of the PC3 DDR or data register can cause an unwanted TCAP interrupt. This can be handled by clearing the ICIE bit before changing the configuration of PC3 and clearing any pending interrupts before enabling ICIE. Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be cleared whenever EVI is used. EVI should not be used when DDRC4 is high. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

80 Parallel Input/Output (I/O) MOTOROLA

The PC2–PC0 pins are shared with the simple serial peripheral interface (SSPI). When the SSPI is not used (SPE = 0), DDRC2–DDRC0 bits control the direction of the pins, and when the SSPI is enabled, the pins are configured as serial clock output or input (SCK), serial data output (SDO), and serial data input (SDI). The direction of the SCK depends on the MSTR bit in the SPCR. When PORTC is read, the value read will be determined by the data direction register. When the port is configured for input (DDRC2, DDRC1, or DDRC0 equal to logic 0), the pin state is read. When the port is configured for output (DDRC2, DDRC1, or DDRC0 equal to logic 0), the output data latch is read. Port C has optional pullup resistors. When the RCx bit in the RCR2 is set, pullup resistors are attached to the PCx pin. When a pin outputs a low level, the pullup resistor is disconnected regardless of an RCR2 register bit being set Bits 5–0 have open drain or CMOS output options, which are controlled by the corresponding WOM2 register bits. These open drain or CMOS output options may be selected for either the general-purpose output ports or the peripheral outputs (EVO, SCK, and SDO). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Input/Output (I/O) Port C MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 81 NON-DISCLOSURE AGREEMENT REQUIRED

6.5.1 Port C Data Register

Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output, PC7 and PC6 are input-only pins Write Anytime; data stored in an internal latch; drives pin only if DDR set for output; writes do not change pin state; when pin configured for SDO, SCK, and EVO peripheral output, bits 7 and 6 are read-only bits and write has no effect Reset Becomes high-impedance input Address: $0002 Bit 7 654321 Bit 0 Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Write: Reset: Unaffected by Reset Figure 6-5. Port C Data Register (PORTC) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

82 Parallel Input/Output (I/O) MOTOROLA

6.5.2 Port C Data Direction Register

Anytime when OPTM = 1 Write Anytime when OPTM = 1; bits7 and 6 are read-only and write has no effect Reset Cleared to $00; all general-purpose I/O configured for input Bits 7 and 6 — Not used Always read logic 0 DDRC5–DDRC0 — Port C Data Direction Register Bitx The timer and SSPI force the I/O state to be an output for each port C line associated with an enabled output function such as SDO and EVO. For these cases, the data direction bits will not change. 0 = Configure I/O pin PCx to input 1 = Configure I/O pin PCx to output Address: Option Map — $0002 Bit 7 654321 Bit 0 Read: 0 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write: Reset: 00000000 Figure 6-6. Port C Data Direction Register (DDRC) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Input/Output (I/O) Port D MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 83 NON-DISCLOSURE AGREEMENT REQUIRED

6.6 Port D

Port D pins serve one of two basic functions, depending on the MCU mode selected:

• LCD frontplane and backplane driver outputs
• General-purpose output pins Since port D is an output-only port, there is no DDRD register. On reset, all port D outputs are disconnected from the pins and the port D data latches are set to a logic 1. By writing a 1 the PDH bit in the LCD control register (LCDCR), LCD frontplanes drivers (FP35–FP38) are disabled and the upper four bits of port D output are connected to the pins. The pin connections of the lower three bits of port D depend on the LCD duty selection by the DUTY1 and DUTY0 bits in the LCDCR. When the LCD duty is not 1/4, the unused backplane driver(s) is (are) replaced by the port D output pin(s) automatically. If DWOMH bit or DWOML bit in the WOM1 register is set, the P-channel drivers of output buffers at the upper four bits or lower three bits, respectively, are disabled (open-drain mode). These open-drain controls do not apply to the pins which are configured as frontplane or backplane driver outputs. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

84 Parallel Input/Output (I/O) MOTOROLA

Anytime; returns output data latch; bit 0 is always read logic 1 Write Anytime; writes do not change pin state when configured for LCD driver output Reset All bits set to logic 1 and output ports disconnected from the pins; LCD is enabled on reset Address: $0003 Bit 7 654321 Bit 0 Read: PD7 PD6 PD5 PD4 PD3 PD2 PD1 1 Write: Reset: 11111111 Figure 6-7. Port D Data Register (PORTD) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Parallel Input/Output (I/O) Port E MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Parallel Input/Output (I/O) 85 NON-DISCLOSURE AGREEMENT REQUIRED

6.7 Port E

Port E pins serve one of two basic functions, depending on the MCU mode selected:

• LCD frontplane driver outputs
• General-purpose output pins Since port E is an output-only port, there is no DDRE register. On reset, all port E outputs are disconnected from the pins and the port E data latches are set to a logic 1. The upper or lower four bits of port E output are connected to the pins instead of the LCD frontplane drivers by writing 1 to the PEH or PEL bit, respectively, in the LCD control register(LCDCR). If EWOMH bit or EWOML bit in the WOM1 register is set, the P-channel driver of output buffers at the upper or lower four bits, respectively, are disabled (open-drain mode). These open-drain controls do not apply to the pins which are configured as frontplane driver outputs. Read Anytime; returns output data latch Write Anytime; writes do not change pin state when configured for LCD driver output Reset All bits set to logic 1 and output ports disconnected from the pins; LCD is enabled on reset Address: $0004 Bit 7 654321 Bit 0 Read: PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Write: Reset: 11111111 Figure 6-8. Port E Data Register (PORTE) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output (I/O) General Release Specification MC68HC(7)05L5 — Rev. 2.0

86 Parallel Input/Output (I/O) MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 87 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 7. Oscillators/Clock Distributions

7.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

88 Oscillators/Clock Distributions MOTOROLA

7.2 Introduction

The two oscillator blocks are OSC and XOSC. Several combinations of the clock distributions are allowed for the modules in the MC68HC05L5. Refer toFigure 7-1. Figure 7-1. Clock Signal Distribution

7.3 OSC Clock Divider and POR Counter

The OSC clock is divided by a 7-bit counter which is used for the system clock, timebase, and power-on reset (POR) counter. Clocks divided by 2, 4, and 64 are available for the system clock selections and a clock divided by 128 is provided for the timebase and POR counter. The POR counter is a 6-bit clock counter that is driven by the OSC divided by 128. The overflow of this counter is used for setting FTUP bit, releasing the POR, and resuming operation from stop mode. XOSC1 XOSC2 STOP OSC1 OSC2 SYS1 SYS0 SEL 1/2 OSC XOSC CLK CTRL POR 6-BIT TIMEBASE TIMER2 TIMER1 SSPI CPU LCD DRIVER AND PORTS WAIT EXCLK XCLK FOSCE/ PWRON SYSTEM CLOCK FTUP OSC DIVIDER 7-BIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions System Clock Control MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 89 NON-DISCLOSURE AGREEMENT REQUIRED The 7-bit divider and POR counter are initialized to $0078 by two conditions:

• Power-on detection
• When FOSCE bit is cleared

7.4 System Clock Control

The system clock is provided for all internal modules except timebase. Both OSC and XOSC are available as the system clock source. The divide ratio is selected by the SYS1 and SYS0 bits in the MISC register. (See Table 7-1.) By default, OSC divided by 64 is selected on reset. NOTE: Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when XOSC clock is not available. The XOSC clock is available when STUP flag is set. Do not switch the system clock to OSC (SYS1 and SYS0 = 00, 01, or 10) when OSC clock is not available. The OSC clock is available when FTUP flag is set. Table 7-1. System Bus Clock Frequency Selection SYS1 SYS0 Divide Ratio CPU Bus Frequency (Hz) OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k 0 0 OSC ÷2 2.0 M 2.0972 M — 0 1 OSC ÷4 1.0 M 1.0486 M — 1 0 OSC ÷64 62.5 k 65.536 k — 1 1 XOSC ÷2 — — 16.384 k Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

90 Oscillators/Clock Distributions MOTOROLA

7.5 OSC and XOSC

The secondary oscillator (XOSC) runs continuously after power up. The main oscillator (OSC) can be stopped to conserve power via the STOP instruction or the FOSCE bit in the MISC register. The effects of restarting the OSC will vary depending on the current state of the MCU, including SYS0, SYS1, and FOSCE.

7.5.1 OSC on Line

If the system clock is OSC, FOSCE should remain logic 1. Executing the STOP instruction in this condition will halt OSC, put the MCU into a low- power mode and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ or reset re-starts the oscillator. When the POR counter overflows, internal reset is released and execution can begin. The stabilization time will vary between 8064 and 8192 counts. NOTE: Exiting STOP with external reset will always return the MCU to the state as defined by the default register definitions, for example, SYS0:SYS1 = 1:0, FOSCE = 1. Figure 7-2. OSC1, OSC2, XOSC1, and XOSC2 Mask Options RfRf R d XOSC1 XOSC2 XOSC OSC1 OSC2 OSC MASK OPTION MASK OPTION ON CHIP OFF CHIP Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions OSC and XOSC MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 91 NON-DISCLOSURE AGREEMENT REQUIRED

7.5.2 XOSC on Line

If XOSC is the system clock (SYS:SYS1 = 1:1), OSC can be stopped either by the STOP instruction or by clearing the FOSCE bit. The suboscillator (XOSC) never stops except during power down. This clock also may be used as the clock source of the system clock and timebase. STUP bit indicates that the XOSC clock is available. OSC and XOSC pins have options for feedback and damping resistor implementations. These options are set through mask option and may be read through the MOSR register. NOTE: When XOSC is not used, the XOSC1 input pin should be connected to theRESET pin. Figure 7-3. Unused XOSC1 Pin

7.5.2.1 XOSC with FOSCE = 1

If the system clock is XOSC and FOSCE = 1, executing the STOP instruction will halt OSC, put the MCU into a low-power mode and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ re-starts the oscillator; however, execution begins immediately using XOSC. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will vary between 8064 and 8192 counts. XOSC1 XOSC2 XOSCRESET LOGIC ON CHIP OFF CHIP NO CONNECT RESET FROM EXTERNAL RESET CIRCUIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

92 Oscillators/Clock Distributions MOTOROLA

7.5.2.2 XOSC with FOSCE = 0

If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider and 6-bit POR counter to $0078. Execution will continue with XOSC and when FOSCE is set again, OSC will re-start. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will be 8072 counts.

7.5.2.3 XOSC with FOSCE = 0 and STOP

If XOSC is the system clock and FOSCE is cleared, further power reduction can be achieved by executing the STOP instruction. In this case, OSC is stopped, the 7-bit divider and 6-bit POR counter are preset to $0078 (since FOSCE = 0) and execution is halted. Exiting STOP with external IRQ does not re-start the OSC; however, execution begins immediately using XOSC. OSC may be re-started by setting FOSCE. When the POR counter overflows, FTUP will be set, signaling that OSC is stable and can be used as the system clock. The stabilization time will be 8072 counts.

7.5.2.4 Stop Mode and Wait Mode

During stop mode, the main oscillator (OSC) is shut down and the clock path from the second oscillator (XOSC) is disconnected. All modules except timebase are halted. Entering stop mode clears the FTUP flag in the MISC register and initializes the POR counter. Stop mode is exited by RESET, IRQ1,IRQ2,KWI, SSPI (slave mode), or timebase interrupt. If OSC is selected as the system clock source during stop mode, CPU resumes after the overflow of the POR counter and this overflow also sets the FTUP status flag. If XOSC is selected as the system clock source during stop mode, no stop recovery time is required for exiting stop mode because XOSC never stops. Re-start of the main oscillator depends on the FOSCE bit. During wait mode, only the CPU clocks are halted and the peripheral modules are not affected. Wait mode is exited byRESET and any interrupts. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions Timebase MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 93 NON-DISCLOSURE AGREEMENT REQUIRED

7.6 Timebase

Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit in the TBCR1 register selects the clock source. This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 8072 clocks, the STUP bit in the MISC register is set. The divided clocks from the timebase are used for LCDCLK, STUP, TBI, and COP. (SeeFigure 7-4). Table 7-2. Recovery Time Requirements Before Reset or Interrupt Power-On Reset External Reset Exit Stop Mode by InterruptCPU Clock Source Stop FOSCE OSC (OSC on) Out 1 — No wait — OSC (OSC off) Out In In(1) 1. This case never occurs. 0(2) 0(1) 2. This case has no meaning for the applications. Wait Wait Wait Wait Wait XOSC (OSC on) Out 1 — No wait — XOSC (OSC off) Out In In Wait Wait Wait No wait No wait Notes: Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

94 Oscillators/Clock Distributions MOTOROLA

Figure 7-4. Timebase Clock Divider

7.6.1 LCDCLK

The clocks divided by 64 and 128 are used as LCD clocks at the LCD driver module, and clocks are selected by the LCLK bit in the TBCR1.

7.6.2 STUP

Timebase divider is initialized to $0078 by the power-on detection and when the count reaches 8072, the STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared until power down. SEL 7-BIT DIVIDER SEL SEL DIVIDE BY 4 TBIF TBCLK LCLK TBIE 7-BIT DIVIDER TBR1 TBR0 COP ENABLE COP CLEAR COP RESET TBI LCD CLOCK XCLK OSC/2 7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions Timebase MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 95 NON-DISCLOSURE AGREEMENT REQUIRED

7.6.3 TBI

Timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz crystal at XOSC pins. The timebase interrupt flag (TBIF) is set every period and interrupt is requested if the enable bit (TBIE) is set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the TBR1 and TBR0 bits in the TBCR2 register. (SeeTable 7-3.) Table 7-3. Timebase Interrupt Frequency TBCR2 Divide Ratio Frequency (Hz) TBR1 TBR0 OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k 0 0 TBCLK ÷128 244 256 256 0 1 TBCLK ÷4096 7.63 8.00 8.00 1 0 TBCLK ÷8192 3.81 4.00 4.00 1 1 TBCLK ÷16,384 1.91 2.00 2.00 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

96 Oscillators/Clock Distributions MOTOROLA

7.6.4 COP

The computer operating properly (COP) watchdog timer is controlled by the COPE and COPC bits in the TBCR2 register. The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI is divided by four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The COP timeout reset has the same vector address as POR and external RESET. To prevent the COP timeout, the COP divider is cleared by writing a logic 1 to the COP clear (COPC) bit. When the timebase divider is driven by the OSC clock, clock for the divider is suspended during stop mode or when FOSCE is a logic 0. This may cause COP period stretching or no COP timeout reset when processing errors occur. To avoid these problems, it is recommended that the XOSC clock be used for the COP functions. When the timebase (COP) divider is driven by the XOSC clock, the divider does not stop counting and the COPC bit must be triggered to prevent the COP timeout. Table 7-4. COP Timeout Period TBCR2 COP Period (ms) TBR1 TBR0 OSC = 4.0 MHz OSC = 4.1943 MHz XOSC = 32.768 kHz Min Max Min Max Min Max 0 1 393 524 375 500 375 500 1 0 786 1048 750 1000 750 1000 1 1 1573 2097 1500 2000 1500 2000 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions Timebase MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 97 NON-DISCLOSURE AGREEMENT REQUIRED

7.6.5 Timebase Control Register 1

Anytime; only one write is allowed on bit 7 after reset TBCLK — Timebase Clock The TBCLK bit selects the timebase clock source. This bit is cleared on reset. After reset, a write to this bit is allowed only once. 0 = XOSC clock selected 1 = OSC clock divided by 128 selected Bit 6 — Reserved This bit is not used and always reads as logic 0. LCLK — LCD Clock The LCLK bit selects the clock for the LCD driver. This bit is cleared on reset. 0 = Divide by 64 selected 1 = Divide by 128 selected Bits 4–2 — Reserved These bits are not used and always read as logic 0. T2R1 and T2R0 — Timer 2 Prescale Rate Select Bits T2R1 and T2R0 select timer 2 clock rate. See9.4 Timer 2 for more detail. Address: $0010 Bit 7 654321 Bit 0 Read: TBCLK 0 LCLK 0 0 0 T2R1 T2R0 Write: Reset: 00000000 Figure 7-5. Timebase Control Register 1 (TBCR1) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

98 Oscillators/Clock Distributions MOTOROLA

7.6.6 Timebase Control Register 2

Anytime; bits 3 and 0 are write-only bits and always read as logic 0 Write Anytime; bit 7 is a read-only bit and write has no effect; bit 1 is 1-time write bit TBIF — Timebase Interrupt Flag The TBIF bit is set every timeout interval of the timebase counter. This read-only bit is cleared by writing a logic 1 to the RTBIF bit. Reset clears the TBIF bit. The timebase interrupt period between reset and the first TBIF depends on the time elapsed during reset, since the timebase divider is not initialized on reset. TBIE — Timebase Interrupt Enable The TBIE bit enables the timebase interrupt capability. If TBIF=1a n d TBIE = 1, the timebase interrupt is generated. 0 = Timebase interrupt disabled 1 = Timebase interrupt requested when TBIF = 1 TBR1 and TBR0 — Timebase Interrupt Rate Select The TBR1 and TBR0 bits select one of four rates for the timebase interrupt period (seeTable 7-3). The TBI rate is also related to the COP timeout reset period. These bits are set to logic 1 on reset. Address: $0011 Bit 7 654321 Bit 0 Read: TBIF TBIE TBR1 TBR0 Write: RTBIF COPE COPC Reset: 00110000 = Unimplemented Figure 7-6. Timebase Control Register 2 (TBCR2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions Timebase MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 99 NON-DISCLOSURE AGREEMENT REQUIRED RTBIF — Reset Timebase Interrupt Flag The RTBIF bit is a write-only bit and is always read as logic 0. Writing logic 1 to this bit clears the TBIF bit and writing logic 0 to this bit has no effect. Bit 2 — Reserved This bit is not used and is always read as logic 0. COPE — COP Enable When the COPE bit is logic 1, the COP reset function is enabled. This bit is cleared on reset (including COP timeout reset) and write to this bit is allowed only once after reset. COPC — COP Clear Writing logic 1 to the COPC bit clears the 2-bit divider to prevent COP timeout. (The COP timeout period depends on the TBI rate.) This bit is write-only and returns to logic 0 when read. Table 7-5. Timebase Interrupt Frequency TBCR2 Divide Ratio Frequency (Hz) TBR1 TBR0 OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k 0 0 TBCLK ÷128 244 256 256 0 1 TBCLK ÷4096 7.63 8.00 8.00 1 0 TBCLK ÷8192 3.81 4.00 4.00 1 1 TBCLK ÷16,384 1.91 2.00 2.00 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

100 Oscillators/Clock Distributions MOTOROLA

7.6.7 Miscellaneous Register

FTUP — OSC Time Up Flag Power-on detection and clearing the FOSCE bit clears this read-only bit. This bit is set by the overflow of the POR counter. Reset does not affect this bit. 0 = During POR or OSC shut down 1 = OSC clock available for the system clock STUP — XOSC Time Up Flag Power-on detection clears this read-only bit. This bit is set after the timebase has counted 8072 clocks. Reset does not affect this bit. 0 = XOSC not stabilized or no signal on XOSC1 and XOSC2 pins 1 = XOSC clock available for the system clock Bits 5 and 4 — Reserved These bits are not used and always read as logic 0. SYS1 and SYS0 — System Clock Select These two bits select the system clock source. On reset, the SYS1 and SYS0 bits are initialized to 1 and 0, respectively. Address: $003E Bit 7 654321 Bit 0 Read: FTUP STUP 0 0 SYS1 SYS0 FOSCE OPTM Write: Reset: * * 001010 = Unimplemented * Unaffected by reset but initialized by power-on reset Figure 7-7. Miscellaneous Register (MISC) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Oscillators/Clock Distributions Timebase MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Oscillators/Clock Distributions 101 NON-DISCLOSURE AGREEMENT REQUIRED NOTE: Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when the XOSC clock is not available. The XOSC clock is available when the STUP flag is set. Do not switch the system clock to OSC (SYS1 and SYS 0 = 00, 01, or 10) when the OSC clock is not available. The OSC clock is available when the FTUP flag is set. FOSCE — Fast (Main) Oscillator Enable The FOSCE bit controls the main oscillator activity. This bit should not be cleared by the CPU when the main oscillator is selected as the system clock source. When this bit is cleared: 1. OSC is shut down. 2. 7-bit dividers at the OSC input and POR counter are initialized to $0078. 3. FTUP flag is cleared. When this bit is set: 1. Main oscillator starts again. 2. FTUP flag is set by the POR counter overflow (8072 clocks). OPTM — Option Map Select The OPTM bit selects one of two register maps at $0000–$000F. This bit is cleared on reset. 0 = Main register map selected 1 = Option map selected Table 7-6. System Bus Clock Frequency Selection SYS1 SYS0 Divide Ratio CPU Bus Frequency (Hz) OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k 0 0 OSC ÷2 2.0 M 2.0972 M — 0 1 OSC ÷4 1.0 M 1.0486 M — 1 0 OSC ÷64 62.5 k 65.536 k — 1 1 XOSC ÷ 2 — — 16.384 k Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Oscillators/Clock Distributions General Release Specification MC68HC(7)05L5 — Rev. 2.0

102 Oscillators/Clock Distributions MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Simple Serial Peripheral Interface (SSPI) 103 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 8. Simple Serial Peripheral Interface (SSPI)

8.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Simple Serial Peripheral Interface (SSPI) General Release Specification MC68HC(7)05L5 — Rev. 2.0

104 Simple Serial Peripheral Interface (SSPI) MOTOROLA

8.2 Introduction

The simple serial peripheral interface (SSPI) of the MC68HC05L5 is a master/slave synchronous serial communication module. SSPI uses a 3-wire protocol: data input, data output, and serial clock. In this format, the clock is not being included in the data stream and must be provided as a separate signal. When the SSPI is enabled (SPE = 1), bits 0–2 of port C become SDI (serial data in), SDO (serial data out), and SCK (serial clock) pins. The corresponding DDRC bit does not change the direction of the pin. The MSTR bit decides the SSPI operation mode. The SCK pin is configured as output in master mode and configured as input in slave mode. The DORD bit in the serial peripheral control register (SPCR) selects the data transmission order. When DORD is set, the least significant bit (LSB) of serial data is shifted out/in first. When the DORD is clear, serial data is shifted from/to the most significant bit (MSB). Master serial clock speed is selected by the SPR bit in the SPCR. An interrupt may be generated by the completion of a transfer.

8.3 Features

Features of the SSPI are:

• Full-duplex, 3-wire synchronous transfers
• Master or slave operation
• Programmable data transmission order, LSB or MSB first
• 1.05-MHz (maximum) transmission bit frequency at 2.1-MHz CPU bus frequency at 5 Vdc
• Two programmable transmission bit rates
• End-of-transmission interrupt flag
• Wakeup from stop mode (slave mode only) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Simple Serial Peripheral Interface (SSPI) Functional Descriptions MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Simple Serial Peripheral Interface (SSPI) 105 NON-DISCLOSURE AGREEMENT REQUIRED

8.4 Functional Descriptions

In master mode, the clock start logic is triggered by the CPU (detection of a CPU write to the 8-bit shift register (SPDR)). The SCK is based on the internal processor clock. This clock is also used in the 3-bit counter and 8-bit shift register. SeeFigure 8-2. When data is written to the 8-bit shift register of the master device, it is then shifted out to the SDO pin for application to the slave device. At the same time, data applied from the slave device via the SDI pin is shifted into the 8-bit shift register. After 8-bit data is shifted in/out, SCK stops and SPIF is set. If SPIE is enabled, an interrupt request is generated. The slave device in stop mode wakes up by this interrupt. Further transfers (writes to SPDR) are inhibited while SPIF is a logic 1. The master-slave basic interconnection is illustrated inFigure 8-1. Figure 8-1. SSPI Master-Slave Interconnection SCKSCK SDISDO SDOSDI SPDR HFF CLOCK GENERATOR SPDR HFF CLOCK GENERATOR MASTER DEVICE SLAVE DEVICE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Simple Serial Peripheral Interface (SSPI) General Release Specification MC68HC(7)05L5 — Rev. 2.0

106 Simple Serial Peripheral Interface (SSPI) MOTOROLA

8.5 Internal Block Descriptions

The following paragraphs describe the main blocks in the SSPI module. (See Figure 8-2). Figure 8-2. SSPI Block Diagram

8.5.1 Control

This block is an interface to the HC05 internal bus and generates a start signal when a write to the SPDR is detected in master mode. It also generates an interrupt request to the CPU.

8.5.2 SPDR

This serial peripheral data register (SPDR) is an 8-bit shift register. The DORD bit in the SPCR determines the bus connection between the internal data bus and SPDR. This register can be read and written by the CPU. CONTROL LOGIC SPSR SPCR SPDR HFF SDO CLOCK GENERATOR SCK HC05 INTERNAL BUS INTERRUPT CONTROLS AND ADDRESS BUS DATA BUS M S T R S P E S T A R T D C O L S P I F SDIDORD S P R 0000 000 00 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Simple Serial Peripheral Interface (SSPI) Signal Descriptions MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Simple Serial Peripheral Interface (SSPI) 107 NON-DISCLOSURE AGREEMENT REQUIRED

8.5.3 SPCR

Bits in the serial peripheral control register (SPCR) control SSPI functions.

8.5.4 SPSR

The serial peripheral status register (SPSR) mainly sets flags such as SPIF and DCOL.

8.5.5 CLKGEN

In master mode, this block generates SCK when the CPU writes to the data register (SPDR) and the clock rate is selected by the SPR bit in the control register. In slave mode, the external clock from the SCK pin is used instead of the master mode clock, and SPR has no affect. This clock generator includes a 3-bit clock counter. Overflow of this counter sets SPIF.

8.6 Signal Descriptions

Three basic signals — SDI, SDO, and SCK — are described in the following subsections. The relationship among SCK, SDI, and SDO is shown inFigure 8-3.

8.6.1 SSPI Data I/O (SDI and SDO)

The two serial data lines — SDI for input and SDO for output — are connected to PC0 and PC1, respectively, when SSPI is enabled (SPE = 1). At the falling edge of SCK, a serial data bit is transmitted out of the SDO pin. At the rising edge of SCK, a serial data bit on the SDI pin is sampled internally. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Simple Serial Peripheral Interface (SSPI) General Release Specification MC68HC(7)05L5 — Rev. 2.0

108 Simple Serial Peripheral Interface (SSPI) MOTOROLA

Figure 8-3. SSPI Clock-Data Timing Diagram When data is transmitted to other devices via the SDO line, the receiving data is shifted into the shift register through the SDI pin. This implies full- duplex transmission with both data-out and data-in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit, SPIF, is used to signify the completion of data transfer.

8.6.2 Serial Clock (SCK)

SCK is used for synchronization of both input and output data streams through its SDI and SDO pins. The master and slave devices are capable of exchanging a data byte during a sequence of eight clock pulses. Since the SCK is generated by MSB BIT6 BIT5 BIT3 BIT2 BIT1 LSBBIT4 SCK SDO DORD = 0 MSB BIT6 BIT5 BIT3 BIT2 BIT1 LSBBIT4SDI DORD = 0 LSB BIT1 BIT2 BIT4 BIT5 BIT6 MSBBIT3SDO DORD = 1 LSB BIT1 BIT2 BIT4 BIT5 BIT6BIT3SDI DORD = 1 DATA SAMPLE MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Simple Serial Peripheral Interface (SSPI) Registers MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Simple Serial Peripheral Interface (SSPI) 109 NON-DISCLOSURE AGREEMENT REQUIRED the master, slave data transfer is accomplished by synchronization to SCK. The master generates the SCK through a circuit driven by the internal processor clock and uses the SCK to latch incoming slave device data on the SDI pin and shift out data to the slave via the SDO pin. The SPR bit in the SPCR of the master selects the transmission clock rate. The slave device receives the SCK from the master device, and uses the SCK to latch incoming master device data on the SDI pin and shifts out data to the master via the SDO pin. The SPR bit in the SPCR of the slave has no meaning. NOTE: PC2/SCK should be at VDD level before SSPI is enabled. This can be done with an internal or external pullup resistor or by setting DDRC2 = 1 and PC2 = 1 prior to enabling the SSPI. Otherwise, the circuit will not initialize correctly.

8.7 Registers

Three registers are in the SSPI provide control, status, and data storage functions. They are:

• Serial peripheral control register, SPCR location $000A
• Serial peripheral status register, SPSR location $000B
• Serial peripheral data register, SPDR location $000C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Simple Serial Peripheral Interface (SSPI) General Release Specification MC68HC(7)05L5 — Rev. 2.0

110 Simple Serial Peripheral Interface (SSPI) MOTOROLA

8.7.1 Serial Peripheral Control Register

SPIE — SSPI Interrupt Enable If the serial peripheral interrupt enable (SPIE) bit is set, an interrupt is generated when SPIF in the SPSR is set and I bit (interrupt mask bit) in the condition code register (CCR) is clear. During stop mode, an SSPI request is accepted only in slave mode. Interrupt in master mode will be pending until stop mode is exited. STOP instruction does not change SPIF and SPIE. 0 = Disable SSPI interrupt 1 = Enable SSPI interrupt SPE — SSPI Enable When the SSPI enable (SPE) bit is set, the SSPI system is enabled and connected to the port C pins. Clearing the SPE bit initializes all control logic in the SSPI modules and disconnects the SSPI from port C pins. This bit is cleared on reset. 0 = Disable SSPI 1 = Enable SSPI Address: $000A Bit 7 654321 Bit 0 Read: SPIE SPE DORD MSTR 0 0 0 SPR Write: Reset: 00000000 Figure 8-4. Serial Peripheral Control Register (SPCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Simple Serial Peripheral Interface (SSPI) Registers MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Simple Serial Peripheral Interface (SSPI) 111 NON-DISCLOSURE AGREEMENT REQUIRED DORD — Data Transmission ORDer When this bit is set, the data in the 8-bit shift register (SPDR) is shifted in/out from the LSB. When this bit is cleared, the data in the SPDR is shifted in/out from the MSB. This bit is cleared on reset. 0 = MSB first 1 = LSB first MSTR — MaSTeR Mode Select The MSTR bit determines whether the device is in master mode or slave mode. In master mode (MSTR = 1), the SCK pin is configured as an output and the serial clock is generated by the internal clock generator when the CPU writes to the SPDR. In slave mode (MSTR = 0), the SCK pin is configured as an input and the serial clock is applied externally. This bit is cleared on reset. 0 = Slave mode 1 = Master mode Bits 3–1 — Reserved These bits are not used and are fixed to 0. SPR — SSPI Clock Rate Select This serial peripheral clock rate bit selects one of two bit rates of SCK. This bit is cleared on reset. 0 = Internal processor clock divided by 2 1 = Internal processor clock divided by 16 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Simple Serial Peripheral Interface (SSPI) General Release Specification MC68HC(7)05L5 — Rev. 2.0

112 Simple Serial Peripheral Interface (SSPI) MOTOROLA

8.7.2 Serial Peripheral Status Register

SPIF — Serial Transfer Complete Flag The serial peripheral data transfer complete flag bit notifies the user that a data transfer between the MC68HC05L5 and an external device has been completed. With the completion of the data transfer, the rising edge of the eighth pulse sets SPIF, and if SPIE is set, SSPI is generated. However, during STOP, the interrupt request is serviced only in slave mode. STOP execution never affects the SPIF flag or SPIE. When SPIF is set, the ninth clock from the clock generator or from the SCK pin is inhibited. Clearing the SPIF bit is done by a software sequence of accessing the SPSR while the SPIF bit is set followed by accessing SPDR (8-bit shift register). This also clears the DCOL bit. While SPIF is set, all writes to the SPDR are inhibited until SPSR is read by the CPU. The SPIF bit is a read-only bit and is cleared on reset. 0 = Data transfer not complete 1 = Data transfer complete DCOL — Data COLlision The data collision bit notifies the user that an attempt was made to write or read the serial peripheral data register while a data transfer was taking place with an external device. The transfer continues uninterrupted; therefore, a write will be unsuccessful, and a data read will be incorrect. Address: $000B Bit 7 654321 Bit 0 Read: SPIF DCOL 000000 Write: Reset: 00000000 = Unimplemented Figure 8-5. Serial Peripheral Status Register (SPSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Simple Serial Peripheral Interface (SSPI) Registers MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Simple Serial Peripheral Interface (SSPI) 113 NON-DISCLOSURE AGREEMENT REQUIRED A data collision only sets the DCOL bit and does not generate an SSPI interrupt. The DCOL bit indicates only the occurrence of data collision. Clearing the DCOL bit is done by a software sequence of accessing the SPSR while SPIF is set followed by accessing the SPDR. Both the SPIF and DCOL bits will be cleared by this sequence. The DCOL bit is cleared on reset. 0 = No data collision 1 = Data collision occurred Bits 5–0 — Reserved These bits are not used and are fixed to 0.

8.7.3 Serial Peripheral Data Register

A read during transmission causes DCOL to be set. Write A write during transmission causes DCOL to be set. The SPDR is used to transmit and receive data on the serial bus. In master mode, a write to this register initiates transmission/reception of a data byte. The SPIF status bit is set at the completion of data byte transmission. A write to the SPDR is inhibited while this register is shifting (a write Address: $000C Bit 7 654321 Bit 0 Read: MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 2 LSB Write: Reset: Unaffected by Reset Figure 8-6. Serial Peripheral Data Register (SPDR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Simple Serial Peripheral Interface (SSPI) General Release Specification MC68HC(7)05L5 — Rev. 2.0

114 Simple Serial Peripheral Interface (SSPI) MOTOROLA

attempt sets DCOL) or when the SPIF bit is set without reading SPSR. Data collision never affects the receiving and transmitting data in SPDR. A write or read of the SPDR after accessing the SPSR with SPIF set will clear the SPIF and DCOL bits. The ability to access the SPDR is inhibited when a transmission is taking place. It is important to read the discussion defining the DCOL and SPIF bits to understand the limits on using the SPDR. When SSPI is not used (SPE = 0), the SPDR can be used as a general- purpose data storage register.

8.8 Port Function

The SSPI shares I/O pins with PC0–PC2. When SPE is set, PC0 becomes SDI input, PC1 becomes SDO output and PC2 becomes SCK. The direction of SCK depends on the MSTR bit. Setting DDRC bits 0–2 does not change the data direction of the pin to output, but instead changes the source of data when PC0–PC2 is read. If DDRCx = 1, port C bitx data latch is read and if DDRCx = 0, PORTCx pin level is read by the CPU. When SPE is clear, SSPI is disconnected from the I/O pins and PC0–PC2 are used as general-purpose I/O pins. See6.5 Port C. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 115 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 9. Timer System

9.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

116 Timer System MOTOROLA

9.2 Introduction

The MC68HC05L5 has two timer modules: timer 1 with a 16-bit counter and timer 2 with an 8-bit counter. Timer 1 has one input pin (TCAP) and no output pin. Timer 2 has one input pin (EVI) and one output pin (EVO). Figure 9-1 illustrates the timer system of the MC68HC05L5. Figure 9-1. Timer System Block Diagram TCAP INPUT CONTROL 1 TIMER1 TIMER2 EVI INPUT CONTROL 2 PRESCALER TIMER REGISTERS OUTPUT CONTROL EVOSEL CAP CLK1 EXCLK CLK2 IEDG IM2 IL2 T2CLK O L O E OVF1 CMP1 CMP2 PH2 16-BIT COUNTER 8-BIT COUNTER Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 117 NON-DISCLOSURE AGREEMENT REQUIRED

9.3 Timer 1

Timer 1 consists of a 16-bit software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output compare interrupt. Pulse widths can vary from several microseconds to many seconds. SeeFigure 9-2. Figure 9-2. Timer 1 Block Diagram INPUT CAPTURE REGISTER CLOCK INTERNAL BUS OUTPUT HIGH BYTE LOW BYTE $16 $17 INTERNAL PROCESSOR 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER 8-BIT BUFFER HIGH BYTE LOW BYTE $1A $1B $18 $19 HIGH BYTE LOW BYTE $14 $15 OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT TIMER STATUS REGULAR $13 ICIE IEDG OLVL OUTPUT LEVEL REGULAR RESETTIMER CONTROL REGULAR $12 OUTPUT LEVEL (TCMP)INTERRUPT CIRCUIT TOIEOCIE EDGE INPUT D CLK C Q (NOT CONNECTED TO A PIN) COMPARE REGISTER (TCAP) ICF OCF TOF Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

118 Timer System MOTOROLA

Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These registers contain the high byte and low byte of that functional segment. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is accessed also. NOTE: The I bit in the condition code register (CCR) should be set while manipulating both the high byte and low byte register of a specific timer function to ensure that an interrupt does not occur.

9.3.1 Counter

The key element in the programmable timer is a 16-bit, free-running counter or counter register preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value. The double-byte, free-running counter can be read from either of two locations: $18–$19 (counter register) or $1A–$1B (counter alternate register). A read from only the least significant byte (LSB) of the free- running counter ($19, $1B) receives the count value at the time of the read. If a read of the free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total counter value. In reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be read to complete the sequence. The counter alternate register differs from the counter register in one respect: A read of the counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 119 NON-DISCLOSURE AGREEMENT REQUIRED The free-running counter is configured to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator startup delay. Because the free-running counter is 16 bits preceded by a fixed divided- by-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt also can be enabled when counter roll over occurs by setting its interrupt enable bit (TOIE).

9.3.2 Output Compare Register

The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of time has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations. The output compare register contents are compared with the contents of the free-running counter continually, and if a match is found, the corresponding output compare flag (OCF) bit is set. The output compare register values should be changed after each successful comparison to establish a new elapsed timeout. An interrupt also can accompany a successful output compare, provided the corresponding interrupt enable bit (OCIE) is set. After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) also is written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal hardware. The processor can write to either byte of the output compare register without affecting the other byte. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

120 Timer System MOTOROLA

9.3.3 Input Capture Register

Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The level transition which triggers the counter transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register. The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the timer used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free- running counter transfer since they occur on opposite edges of the internal bus clock. NOTE: Since the TCAP pin is shared with the PC3 I/O pin, changing the state of the PC3 DDR or data register can cause an unwanted TCAP interrupt. This can be handled by clearing the ICIE bit before changing the configuration of PC3 and clearing any pending interrupts before enabling ICIE. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 121 NON-DISCLOSURE AGREEMENT REQUIRED

9.3.4 Timer Control Register

The TCR is a read/write register containing five control bits. Three bits enable interrupts associated with the timer status register flags ICF, OCF, and TOF. ICIE — Input Capture Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled OC1IE — Output Compare 1 Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled TOIE — Timer Overflow Interrupt Enable 0 = Interrupt disabled 1 = Interrupt enabled IEDG — Input Edge The value of the input edge determines which level transition on the TCAP pin will trigger free-running counter transfer to the input capture register. Reset does not affect the IEDG bit. 0 = Negative edge 1 = Positive edge Bits 2–4 — Not Used Always read logic 0 OLVL — Not Used Always read logic 0 Address: $0012 Bit 7 654321 Bit 0 Read: ICIE OC1IE TOIE 0 0 0 IEDG OLVL Write: Reset: 000000U0 U = Unaffected Figure 9-3. Timer Control Register (TCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

122 Timer System MOTOROLA

9.3.5 Timer Status Register

The TSR is a read-only register containing three status flag bits. ICF — Input Capture Flag 0 = Flag cleared when TSR and input capture low register ($15) are accessed 1 = Flag set when selected polarity edge is sensed by input capture edge detector OC1F — Output Compare 1 Flag 0 = Flag cleared when TSR and output compare low register ($17) are accessed 1 = Flag set when output compare register contents match the free- running counter contents TOF — Timer Overflow Flag 0 = Flag cleared when TSR and counter low register ($19) are accessed 1 = Flag set when free-running counter transition from $FFFF to $0000 occurs Bits 0–4 — Not Used Always read logic 0 Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit. Address: $0013 Bit 7 654321 Bit 0 Read: ICF OC1F TOF 00000 Write: Reset: U U U 00000 = Unimplemented U = Unaffected Figure 9-4. Timer Status Register (TSR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 123 NON-DISCLOSURE AGREEMENT REQUIRED A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. The timer status register is read or written when TOF is set. 2. The LSB of the free-running counter is read but not for the purpose of servicing the flag. The counter alternate register at address $1A and $1B contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer overflow flag in the timer status register.

9.3.6 Timer During Wait Mode

The CPU clock halts during wait mode, but timer 1 remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode.

9.3.7 Timer During Stop Mode

In stop mode, timer 1 stops counting and holds the last count value if STOP is exited by an interrupt. IfRESET is used, the counter is forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU. When the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. IfRESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

124 Timer System MOTOROLA

9.4 Timer 2

Timer 2 is an 8-bit event counter which has one compare register, one event input pin (EVI), and one event output pin (EVO). The event counter is clocked by the external clock (EXCLK) or prescaled system clock (CLK2), selected by the T2CLK bit in the TCR2 register. The EXCLK may be EVI direct or EVI gated by CLK2, which is selected by the IM2 bit at the EVI block (see9.4.6 Timer Input 2 (EVI)). Timer 2 may be used as a modulus clock divider with EVO pin, free- running counter (when compare register is $00), or periodic interrupt timer. The timer counter 2 (TCNT2) is an 8-bit up counter with preset input. The counter is preset to $01 by a CMP2 signal from the comparator or by a CPU write to it that is done while the system clock (PH2) is low. Figure 9-5. Timer 2 Block Diagram COUNTER 2 COMPARATOR 2 REGISTER (OC2) BUFFER 2 S E L TRANSFER TRANSFER $01 $010 COUNTER WRITE CLK2 EXCLK T2CLK CMP2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 125 NON-DISCLOSURE AGREEMENT REQUIRED The CLK2 from the prescaler or the EXTCLK from the EVI block is selected as timer clock by the T2CLK bit in the TCR2 register. The CLK2 and the EXCLK are synchronized to the falling edge of system clock in the prescaler and the EVI blocks. The minimum pulse width of CLK2 is the same as the system clock, and the minimum pulse width of EXCLK (event mode) is one PH2 cycle. When the EXCLK (event mode) is selected, 50% duty is not guaranteed. The counter is incremented by the falling edge of the timer clock and the period between two falling edges is defined as one timer cycle in the following description. The compare register (OC2) is provided for comparison with the timer counter 2 (TCNT2). The OC2 data is transferred to the buffer register when the counter is preset by a CPU write or by a compare output (CMP2). This buffer register is compared with the timer counter 2 (TCNT2). The comparison between the counter and the OC2 buffer register is done when the system clock is high in each bus cycle. If the counter matches with the OC2 buffer register, the comparator latches this result during the current timer cycle. When the next timer cycle begins, the comparator outputs CMP2 signal (if the compare match is detected during previous timer cycle). This CMP2 is used in the counter preset data transfer to the buffer register, setting OC2F in the TSR2 and the EVO block. The counter preset overrides the counter increment. The OC2F bit may generate interrupt requests if the OC2IE bit in the TCR2 is set. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

126 Timer System MOTOROLA

Figure 9-6. Timer 2 Timing Diagram for f(PH2) > f(TIMCLK) N N 01COUNTER2 PH2 TIMCLK OC2 (BUFFER) CMP2 EVO COMPARE COUNT UP COUNT UP COUNT UP COMPARE O C 2=1 PRESET COUNT UP COUNT UP COUNT UP COUNTER2 PH2 TIMCLK OC2 (BUFFER) CMP2 EVO PRESET PRESET PRESET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 127 NON-DISCLOSURE AGREEMENT REQUIRED Figure 9-7. Timer 2 Timing Diagram for f(PH2) = f(TIMCLK) N-1 N 02COUNTER2 PH2 TIMCLK OC2 (BUFFER) CMP2 EVO OC2 = 1 Legend: 1. COUNT UP 2. COMPARE 3. PRESET that overrides COUNT UP N0 1 1111 2222 01COUNTER2 PH2 TIMCLK OC2 (BUFFER) CMP2 EVO 01 01 1111 2222 333 Legend: 1. COUNT UP 2. COMPARE 3. PRESET that overrides COUNT UP Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

128 Timer System MOTOROLA

9.4.1 Timer Control Register 2

TI2IE — Timer Input 2 Interrupt Enable The TI2IE bit enables timer input 2 (EVI) interrupt when TI2F is set. This bit is cleared on reset. 0 = Timer input 2 interrupt disabled 1 = Timer input 2 interrupt enabled OC2IE — Compare 2 Interrupt Enable The OC2IE bit enables compare 2 (CMP2) interrupt when compare match is detected (OC2F is set). This bit is cleared on reset. 0 = Timer input 2 interrupt disabled 1 = Timer input 2 interrupt enabled Bit 5 — Reserved This bit is not used and is always read as logic 0. T2CLK — Timer 2 Clock Select The T2CLK bit selects the clock source for the timer counter 2. This bit is cleared on reset. 0 = CLK2 from prescaler selected 1 = EXCLK from EVI input block selected IM2 — Timer Input 2 Mode Select The IM2 bit selects whether EVI input is gated or not gated by CLK2. This bit is cleared on reset. 0 = EVI not gated by CLK2 (event mode) 1 = EVI gated by CLK2 (gate mode) Address: $001C BIt 7 654321 Bit 0 Read: TI2IE OC2IE 0 T2CLK IM2 IL2 OE2 OL2 Write: Reset: 00000000 Figure 9-8. Timer Control Register 2 (TCR2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 129 NON-DISCLOSURE AGREEMENT REQUIRED IL2 — Timer Input 2 Active Edge (Level) Select The IL2 bit selects the active edge of EVI to increment the counter for event mode (IM2 = 0) or gate enable level of EVI for gate mode (IM2 = 1). This bit is cleared on reset. 0 = Falling edge selected (event mode) Low level enables counting (gate mode) 1 = Rising edge selected (event mode) High level enables counting (gate mode) OE2 — Timer Output 2 (EVO) Output Enable The OE2 bit enables EVO output on the PC5 pin. When this bit is changed, control of the pin is delayed (synchronized) until the next active edge of EVO is selected by the OL2 bit. This bit is cleared on reset. 0 = EVO output disabled 1 = EVO output enabled OL2 — Timer Output 2 Edge Select for Synchronization The OL2 bit selects which edge of EVO clock should be synchronized by the OE2 bit control. The OL2 bit also decides the initial value of the CMP2 divider, when counter 2 is written to by the CPU. This bit is cleared on reset. 0 = The falling edge of EVO switches EVO output and PC5 if the OE2 bit has been changed. 1 = The rising edge of EVO switches EVO output and PC5 if the OE2 bit has been changed. Table 9-1. EVI Modes Selection IM2 IL2 Action on Clock 0 0 Falling edge of EVI increments counter 0 1 Rising edge of EVI increments counter 1 0 Low level on EVI enables counting 1 1 High level on EVI enables counting Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

130 Timer System MOTOROLA

9.4.2 Timer Status Register 2

TI2F — Timer Input 2 (EVI) Interrupt Flag In event mode, the event edge sets TI2F. In gated time accumulation mode, the trailing edge of the gate signal at the EVI input pin sets TI2F. When the TI2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no effect. The TI2F is cleared by writing a logic 1 to the RTI2F bit and on reset. OC2F — Compare 2 Interrupt Flag The OC2F bit is set when compare match is detected between counter 2 and OC2 register. When OC2IE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and writes have no effect. The OC2F is cleared by writing a logic 1 to ROC2F bit and on reset. Bits 5 and 4 — Reserved These bits are not used and always read as logic 0. RTI2F — Reset Timer Input 2 Flag The RTI2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the TI2F bit and writing a logic 0 to this bit has no effect. ROC2F — Reset Output Compare 2 Flag The ROC2F bit is a write-only bit and always reads as logic 0. Writing logic 1 to this bit clears the OC2F bit and writing a logic 0 to this bit has no effect. Bits 1 and 0 — Reserved These bits are not used and always read as logic 0. Address: $001D BIt 7 654321 Bit 0 Read: TI2F OC2F 00 00 00Write: RTI2F ROC2F Reset: 00000000 = Unimplemented Figure 9-9. Timer Status Register 2 (TSR2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 131 NON-DISCLOSURE AGREEMENT REQUIRED

9.4.3 Output Compare Register 2

The OC2 register data is transferred to the buffer register when the CPU writes to TCNT2, when the CMP2 presets the TCNT2, or when system resets. When the OC2 buffer register matches the TCNT2 register, the OC2F bit in the TSR2 register is set and TCNT2 is preset to $01.

9.4.4 Timer Counter Register 2

TCNT2 is incremented by the falling edge of the timer clock, which is synchronized and has the same timing as the falling edge of PH2. The TCNT2 register is compared with the OC2 buffer register and initialized to $01 if it matches. It is also initialized to $01 on reset and any CPU write to this register. The CPU read of this counter should be done while PH2 is high. Data may be latched by the local or main data bus while PH2 is low. Address: $001E BIt 7 654321 Bit 0 Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write: Reset: 00000000 Figure 9-10. Output Compare Register 2 (OC2) Address: $001F BIt 7 654321 Bit 0 Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write: Reset: 00000001 Figure 9-11. Timer Counter Register 2 (TCNT2) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

132 Timer System MOTOROLA

9.4.5 Timebase Control Register 1

T2R1/T2R0 — Prescale Rate Select Bits for Timer 2 The T2R1 and T2R0 bits select prescale rate of CLK2 for timer 2 and timer input 2. These bits are cleared on reset.

9.4.6 Timer Input 2 (EVI)

The event input (EVI) is used as an external clock input for timer 2. Figure 9-13. EVI Block Diagram Address: $0010 BIt 7 654321 Bit 0 Read: TBCLK 0 LCLK 0 0 0 T2R1 T2R0 Write: Reset: 00000000 Figure 9-12. Timebase Control Register 1 (TBCR1) Table 9-2. Time Base Prescale Rate Selection T2R1 T2R0 System Clock Divided by 00 1 01 4 10 3 2 1 1 256 PC4 EVI SYNC ACTIVE EDGE/LEVEL SELECTOR GATE/EVENT MODE CONTROL PC4 PH2 IL2 IM2 CLK2 TO TI2F EXCLK Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 133 NON-DISCLOSURE AGREEMENT REQUIRED Since the external clock may be asynchronous to the internal clock, this input has a synchronizer which samples external clock by the internal system clock. (The input transition synchronizes to the falling edge of PH2. Therefore, to be measured, the minimum pulse width for EVI must be larger than one system clock.) The IM2 and IL2 bits in the TCR2 determine how this synchronized external clock is used. The IM2 bit decides between event mode and gate mode, and the IL2 bit decides which level or edge is activated. In event mode (IM2 = 0), the external clock drives the timer 2 counter directly and the active edge at the EVI pin is selected by the IL2 bit. When an active edge is detected, the TI2F bit in the TCR2 is set. NOTE: Since the EVI pin is shared with the PC4 I/O pin, DDRC4 should always be cleared whenever EVI is used. EVI should not be used when DDRC4 is high. In gate mode (IM2 = 1), the EVI input is gated by CLK2 from the prescaler and gate output drives the timer 2 counter. The IL2 bit decides active level of the external input. When the transition from active level to inactive level is detected, the TI2F bit is set. Changing the IM2 bit may cause an illegal count up of TCNT2, thus presetting TCNT2 after initializing IM2 is required. Table 9-3. EVI Modes Selection IM2 IL2 Action on Clock 0 0 Falling edge of EVI increments counter 0 1 Rising edge of EVI increments counter 1 0 Low level on EVI enables counting 1 1 High level on EVI enables counting Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

134 Timer System MOTOROLA

Figure 9-14. EVI Timing Diagram X+1 X+2COUNTER PH2 EXCLK IL2 = 0 IM2 = 0 Event Mode EVI X X+1 X+2COUNTER EXCLK IL2 = 1 X COUNTER CLK2 EXCLK IL2 = 0 IM2 = 1 Gate Mode EVI SYNCHRONIZED COUNTER EXCLK IL2 = 1 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 135 NON-DISCLOSURE AGREEMENT REQUIRED

9.4.7 Event Output (EVO)

The EVO pin is the clock output pin of timer 2. The compare output from the timer 2 (CMP2) is divided in this block for 50% duty output signal. This 1/2 divider is initialized to the level of the OL2 bit when the timer counter 2 is written to by the CPU (initialized). When the OE2 bit in the timer control register 2 (TCR2) is set, the EVO output is activated, and, when OE2 is cleared, EVO is deactivated. These controls must be done synchronously to the EVO output signal to avoid an incomplete pulse on the pin. The OL2 bit in the TCR2 decides which edge of EVO should be synchronized. When the DDRC5 bit is set or the synchronized output enable is high (clock on), the output buffer at the EVO/PC5 pin is enabled. If the DDRC5 bit is set to 1, the pin state during the idling condition (clock off) depends on the PC5 output data latch. If the DDRC5 bit is cleared, the pin becomes high impedance during clock off. Figure 9-15. EVO Block Diagram D C Q SEL PC5 EVO OE2 OL2 CMP2 CNTR2 WRITE PC5 (OUT) PC5 (IN) DDRC5 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

136 Timer System MOTOROLA

Figure 9-16. EVO Timing Diagram PC5 = 0/EVO OE2 CMP2/2 OL2 = 0 CMP2 EVO PC5 = 1/EVO OE2 CMP2/2 OL2 = 1 CMP2 EVO CNTR2 WRITE Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Timer System 137 NON-DISCLOSURE AGREEMENT REQUIRED

9.5 Prescaler

The 8-bit prescaler in the timer system divides system clock (PH2) and provides divided clock to each timer and event input. CLK1 for timer 1 is a fixed frequency clock (PH2/PH4). CLK2 for timer 2 is selected by T2R1 and T2R0 bits in the TBCR1, and this clock is also used as the event input for gate mode. The CLK2 transitions must be synchronous to the falling edge of PH2. Figure 9-17. Prescaler Block Diagram Table 9-4. Timebase Prescale Rate Selection T2R1 T2R0 System Clock Divided by 00 1 01 4 10 3 2 1 1 256 8-BIT DIVIDER SEL 1111 1 4 32 256 T2R1 T2R0 CLK2 FOR TIMER 2 CLK1 FOR TIMER 11 RST PH2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Timer System General Release Specification MC68HC(7)05L5 — Rev. 2.0

138 Timer System MOTOROLA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA LCD Driver 139 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 10. LCD Driver

10.1 Contents

10.2 Introduction

The LCD driver may be configured with four backplanes (BP) and 39 frontplanes (FP) maximum. The VDD voltage is the highest level of the output waveform and the lower three levels are applied from VLCD1, VLCD2, and VLCD3 inputs. On reset, LCD enable bit (LCDE) in the LCD control register (LCDCR) is cleared (LCD drivers at a disabled state) and all BP pins and FP pins output VDD levels. The LCD clock is generated by the timebase module, and the LCLK bit in the TBCR1 selects the clock frequency. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED LCD Driver General Release Specification MC68HC(7)05L5 — Rev. 2.0

140 LCD Driver MOTOROLA

10.3 LCD Waveform Examples

Figure 10-1,Figure 10-2,Figure 10-3, andFigure 10-4 illustrate the LCD timing examples. Figure 10-1. LCD 1/1 Duty and 1/1 Bias Timing Diagram

1 FRAME

DUTY = 1/1 (STATIC) BIAS = 1/1 (VLCD1 = VDD , VLCD2 = VLCD3 = VDD –VLCD) BP0 FPx (XXX1) FPy (XXX1) BP0–FPx (0FF) BP0–FPy (ON) VDD , VLCD1 VLCD2, 3 VDD , VLCD1 VLCD2, 3 VDD , VLCD1 VLCD2, 3 +VLCD –VLCD +VLCD –VLCD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA LCD Driver 141 NON-DISCLOSURE AGREEMENT REQUIRED Figure 10-2. LCD 1/2 Duty and 1/2 Bias Timing Diagram DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = VDD –VLCD/2, VLCD3 = VDD –VLCD) FPY (XX00) FPX(XX01) BP0–FPY (0FF) VDD BP1–FPX (OFF) BP0 VLCD1, 2 VLCD3 BP1 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 VDD VLCD1, 2 VLCD3 VLCD VLCD/2 –VLCD/2 –VLCD VLCD VLCD/2 –VLCD/2 –VLCD BP0–FPX (ON) VLCD VLCD/2 –VLCD/2 –VLCD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED LCD Driver General Release Specification MC68HC(7)05L5 — Rev. 2.0

142 LCD Driver MOTOROLA

Figure 10-3. LCD 1/3 Duty and 1/3 Bias Timing Diagram DUTY = 1/3 BIAS = 1/3 (VLCD1 = VDD –VLCD/3, VLCD2 = VDD –2VLCD/3, VLCD3 = VDD –VLCD) BP0 FPx (X010) VDD VLCD1 VLCD3 VDD VLCD2 VLCD3 VDD VLCD1 VLCD2 VLCD3 VDD VLCD1 BP1–FPx (ON) +2VLCD/3 +VLCD/3 –VLCD/3 –2VLCD/3 –VLCD +VLCD +2VLCD/3 +VLCD/3 –VLCD/3 VLCD2 VLCD1 VLCD2 VLCD3 +VLCD –2VLCD/3 –VLCD BP1 BP0–FPx (OFF) BP2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA LCD Driver 143 NON-DISCLOSURE AGREEMENT REQUIRED Figure 10-4. LCD 1/4 Duty and 1/3 Bias Timing Diagram DUTY = 1/4 BIAS = 1/3 (VLCD1 = VDD –VLCD/3, VLCD2 = VDD –2VLCD/3, VLCD3 = VDD –VLCD) BP0 FPX (1001) VDD VLCD1 VLCD3 VDD VLCD2 VLCD3 VDD VLCD1 VLCD2 VLCD3 VDD VLCD1 VLCD1 VLCD2 +VLCD +2VLCD/3 +VLCD/3 –VLCD/3 –2VLCD/3 –VLCD +VLCD/3 VLCD2 VLCD1 VLCD2 VLCD3 VDD VLCD3 –VLCD/3 BP1 BP1–FPX (OFF) BP2 +VLCD +2VLCD/3 –2VLCD/3 –VLCD BP3 BP0–FPX (ON) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED LCD Driver General Release Specification MC68HC(7)05L5 — Rev. 2.0

144 LCD Driver MOTOROLA

10.4 Backplane Driver and Port Selection

The number of backplane (port D) pins depends on the LCD duty. It is automatically selected by DUTY1 and DUTY0 bits in the LCD control register (LCDCR). On reset, these bits are cleared and 1/4 duty is selected. (SeeTable 10-1.) Table 10-1. Backplane and Port Selection Duty LCD Control Pin Selection DUTY1 DUTY0 BP3/PD3 BP2/PD2 BP1/PD1 BP0 1 / 1 0 1 PD3 PD2 PD1 BP0 1 / 2 1 0 PD3 PD2 BP1 BP0 1 / 3 1 1 PD3 BP2 BP1 BP0 1 / 4 0 0 BP3 BP2 BP1 BP0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Frontplane Driver and Port Selection MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA LCD Driver 145 NON-DISCLOSURE AGREEMENT REQUIRED

10.5 Frontplane Driver and Port Selection

The number of frontplane (FP) pins depends on the number of port D and port E bits. If port bits are selected as a parallel output port, the number of the FP pins is decreased to 27 as a minimum. The selections between frontplane and port (nibble wide) are done by the PEH, PEL, and PDH bits in the LCDCR (seeTable 10-2). On reset, port D and port E bits are disconnected and FP27–FP38 pins output VDD levels. Table 10-2. Frontplane and Port Selection FP / Port Control Port Selection PEH PEL PDH FP27:FP30/ PE7:PE4 FP31:FP34/ PE3:PE0 FP35:FP38/ PD7:PD4

0 FP35:FP38

1 PD7:PD4

0 FP31:FP34

1 PE3:PE0

0 FP27:FP30

1 PE7:PE4

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED LCD Driver General Release Specification MC68HC(7)05L5 — Rev. 2.0

146 LCD Driver MOTOROLA

10.6 LCD Control Register

LCDE — LCD Output Enable The LCDE bit enables all BP and FP outputs. (This bit does not affect PEH, PEL, or PDH bits.) This bit is cleared on reset. 0 = All dedicated FP pins output highest (VDD ) level; BP and FP pins are shared with an output port data. 1 = All BP and FP pins output LCD waveforms. DUTY1 and DUTY0 — LCD Duty Select The DUTY1 and DUTY0 bits select the duty of the LCD driver. The number of BP pins is related to this duty selection. The unused BP pin is used as a port D pin. Default duty is 1/4 duty. These bits are cleared on reset. SeeTable 10-1. Bit 4 — Reserved This bit is not used and always reads as logic 0. PEH — Select Port E (H) The PEH bit enables the upper four bits of port E instead of LCD drivers. This bit is cleared on reset. See10.5 Frontplane Driver and Port Selection. 0 = FP27–FP30 selected 1 = PE7–PE4 selected Address: $0020 Bit 7 654321 Bit 0 Read: LCDE DUTY1 DUTY0 0 PEH PEL PDH 0 Write: Reset: 00000000 Figure 10-5. LCD Control Register (LCDCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA LCD Driver 147 NON-DISCLOSURE AGREEMENT REQUIRED PEL — Select Port E (L) The PEL bit enables the lower four bits of port E instead of LCD drivers. This bit is cleared on reset. See10.5 Frontplane Driver and Port Selection. 0 = FP31–FP34 selected 1 = PE3–PE0 selected PDH — Select Port D (H) The PDH bit enables the upper four bits of port D instead of LCD drivers. This bit is cleared on reset. See10.5 Frontplane Driver and Port Selection. 0 = FP35–FP38 selected 1 = PD7–PD4 selected Bit 0 — Reserved This bit is not used and is always read as logic 0. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED LCD Driver General Release Specification MC68HC(7)05L5 — Rev. 2.0

148 LCD Driver MOTOROLA

10.7 LCD Data Register

LCDRx — LCD Data Registers Data in the LCDRx (LCDR1–LCDR20) controls the waveform of the two frontplane drivers. Bits 0–3 and bits 4–7 of this register decide the waveforms at the BP0–BP3 timings. If the LCD duty is not 1/4, the register bit for the unused backplane has no meaning. The upper four bits of LCDR20 are not implemented and unknown data may be read. (See Table 10-3.) 0 = Output deselect waveform at the corresponding backplane timing 1 = Output select waveform at the corresponding backplane timing Address: $0021–$0034 FP (2x–1) FP (2x–2) Bit 7 654321 Bit 0 Read: BP3 BP2 BP1 BP0 BP3 BP2 BP1 BP0 Write: Reset: Unaffected by Reset Figure 10-6. LDC Data Registers Table 10-3. Frontplane Data Register Bit Usage Duty Frontplane Data Register Bit Usage Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 / 2 — — BP1 BP0 — — BP1 BP0 1 / 3 — BP2 BP1 BP0 — BP2 BP1 BP0 1 / 4 BP3 BP2 BP1 BP0 BP3 BP2 BP1 BP0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 149 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 11. Instruction Set

11.1 Contents

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

150 Instruction Set MOTOROLA

11.2 Introduction

The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.

11.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 151 NON-DISCLOSURE AGREEMENT REQUIRED

11.3.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.

11.3.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.

11.3.3 Direct

Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.

11.3.4 Extended

Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

152 Instruction Set MOTOROLA

11.3.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.

11.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.

11.3.7 Indexed,16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 153 NON-DISCLOSURE AGREEMENT REQUIRED

11.3.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.

11.4 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

154 Instruction Set MOTOROLA

11.4.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions Instruction Mnemonic Add Memory Byte and Carry Bit to Accumulator ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract Memory Byte from Accumulator SUB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 155 NON-DISCLOSURE AGREEMENT REQUIRED

11.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 11-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left (Same as LSL) ASL Arithmetic Shift Right ASR Bit Clear BCLR (1) 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. Bit Set BSET (1) Clear Register CLR Complement (One’s Complement) COM Decrement DEC Increment INC Logical Shift Left (Same as ASL) LSL Logical Shift Right LSR Negate (Two’s Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST (2) 2. TST is an exception to the read-modify-write sequence be- cause it does not write a replacement value. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

156 Instruction Set MOTOROLA

11.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 157 NON-DISCLOSURE AGREEMENT REQUIRED Table 11-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch ifIRQ Pin High BIH Branch ifIRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

158 Instruction Set MOTOROLA

11.4.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions Instruction Mnemonic Bit Clear BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Bit Set BSET Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 159 NON-DISCLOSURE AGREEMENT REQUIRED

11.4.5 Control Instructions

These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Stop Oscillator and EnableIRQ Pin STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable InterruptsWAIT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

160 Instruction Set MOTOROLA

11.5 Instruction Set Summary

Table 11-6. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Add with Carry A ← (A) + (M) + (C) ↕ — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ← (A) + (M) ↕ — ↕↕↕ IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left (Same as LSL) — — ↕↕↕ DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — ↕↕↕ DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ← 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ← (PC) + 2 +rel ? Z = 1 ————— R E L 2 7 r r 3 BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 +rel ? H = 0 ————— R E L 2 8 r r 3 BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 +rel ? H = 1 ————— R E L 2 9 r r 3 C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 161 NON-DISCLOSURE AGREEMENT REQUIRED BHI rel Branch if Higher PC ← (PC) + 2 +rel ? C∨ Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BIH rel Branch if IRQ Pin High PC ← (PC) + 2 +rel ? IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 +rel ? IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte (A) ∧ (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch if Lower orSame PC ← (PC) + 2 +rel ? C∨ Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 +rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ← (PC) + 2 +rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ← (PC) + 2 +rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ← (PC) + 2 +rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ← (PC) + 2 +rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr relBranch if Bit n Clear PC ← (PC) + 2 +rel ? M n = 0 ———— ↕ DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ← (PC) + 2 +rel ? 1 = 0 ————— R E L 2 1 r r 3 BRSET n opr relBranch if Bit n Set PC ← (PC) + 2 +rel ? M n = 1 ———— ↕ DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BSET n opr Set Bit n Mn ← 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

162 Instruction Set MOTOROLA

BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) +rel CLC Clear Carry Bit C ← 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2 CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte (A) – (M) — — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (A) X ← (X) = $FF – (X) M ← (M) = $FF – (M) M ← (M) = $FF – (M) —— ↕↕ 1 DIR INH INH IX1 IX dd ff CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte (X) – (M) — — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory Byte A ← (A)⊕ (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff INC opr INCA INCX INC opr,X INC ,X Increment Byte M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 DIR INH INH IX1 IX dd ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 163 NON-DISCLOSURE AGREEMENT REQUIRED JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ← Jump Address ————— DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP← (SP) – 1 Push (PCH); SP← (SP) – 1 PC ← Effective Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ← (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ← (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left (Same as ASL) — — ↕↕↕ DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 ↕↕ DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ← (X)× (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) DIR INH INH IX1 IX dd ff NOP No Operation ————— I N H 9 D 2 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory A ← (A)∨ (M) — — ↕↕ — IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set General Release Specification MC68HC(7)05L5 — Rev. 2.0

164 Instruction Set MOTOROLA

ROL opr,X ROL ,X Rotate Byte Left through Carry Bit — — ↕↕↕ DIR INH INH IX1 IX dd ff ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit — — ↕↕↕ DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ← $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL)————— I N H 8 1 6 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ← 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in Memory M ← (A) — — ↕↕ — DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ← (X) — — ↕↕ — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator A ← (A) – (M) — — ↕↕↕ IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Instruction Set 165 NON-DISCLOSURE AGREEMENT REQUIRED

11.6 Opcode Map

See Table 11-7. SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register X ← ( A ) ————— I N H 9 7 2 TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 — — ↕↕ — DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator A ← ( X ) ————— I N H 9 F 2 WAIT Stop CPU Clock and Enable Interrupts — 0 — — — INH 8F 2 A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask ∧ Logical AND ii Immediate operand byte ∨ Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag ↕ Set or cleared n Any bit — Not affected Table 11-6. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIREDGeneral Release Specification MC68HC(7)05L5 — Rev. 2.0

166 Instruction Set MOTOROLA

Table 11-7. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

0123456789 ABCDEF

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 12. Electrical Specifications

12.1 Contents

12.2 Introduction

This section contains parametric and timing information. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC(7)05L5 — Rev. 2.0

12.3 Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. Keep VIn and VOut within the range VSS ≤ (VInor VOut)≤ VDD . Connect unused inputs to the appropriate voltage level, either VSS or VDD . NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to12.7 5.0-Volt DC Electrical Characteristicsand 12.8 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions. Rating Symbol Value Unit Supply voltage VDD VLCD1 VLCD2 VLCD3 –0.3 to +7.0 VSS –0.3 to VDD +0.3 VSS –0.3 to VDD +0.3 VSS –0.3 to VDD +0.3 V Input voltage V In VSS –0.3 to VDD + 0.3 V Self-check mode (IRQ1 pin only) VIn VSS –0.3 to 2 x VDD + 0.3 V Output voltage V Out VSS –0.3 to VDD + 0.3 V Current drain per pin excluding VDD and VSS I 12.5 mA Operating junction temperature T J +150 °C Storage temperature range T stg –55 to +150 °C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Operating Temperature Range MC68HC(7)05L5 — Rev. 2.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

12.4 Operating Temperature Range

12.5 Thermal Characteristics

12.6 Recommended Operating Conditions

Characteristic Symbol Value Unit Operating temperature range MC68HC05L5 (standard) MC68HC05L5C (extended) TA TL to TH 0 to +70 –40 to +85 Characteristic Symbol Value Unit Thermal resistance 80-pin plastic quad flat pack θJA 120 °C/W Rating(1) 1. +2.2≤ VDD ≤ +5.5 Vdc, VSS = 0 Vdc, TL ≤ TA ≤ TH , unless otherwise noted Symbol Min Typ Max Unit Supply voltage (fOP = 2.1 MHz) V DD 4.5 5.0 5.5 V (fOP = 1.0 MHz) V DD 2.2 — 5.5 V VLCD1 VDD – 1/3 VLCD V VLCD2 VDD – 2/3 VLCD V VLCD3 VDD – 3/3 VLCD V Fast clock oscillation frequency fOSC — 3.52 4.2 MHz External capacitance (fOSC = 3.52 MHz) — pF Slow clock oscillation frequency fXOSC — 32.768 — MHz External capacitance (fXOSC = 32.768 kHz) CX1 CX2 — pF Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC(7)05L5 — Rev. 2.0 12.7 5.0-Volt DC Electrical Characteristics Characteristic(1) 1. +4.5≤ VDD ≤ +5.5 Vdc, VSS = 0 Vdc, TL ≤ TA ≤ TH , unless otherwise noted. All values shown reflect average measure- ments. Typical values at midpoint of voltage range, 25°C only. Symbol Min Typ Max Unit Output voltage ILoad = 10.0 µA ILoad = –10.0µA VOL VOH VDD –0.1 0.1 V Output high voltage (VDD = 5.0 V) (ILoad = –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOH VDD –0.8 — — V Output low voltage (VDD = 5.0 V) (ILoad = 0.8 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOL — — 0.4 V Input high voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIH 0 . 8xVDD —V DD V Input low voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIL VSS — 0.2 x V DD V Supply current(2), (3), (4), (5) Run (fop = 2.1 MHz) Wait (fop = 2.1 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 5.0 V, TA = +25oC 2. Run (Operating) IDD , wait IDD ; measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail (VSS or VDD ); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD ; all ports configured as inputs; VIL = 0.2 V; VIH = VDD –0.2 V 4. Stop IDD measured with OSC1 = VSS . 5. Wait IDD is affected linearly by the OSC2 capacitance. IDD 6.0 3.0 3.0 17.0 12.0 6.0 10.0 mA mA µA µA Input current(6) (with pullups disabled) PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 6. Input current is measured with output transistor turned off and VIn = 0 V. Iin —— ± 1.0 µA Input current(6) (with pullups enabled, VDD = 5.0 V) PA0–PA7 PB0–PB7 PC0–PC7 Iin 150 150 150 500 340 340 1000 µA µA µA LCD pin output impedance FP0–FP26 BP0–BP3 Zo, FP Zo, BP kΩ kΩ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

3.3-Volt DC Electrical Characteristics MC68HC(7)05L5 — Rev. 2.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED 12.8 3.3-Volt DC Electrical Characteristics Characteristic(1) Typical values at midpoint of voltage range, 25°C only. Symbol Min Typ Max Unit Output voltage ILoad = 10.0 µA ILoad = –10.0µA VOL VOH VDD –0.1 0.1 V Output high voltage (VDD = 3.5 V) (ILoad = –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOH VDD –0.8 — — V Output low voltage (VDD = 3.5 V) (ILoad = 0.8 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOL — — 0.4 V Input high voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET,OSC1, XOSC1 VIH 0.8 x VDD —V DD V Input low voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIL VSS —0 2 x V DD V Supply current(2), (3), (4), (5) Run (fop = 1.0 MHz) Wait (fop = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 3.0 V, TA= +25oC 2. Run (Operating) IDD , wait IDD ; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD ); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD ; all ports configured as inputs; VIL = 0.2 V; VIH = VDD –0.2 V 4. Stop IDD measured with OSC1 = VSS . 5. Wait IDD is affected linearly by the OSC2 capacitance. IDD 1.8 0.8 2.0 8.0 8.0 5.0 10.0 mA mA µA µA Input current(6) (with pullups disabled) PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 6. Input current is measured with output transistor turned off and VIn = 0 V. IIn —— ± 1.0 µA Input current(6) (with pullups enabled, VDD = 3.3 V) PA0–PA7 PB0–PB7 PC0–PC7 IIn 300 230 230 760 µA µA µA LCD pin output impedance FP0–FP26 BP0–BP3 Zo, FP Zo, BP kΩ kΩ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC(7)05L5 — Rev. 2.0 12.9 2.7-Volt DC Electrical Characteristics Characteristic(1) Typical values at midpoint of voltage range, 25°C only. Symbol Min Typ Max Unit Output voltage ILoad = 10.0 µA ILoad = –10.0µA VOL VOH VDD –0.1 0.1 V Output high voltage (VDD = 2.2 V) (ILoad = –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOH VDD –0.6 — — V Output low voltage (VDD = 2.2 V) (ILoad = 0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOL — — 0.3 V Input high voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIH 0 . 8xVDD —V DD V Input low voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIL VSS — 0.2 x V DD V Supply current(2), (3), (4), (5) Run (fop = 1.0 MHz) Wait (fop = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 2.2 V, TA= +25oC 2. Run (Operating) IDD , wait IDD ; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD ); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD ; all ports configured as inputs; VIL = 0.2 V; VIH = VDD –0.2 V 4. Stop IDD measured with OSC1 = VSS . 5. Wait IDD is affected linearly by the OSC2 capacitance. IDD 0.7 0.4 1.5 5.0 8.0 5.0 10.0 mA mA µA µA Input current(6) (with pullups disabled) PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 6. Input current is measured with output transistor turned off and VIn = 0 V. IIn —— ± 1.0 µA Input current(6) (with pullups enabled, VDD = 2.7 V) PA0–PA7 PB0–PB7 PC0–PC7 IIn 150 110 110 420 µA µA µA LCD pin output impedance FP0–FP26 BP0–BP3 Zo, FP Zo, BP kΩ kΩ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

12.10 Control Timing

Characteristic(1) 1. +2.2≤ VDD ≤ +5.5 Vdc, VSS = 0 Vdc, TL ≤ TA ≤ TH , unless otherwise noted. Symbol Min Max Unit Frequency of oscillation (OSC) Crystal External clock fosc — dc 4.2 4.2 MHz Internal operating frequency(2), crystal or external clock (fOSC /2) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V 2. The system clock divider configuration (SYS1–SYS0 bits) should be selected such that the internal operating frequency (fOP ) does not exceed value specified in fOP for a given fOSC . fop — 2.1 1.0 MHz Cycle time (fast OSC selected) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V tcyc 480 1.0 ns µs RESET pulse width when bus clock active t RL 1.5 — t cyc Timer Resolution Input capture (TCAP) pulse width tRESL tTH , tTL 4.0 284 tcyc ns Interrupt pulse width low (edge-triggered) t ILIH 284 — ns Interrupt pulse period(3) 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc. tILIL note 3 — t cyc OSC1 pulse width (external clock input) t OH , tOL 110 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications General Release Specification MC68HC(7)05L5 — Rev. 2.0 Figure 12-1. Stop Recovery Timing Diagram FFFE FFFE FFFE FFFE FFFF 4 tRL tILIH OSC1 1 RESET IRQ2 IRQ3 INTERNAL CLOCK INTERNAL ADDRESS BUS tILCH 8092 tcyc Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option 4. RESET vector address shown for timing example RESET OR INTERRUPT VECTOR FETCH Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA Mechanical Specifications 175 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 13. Mechanical Specifications

13.1 Contents

13.2 Introduction

This section describes the dimensions of the quad flat pack (QFP). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED Mechanical Specifications General Release Specification MC68HC(7)05L5 — Rev. 2.0

176 Mechanical Specifications MOTOROLA

13.3 Quad Flat Pack (QFP) — Case 841B-01

/C0077/C0073 /C0077/C0073/C0077 /C0077 /C0077/C0073 /C0073/C0077 /C0073 /C0073/C0077 /C0074 /C0077 /C0051 /C0051 /C0050 /C0050/C0050 /C0050 /C0050/C0050 /C0051 /C0054 ° ( /C0051 ° ( /C0051 /C0054 /C0051 /C0054 /C0051 /C0050 /C0051 /C0050 /C0051/C0051 /C0050 /C0050/C0051 /C0051 /C0050/C0054 ° ( ° ( /C0054/C0054 ° ( /C0054/C0054 /C0054 /C0051 /C0051 ° ( /C0050 /C0054 /C0054 /C0050 /C0050 /C0051 "# ))! "%""% ’"" " " !)))) ))" /C0054 " #! " #! !/C0050 ""# " #! " #! !/C0051" &!! P -A,B,D- B B DETAIL A F D N SECTION B-B J -H-/C0077 DETAIL C K Q R T W X U -H- /C0077 12 0 DETAIL C /C0073 -C- M C H M G -B--A- -D- B A L S V L E DETAIL A /C0050 ! ! /C0050 /C0050 ! ! /C0050 ! ! /C0050 /C0050 ! ! /C0054 ! /C0050/C0054! /C0050/C0051 /C0054! /C0051/C0050 ! /C0051! /C0054 /C0054 /C0050 ! ! Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Section 14. Ordering Information

14.1 Contents

14.2 Introduction

This section contains instructions for ordering custom-masked ROM MCUs.

14.3 MCU Ordering Forms

To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs:

• A current MCU ordering form that iscompletely filled out (Contact your Motorola sales office for assistance.)
• A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU
• Customer’s application program on one of the media listed in14.4 Application Program Media Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED

Ordering Information

General Release Specification MC68HC(7)05L5 — Rev. 2.0 The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lowercase letters. Then press the return key to start the BBS software.

14.4 Application Program Media

Please deliver the application program to Motorola in one of the following media:

• Macintosh®1 3 1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M)
• MS-DOS ®2 or PC-DOSTM 3 3 1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M)
• MS-DOS ® or PC-DOSTM 5 1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M) Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette On diskettes, the application program must be in Motorola’s S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if non-user areas contain any non-zero code. If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames. In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code.

14.5 ROM Program Verification

The primary use for the on-chip ROM is to hold the customer’s application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer’s application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification MC68HC(7)05L5 — Rev. 2.0

14.6 ROM Verification Units (RVUs)

After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer’s application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer’s user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance.

14.7 MC Order Numbers

Table 14-1 shows the MC order numbers for the available package types. Table 14-1. MC Order Numbers Package Type Operating Temperature Range MC Order Number 80-pin plastic quad flat pack (QFP) 0 °C to +70°C MC68HC05L5FU –40 °C to +85°C MC68HC05L5CFU Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 181 NON-DISCLOSURE AGREEMENT REQUIRED General Release Specification — MC68HC05L5 Appendix A. MC68HC705L5 A.1 Contents A.3 Differences between MC68HC05L5 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

182 MC68HC705L5 MOTOROLA

A.2 Introduction The MC68HC705L5 is similar to the MC68HC05L5 with the exception of the EPROM feature. The program ROM on the MC68HC05L5 has been replaced by 8-K electrically programmable read-only memory to allow modification of the program code for emulation. All information pertaining to the MC68HC05L5 in this document applies to the EPROM part with the additions and exceptions explained in this appendix. The additional features available on the MC68HC705L5 are:

• 8,192 bytes of EPROM
• On-chip bootstrap firmware for programming use
• Self-check mode replaced by bootstrap capability A.3 Differences between MC68HC05L5 and MC68HC705L5 A.4 MCU Structure Figure A-1 shows the structure of the MC68HC705L5 MCU. Table A-1. Differences Between MC68HC05L5 and MC68HC705L5 Item MC68HC05L5 MC68HC705L5 ROM memory type Mask ROM EPROM Internal test mode Self-check mode Bootstrap mode LCD 1/2 duty 1/2 bias waveform See Figure 10-2 See Figure A-6 COP watch dog timer Software selectable No COP function EPROM programming Not applicable Through V PP pin and PCR Mask option Customer specified No mask option OSC, XOSC, and RESET pin resistor option Available by mask option Not available Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 183 NON-DISCLOSURE AGREEMENT REQUIRED Figure A-1. Block Diagram NOTE: A line over a signal name indicates an active low signal. For example, RESET is active low. PA0 PC5/EVO PC6/IRQ2 PC7/IRQ1 PC0/SDI TIME BASE INTERNAL CPU M68HC05 CPU ALU CPU REGISTERS CONTROL SRAM BOOTSTRAP ROM SYSTEM PROCESSOR CLOCK ÷ 2 PA1 PA2 PA3 PA4 PORT A DATA A DIR REG PA5 PA6 PA7 OSC SEL LCD DRIVERS EPROM RESET VDD OSC1 OSC2 VSS PORT B DATA B DIR REG KEY WAKEUP PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB6/KWI6 PB7/KWI7 PB5/KWI5 PB4/KWI4 PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PORT C DATA C DIR REG SPITIMER2 FP0–PF26 PORT E FP36/PD6 BP0 BP2/PD2 BP1/PD1 FP35/PD7 FP37/PD5 FP38/PD4 BP3/PD3 FP28/PE6 FP34/PE0 FP32/PE2 FP33/PE1 FP27/PE7 FP29/PE5 FP30/PE4 FP31/PE3 PORT D VLCD3 VLCD2 VLCD1 DIV VPP (1) 8,192 BYTES XOSCXOSC1 XOSC2 Note 1. The VPP pin should be connected toVDD in single-chip mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

184 MC68HC705L5 MOTOROLA

A.5 Mask Options There are no mask options available for the MC68HC705L5. For this reason, the MOR register at address $000F of option map shown in Section 2. Memory Map has no meaning. A.6 Functional Pin Description The MC68HC705L5 is available in the 80-pin quad flat pack (QFP). The pin assignment is shown inFigure A-2. Figure A-2. Pin Assignments for Single-Chip Mode 20 40 41 6180 VDD FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 VLCD1 VSS VPP (1) XOSC1 XOSC2 RESET VSS FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1/PD1 BP2/PD2 BP3/PD3 VDD PC7/IRQ1 PC6/IRQ2 PC5/EVO PC4/EVI PC3/TCAP PC2/SCK FP27/PE7 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 PC0/SDI PC1/SDO Note 1. The VPP pin should be connect to VDD in single-chip mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 185 NON-DISCLOSURE AGREEMENT REQUIRED Table A-2. Pin Configuration Pin Number SCM, Bootstrap I/O Pin Number SCM, Bootstrap I/O PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 I/O I/O I/O I/O I/O I/O I/O I/O FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 O O O O O O O O O O O O O O O O O O O O O O O O O O O PB0/KWI0 PB1/KWI1 PB2/KWI2 PB3/KWI3 PB4/KWI4 PB5/KWI5 PB6/KWI6 PB7/KWI7 I I I I I I I I PC0/SDI PC1/SDO PC2/SCK PC3/TCAP PC4/EVI PC5/EVO PC6/IRQ2 PC7/IRQ1 I/O I/O I/O I/O I/O I/O I I

17 V PP

(1) I VDD VDD VSS VSS OSC1 OSC2 XOSC1 XOSC2 I I O O I O I O FP27/PE7 FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 O O O O O O O O VLCD1 VLCD2 VLCD3 BP3/PD3 BP2/PD2 BP1/PD1 BP0 I I I O O O O FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 O O O O Note 1. The VPP pin should be connected to VDD in single-chip mode. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

186 MC68HC705L5 MOTOROLA

A.7 Programming Voltage (VPP) In single-chip (user) mode, the VPP pin should be tied to VDD level. A.8 Modes of Operation The MC68HC705L5 has two operating modes: single-chip mode (SCM) and bootstrap mode. Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The bootstrap mode is provided for EPROM programming, dumping EPROM contents, and loading programs into the internal RAM and executing them. This is a very versatile mode because there are essentially no limitations on the special-purpose program that is boot- loaded into the internal RAM. A.8.1 Mode Entry Mode entry is done at the rising edge of theRESET pin. Once the device enters one of the modes, the mode cannot be changed by software. Only an external reset can change the mode. At the rising edge of theRESET pin, the device latches the states of IRQ1 andIRQ2 and places itself in the specified mode. While the RESET pin is low, all pins are configured as single-chip mode. Table A-3 shows the states ofIRQ1 andIRQ2 for each mode entry. High voltage VTST = 2 x VDD is required to select modes other than single-chip mode. Table A-3. Mode Select Summary Modes RESET PC6/ IRQ1 PC7/ IRQ2 Single-chip (user) mode V SS or VDD VSS or VDD Boot-strap mode V TST VDD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 187 NON-DISCLOSURE AGREEMENT REQUIRED Figure A-3. Mode Entry Diagram A.8.2 Single-Chip Mode (SCM) In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows the maximum number of I/O pins for on-chip peripheral functions, for example, ports A through E, and LCD drivers. A.8.3 Bootstrap Mode In this mode, the reset vector is fetched from a 496-byte internal bootstrap ROM at $3E00–$3FEF. The bootstrap ROM contains a small program which loads a program into the internal RAM and then passes control to that program at location $00C0 or executes the EPROM programming sequence and dumps EPROM contents. Since these modes are not normal user modes, all of the privileged control bits are accessible. This allows the bootstrap mode to be used for self test of the device. VTST VDD VSS VDD VSS IRQ2 IRQ1 RESET SINGLE-CHIP MODE VTST = 2 x VDD VDD VSS Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

188 MC68HC705L5 MOTOROLA

A.9 Memory Map The MC68HC705L5 contains a 8,192-byte EPROM, 496 bytes of boot- strap ROM, and 256 bytes of RAM. An additional 16 bytes of EPROM are provided for user vectors at $3FF0–$3FFF. The MCU’s memory map is shown inFigure A-4. Figure A-4. Memory Map $0000 $000F $0010 $003F RAM $0000 $003F $0040 $00C0 $00FF $013F $0140 $0FFF $1000 $2FFF $3000 $3DFF $3E00 $3FDF $3FE0 $3FEF $3FF0 $3FFF UNUSED EPROM UNUSED BOOTSTRAP ROM TEST VECTORS USER VECTORS DUAL-MAPPED iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 189 NON-DISCLOSURE AGREEMENT REQUIRED A.10 Boot ROM Boot ROM is 496 bytes of mask ROM positioned at $3E00–$3FEF. This ROM contains bootstrap loader programs and reset/interrupt vectors in the bootstrap mode. The bootstrap loader programs include:

• EPROM programming and verification
• Dumping EPROM contents
• Loading programs into the internal RAM
• Executing programs in the internal RAM A.11 EPROM The 8-Kbyte EPROM is positioned at $1000–$2FFF, and the additional 16 bytes of EPROM are located at $3FF0–$3FFF for user vectors. The erased state of EPROM is read as $FF and EPROM power is supplied from the VPP pin and the VDD pin. The program control register (PCR) is provided for EPROM programming and testing. The functions of EPROM depend on the device mode. In user mode, ELAT and PGM bits in the PCR are available for user programming, and the remaining test bits become read-only bits. The VPP pin should be tied to 5 volts or programming voltage. A.11.1 Programming Sequence To program the MC68HC705L5, execute this sequence:
• Set the ELAT bit
• Write the data to the address to be programmed
• Set the PGM bit
• Delay for an appropriate amount of time
• Clear the PGM bit and the ELAT bit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

190 MC68HC705L5 MOTOROLA

Clearing the PGM bit and the ELAT bit may be done on a single CPU write. NOTE: It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. A.11.2 Program Control Register A program control register is provided for EPROM programming. Bits 7–3 — Reserved These bits are reserved and read as logic 0 in user mode. Bit 2 — Reserved This bit is not used and always reads as logic 0. ELAT — EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (Writes to EPROM cause address and data to be latched.) EPROM is in programming mode and cannot be read if ELAT is logic 1. This bit should not be set when no programming voltage is applied to the VPP pin. PGM — EPROM ProGraM command 0 = Programming power switched off from EPROM array 1 = Programming power switched on to EPROM array If ELAT≠ 1, then PGM = 0. Address: $000D Bit 7 654321 Bit 0 Read: RRRRRR E L A T P G M Write: Reset: 00000000 R = Reserved Figure A-5. Program Control Register (PCR) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 191 NON-DISCLOSURE AGREEMENT REQUIRED A.12 COP Watchdog Timer The MC68HC705L5 does not have a COP watchdog timer. For this reason, the COPE and COPC bits in timebase control register 2 (address: $0011) has no meaning. These bits are not used and always read as logic 0. Also or the same reason, COP watchdog timer reset does not occur on the MC68HC705L5. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

192 MC68HC705L5 MOTOROLA

A.13 LCD 1/2 Duty and 1/2 Bias Timing Diagram Figure A-6. CD 1/2 Duty and 1/2 Bias Timing Diagram 1FRAME DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = VDD –VLCD/2, VLCD3 = VDD –VLCD) BP0 FPx (XX10) BP0–FPx (OFF) VDD VLCD1, 2 VDD VLCD1, 2 VDD VLCD1, 2 VLCD3 +VLCD +VLCD/2 BP0–FPy (OFF) BP1–FPy (OFF) +VLCD/2 –VLCD +VLCD +VLCD/2 –VLCD/2 –VLCD +VLCD +VLCD/2 VLCD3 VLCD3 -VLCD/2 +VLCD –VLCD/2 –VLCD/2 –VLCD BP1 BP1–FPx (ON) -VLCD FPy (XX00) VDD VLCD1, 2 VLCD3 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 193 NON-DISCLOSURE AGREEMENT REQUIRED A.14 Electrical Specifications This section contains parametric and timing information for the MC68HC705L5. A.14.1 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in this table. Keep VIn and VO UT within the range VSS ≤ (VInor VO UT )≤ VDD . Connect unused inputs to the appropriate voltage level, either VSS or VDD . NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer toA.15.2 5.0-Volt DC Electrical Characteristicsand A.15.3 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions. Rating Symbol Value Unit Supply voltage VDD VLCD1 VLCD2 VLCD3 –0.3 to +7.0 VSS –0.3 to VDD +0.3 VSS –0.3 to VDD +0.3 VSS –0.3 to VDD +0.3 V Input voltage V In VSS –0.3 to VDD + 0.3 V Boot-strap mode IRQ1 pin only VIn VSS –0.3 to 2 x VDD + 0.3 V Output voltage V Out VSS –0.3 to VDD + 0.3 V Current drain per pin excluding VDD and VSS I 12.5 mA Operating junction temperature T J +150 °C Storage temperature range T stg –55 to +150 °C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

194 MC68HC705L5 MOTOROLA

A.14.2 Operating Temperature Range A.14.3 Thermal Characteristics A.15 Recommended Operating Conditions A.15.1 EPROM Programming Voltage Characteristic Symbol Value Unit Operating temperature range MC68HC705L5 (standard) TA TL to TH 0 to +70 °C Characteristic Symbol Value Unit Thermal resistance 80-pin plastic quad flat pack θJA 120 °C/W Rating(1) 1. +3.0≤ VDD ≤ +5.5 Vdc, VSS = 0 Vdc, TL ≤ TA ≤ TH , unless otherwise noted Symbol Min Typ Max Unit Supply voltage (fOP = 2.1 MHz) V DD 4.5 5.0 5.5 V (fOP = 1.0 MHz) V DD 3.0 — 5.5 V VLCD1 VDD – 1/3 VLCD V VLCD2 VDD – 2/3 VLCD V VLCD3 VDD – 3/3 VLCD V Fast clock oscillation frequency fOSC — 3.52 4.2 MHz External capacitance (fOSC = 3.52 MHz) — pF Slow clock oscillation frequency fXOSC — 32.768 — MHz External capacitance (fXOSC = 32.768 kHz) CX1 CX2 — pF Characteristics(1) 1. VDD = 5.0 Vdc, VSS = 0 Vdc, TA = 25oC Symbol Min Typ Max Unit EPROM programming voltage V PP 12.0 12.5 13.0 V Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 195 NON-DISCLOSURE AGREEMENT REQUIRED A.15.2 5.0-Volt DC Electrical Characteristics Characteristic(1) Typical values at midpoint of voltage range, 25°C only. Symbol Min Typ Max Unit Output voltage ILoad = 10.0 µA ILoad = –10.0µA VOL VOH VDD –0.1 0.1 V Output high voltage (VDD = 5.0 V) (ILoad = –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOH VDD –0.8 — — V Output low voltage (VDD = 5.0 V) (ILoad = 0.8 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOL — — 0.4 V Input high voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIH 0.8 x VDD —V DD V Input low voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIL VSS — 0.2 x V DD V Supply current(2), (3), (4), (5) Run (fOP = 2.1 MHz) Wait (fOP = 2.1 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 5.0 V, TA = +25oC 2. Run (Operating) IDD , wait IDD ; measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail (VSS or VDD ); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD ; all ports configured as inputs; VIL = 0.2 V; VIH = VDD –0.2 V 4. Stop IDD measured with OSC1 = VSS . 5. Wait IDD is affected linearly by the OSC2 capacitance. IDD 6.0 3.0 3.0 17.0 12.0 6.0 10.0 mA mA µA µA Input current(6)(with pullups disabled) PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 6. Input current measured with output transistor turned off and VIn = 0 V. IIn —— ± 1.0 µA Input current(6) (with pullups enabled, VDD = 5.0 V) PA0–PA7 PB0–PB7 PC0–PC7 IIn 160 150 150 500 340 340 1000 µA µA µA LCD pin output impedance FP0–FP26 BP0–BP3 Zo, FP Zo, BP kΩ kΩ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

196 MC68HC705L5 MOTOROLA

A.15.3 3.3-Volt DC Electrical Characteristics Characteristic(1) Typical values at midpoint of voltage range, 25°C only. Symbol Min Typ Max Unit Output voltage ILoad = 10.0 µA ILoad = –10.0µA VOL VOH VDD –0.1 0.1 V Output high voltage (VDD = 3.5 V) (ILoad = –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOH VDD –0.8 — — V Output low voltage (VDD = 3.5 V) (ILoad = 0.8 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 VOL — — 0.4 V Input high voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIH 0.8 x VDD —V DD V Input low voltage PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 VIL VSS — 0.2 x V DD V Supply current(2), (3), (4), (5) Run (fOP = 1.0 MHz) Wait (fOP = 1.0 MHz) Stop No clock XOSC = 32.768 kHz, VDD = 3.0 V, TA= +25oC 2. Run (Operating) IDD , wait IDD ; measured using external square wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail (VSS or VDD ); no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 3. Wait, stop IDD ; all ports configured as inputs; VIL = 0.2 V; VIH = VDD –0.2 V 4. Stop IDD measured with OSC1 = VSS . 5. Wait IDD is affected linearly by the OSC2 capacitance. IDD 1.8 0.8 2.0 8.0 8.0 5.0 10.0 mA mA µA µA Input current(6) (with pullups disabled) PA0–PA7, PB0–PB7, PC0–PC7,RESET, OSC1, XOSC1 6. Input current measured with output transistor turned off and VIn = 0 V. IIn —— ± 1.0 µA Input current(6) (with pullups enabled, VDD = 3.3 V) PA0–PA7 PB0–PB7 PC0–PC7 IIn 300 230 230 760 µA µA µA LCD pin output impedance FP0–FP26 BP0–BP3 Zo, FP Zo, BP kΩ kΩ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68HC(7)05L5 — Rev. 2.0 General Release Specification MOTOROLA MC68HC705L5 197 NON-DISCLOSURE AGREEMENT REQUIRED A.15.4 3.3-Volt and 5.0-Volt Control Timing Characteristic(1) 1. +3.0≤ VDD ≤ +5.5 Vdc, VSS = 0 Vdc,TL ≤ TA ≤ TH , unless otherwise noted. Symbol Min Max Unit Frequency of oscillation (OSC) Crystal External Clock fOSC — dc 4.2 4.2 MHz Internal operating frequency(2), crystal or external clock (fOSC /2) VDD = 4.5 V to 5.5 V VDD = 3.0 V to 5.5 V 2. The system clock divider configuration (SYS1–SYS0 bits) should be selected such that the internal operating frequency (fOP ) does not exceed value specified in fOP for a given fOSC . fOP — 2.1 1.0 MHz Cycle time (fast OSC selected) VDD = 4.5 V to 5.5 V VDD = 3.0 V to 5.5 V tcyc 480 1.0 ns µs RESET pulse width (when bus clock active) t RL 1.5 — t cyc Timer Resolution Input capture (TCAP) pulse width tRESL tTH , tTL 4.0 284 tcyc ns Interrupt pulse width low (edge-triggered) t ILIH 284 — ns Interrupt pulse period(3) 3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc. tILIL see note — t cyc OSC1 pulse width (external clock input) t OH , tOL 110 — ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NON-DISCLOSURE AGREEMENT REQUIRED MC68HC705L5 General Release Specification MC68HC(7)05L5 — Rev. 2.0

198 MC68HC705L5 MOTOROLA

A.16 MC Order Number Table A-4 shows the MC order number for the available package type. Table A-4. MC Order Number Package Type Operating Temperature Range MC Order Number 80-pin plastic quad flat pack (QFP) 0 °C to +70°C MC68HC705L5FU Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

© Motorola, Inc., 1998 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized foruse as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P .O. Box 5405, Denver, Colorado 80217, 1-800-441-2447 or 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 03-5487-8488 TOUCHTONE, 1-602-244-6609; US and Canada ONL Y , 1-800-774-1848 HOME PAGE: http://motorola.com/sps/ Mfax is a trademark of Motorola, Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...